183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0
2316328f5SSimon Glass /*
3316328f5SSimon Glass * Copyright (c) 2015, Google, Inc
4316328f5SSimon Glass * Written by Simon Glass <sjg@chromium.org>
5316328f5SSimon Glass * All rights reserved.
6316328f5SSimon Glass */
7316328f5SSimon Glass
8316328f5SSimon Glass #include <common.h>
9555a3472SStefan Roese #include <dm.h>
10316328f5SSimon Glass #include <pci.h>
11316328f5SSimon Glass #include <usb.h>
12316328f5SSimon Glass #include "xhci.h"
13316328f5SSimon Glass
xhci_pci_init(struct udevice * dev,struct xhci_hccr ** ret_hccr,struct xhci_hcor ** ret_hcor)14555a3472SStefan Roese static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
15555a3472SStefan Roese struct xhci_hcor **ret_hcor)
16555a3472SStefan Roese {
17555a3472SStefan Roese struct xhci_hccr *hccr;
18555a3472SStefan Roese struct xhci_hcor *hcor;
19555a3472SStefan Roese u32 cmd;
20555a3472SStefan Roese
21555a3472SStefan Roese hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
22555a3472SStefan Roese PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
23555a3472SStefan Roese hcor = (struct xhci_hcor *)((uintptr_t) hccr +
24555a3472SStefan Roese HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
25555a3472SStefan Roese
26*9fddf6c7SBin Meng debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n",
27*9fddf6c7SBin Meng hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
28555a3472SStefan Roese
29555a3472SStefan Roese *ret_hccr = hccr;
30555a3472SStefan Roese *ret_hcor = hcor;
31555a3472SStefan Roese
32555a3472SStefan Roese /* enable busmaster */
33555a3472SStefan Roese dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
34555a3472SStefan Roese cmd |= PCI_COMMAND_MASTER;
35555a3472SStefan Roese dm_pci_write_config32(dev, PCI_COMMAND, cmd);
36555a3472SStefan Roese }
37555a3472SStefan Roese
xhci_pci_probe(struct udevice * dev)38555a3472SStefan Roese static int xhci_pci_probe(struct udevice *dev)
39555a3472SStefan Roese {
40555a3472SStefan Roese struct xhci_hccr *hccr;
41555a3472SStefan Roese struct xhci_hcor *hcor;
42555a3472SStefan Roese
43555a3472SStefan Roese xhci_pci_init(dev, &hccr, &hcor);
44555a3472SStefan Roese
45555a3472SStefan Roese return xhci_register(dev, hccr, hcor);
46555a3472SStefan Roese }
47555a3472SStefan Roese
48555a3472SStefan Roese static const struct udevice_id xhci_pci_ids[] = {
49555a3472SStefan Roese { .compatible = "xhci-pci" },
50555a3472SStefan Roese { }
51555a3472SStefan Roese };
52555a3472SStefan Roese
53555a3472SStefan Roese U_BOOT_DRIVER(xhci_pci) = {
54555a3472SStefan Roese .name = "xhci_pci",
55555a3472SStefan Roese .id = UCLASS_USB,
56555a3472SStefan Roese .probe = xhci_pci_probe,
575e941943SBin Meng .remove = xhci_deregister,
58555a3472SStefan Roese .of_match = xhci_pci_ids,
59555a3472SStefan Roese .ops = &xhci_usb_ops,
60555a3472SStefan Roese .platdata_auto_alloc_size = sizeof(struct usb_platdata),
615e941943SBin Meng .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
62555a3472SStefan Roese .flags = DM_FLAG_ALLOC_PRIV_DMA,
63555a3472SStefan Roese };
64555a3472SStefan Roese
65555a3472SStefan Roese static struct pci_device_id xhci_pci_supported[] = {
66555a3472SStefan Roese { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) },
67555a3472SStefan Roese {},
68555a3472SStefan Roese };
69555a3472SStefan Roese
70555a3472SStefan Roese U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported);
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