1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2732c7c24SAjay Bhargav /*
3732c7c24SAjay Bhargav * (C) Copyright 2012
4732c7c24SAjay Bhargav * eInfochips Ltd. <www.einfochips.com>
5c7c47ca2SAjay Bhargav * Written-by: Ajay Bhargav <contact@8051projects.net>
6732c7c24SAjay Bhargav *
7732c7c24SAjay Bhargav * (C) Copyright 2009
8732c7c24SAjay Bhargav * Marvell Semiconductor <www.marvell.com>
9732c7c24SAjay Bhargav */
10732c7c24SAjay Bhargav
11732c7c24SAjay Bhargav #include <common.h>
12732c7c24SAjay Bhargav #include <asm/io.h>
13732c7c24SAjay Bhargav #include <usb.h>
14732c7c24SAjay Bhargav #include <asm/arch/cpu.h>
15732c7c24SAjay Bhargav #include <asm/arch/armada100.h>
16732c7c24SAjay Bhargav #include <asm/arch/utmi-armada100.h>
17732c7c24SAjay Bhargav
utmi_phy_init(void)18732c7c24SAjay Bhargav static int utmi_phy_init(void)
19732c7c24SAjay Bhargav {
20732c7c24SAjay Bhargav struct armd1usb_phy_reg *phy_regs =
21732c7c24SAjay Bhargav (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
22732c7c24SAjay Bhargav int timeout;
23732c7c24SAjay Bhargav
24732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
25732c7c24SAjay Bhargav udelay(1000);
26732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
27732c7c24SAjay Bhargav
28732c7c24SAjay Bhargav clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
29732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
30732c7c24SAjay Bhargav
31732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
32732c7c24SAjay Bhargav
33732c7c24SAjay Bhargav /* Calibrate pll */
34732c7c24SAjay Bhargav timeout = 10000;
35732c7c24SAjay Bhargav while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
36732c7c24SAjay Bhargav ;
37732c7c24SAjay Bhargav if (!timeout)
38732c7c24SAjay Bhargav return -1;
39732c7c24SAjay Bhargav
40732c7c24SAjay Bhargav udelay(200);
41732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
42732c7c24SAjay Bhargav udelay(400);
43732c7c24SAjay Bhargav clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
44732c7c24SAjay Bhargav
45732c7c24SAjay Bhargav udelay(200);
46732c7c24SAjay Bhargav setbits_le32(&phy_regs->utmi_tx, RCAL_START);
47732c7c24SAjay Bhargav udelay(400);
48732c7c24SAjay Bhargav clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
49732c7c24SAjay Bhargav
50732c7c24SAjay Bhargav timeout = 10000;
51732c7c24SAjay Bhargav while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
52732c7c24SAjay Bhargav ;
53732c7c24SAjay Bhargav if (!timeout)
54732c7c24SAjay Bhargav return -1;
55732c7c24SAjay Bhargav
56732c7c24SAjay Bhargav return 0;
57732c7c24SAjay Bhargav }
58732c7c24SAjay Bhargav
59732c7c24SAjay Bhargav /*
60732c7c24SAjay Bhargav * Initialize USB host controller's UTMI Physical interface
61732c7c24SAjay Bhargav */
utmi_init(void)62732c7c24SAjay Bhargav int utmi_init(void)
63732c7c24SAjay Bhargav {
64732c7c24SAjay Bhargav struct armd1mpmu_registers *mpmu_regs =
65732c7c24SAjay Bhargav (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
66732c7c24SAjay Bhargav
67732c7c24SAjay Bhargav struct armd1apmu_registers *apmu_regs =
68732c7c24SAjay Bhargav (struct armd1apmu_registers *)ARMD1_APMU_BASE;
69732c7c24SAjay Bhargav
70732c7c24SAjay Bhargav /* Turn on 26Mhz ref clock for UTMI PLL */
71732c7c24SAjay Bhargav setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
72732c7c24SAjay Bhargav
73732c7c24SAjay Bhargav /* USB Clock reset */
74732c7c24SAjay Bhargav writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
75732c7c24SAjay Bhargav writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
76732c7c24SAjay Bhargav
77732c7c24SAjay Bhargav /* Initialize UTMI transceiver */
78732c7c24SAjay Bhargav return utmi_phy_init();
79732c7c24SAjay Bhargav }
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