1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. 3 * 4 * Interrupt support is added. Now, it has been tested 5 * on ULI1575 chip and works well with USB keyboard. 6 * 7 * (C) Copyright 2007 8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> 9 * 10 * (C) Copyright 2003 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> 12 * 13 * Note: Much of this code has been derived from Linux 2.4 14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 15 * (C) Copyright 2000-2002 David Brownell 16 * 17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 18 * ebenard@eukrea.com - based on s3c24x0's driver 19 * 20 * SPDX-License-Identifier: GPL-2.0+ 21 */ 22 /* 23 * IMPORTANT NOTES 24 * 1 - Read doc/README.generic_usb_ohci 25 * 2 - this driver is intended for use with USB Mass Storage Devices 26 * (BBB) and USB keyboard. There is NO support for Isochronous pipes! 27 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG 28 * to activate workaround for bug #41 or this driver will NOT work! 29 */ 30 31 #include <common.h> 32 #include <asm/byteorder.h> 33 34 #if defined(CONFIG_PCI_OHCI) 35 # include <pci.h> 36 #if !defined(CONFIG_PCI_OHCI_DEVNO) 37 #define CONFIG_PCI_OHCI_DEVNO 0 38 #endif 39 #endif 40 41 #include <malloc.h> 42 #include <usb.h> 43 44 #include "ohci.h" 45 46 #ifdef CONFIG_AT91RM9200 47 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ 48 #endif 49 50 #if defined(CONFIG_CPU_ARM920T) || \ 51 defined(CONFIG_S3C24X0) || \ 52 defined(CONFIG_440EP) || \ 53 defined(CONFIG_PCI_OHCI) || \ 54 defined(CONFIG_MPC5200) || \ 55 defined(CONFIG_SYS_OHCI_USE_NPS) 56 # define OHCI_USE_NPS /* force NoPowerSwitching mode */ 57 #endif 58 59 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 60 #undef DEBUG 61 #undef SHOW_INFO 62 #undef OHCI_FILL_TRACE 63 64 /* For initializing controller (mask in an HCFS mode too) */ 65 #define OHCI_CONTROL_INIT \ 66 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 67 68 #ifdef CONFIG_PCI_OHCI 69 static struct pci_device_id ohci_pci_ids[] = { 70 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ 71 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ 72 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ 73 /* Please add supported PCI OHCI controller ids here */ 74 {0, 0} 75 }; 76 #endif 77 78 #ifdef CONFIG_PCI_EHCI_DEVNO 79 static struct pci_device_id ehci_pci_ids[] = { 80 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ 81 /* Please add supported PCI EHCI controller ids here */ 82 {0, 0} 83 }; 84 #endif 85 86 #ifdef DEBUG 87 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 88 #else 89 #define dbg(format, arg...) do {} while (0) 90 #endif /* DEBUG */ 91 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 92 #ifdef SHOW_INFO 93 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 94 #else 95 #define info(format, arg...) do {} while (0) 96 #endif 97 98 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER 99 # define m16_swap(x) cpu_to_be16(x) 100 # define m32_swap(x) cpu_to_be32(x) 101 #else 102 # define m16_swap(x) cpu_to_le16(x) 103 # define m32_swap(x) cpu_to_le32(x) 104 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ 105 106 #ifdef CONFIG_DM_USB 107 /* 108 * We really should do proper cache flushing everywhere, but for now we only 109 * do it for new (driver-model) usb code to avoid regressions. 110 */ 111 #define flush_dcache_buffer(addr, size) \ 112 flush_dcache_range((unsigned long)(addr), \ 113 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 114 #define invalidate_dcache_buffer(addr, size) \ 115 invalidate_dcache_range((unsigned long)(addr), \ 116 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 117 #else 118 #define flush_dcache_buffer(addr, size) 119 #define invalidate_dcache_buffer(addr, size) 120 #endif 121 122 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ 123 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) 124 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) 125 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) 126 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) 127 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) 128 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) 129 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) 130 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) 131 132 #ifdef CONFIG_DM_USB 133 /* 134 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep 135 * them around when building for older boards not yet converted to the dm 136 * just in case (to avoid regressions), for dm this turns them into nops. 137 */ 138 #define ohci_mdelay(x) 139 #else 140 #define ohci_mdelay(x) mdelay(x) 141 #endif 142 143 /* global ohci_t */ 144 static ohci_t gohci; 145 /* this must be aligned to a 256 byte boundary */ 146 struct ohci_hcca ghcca[1]; 147 148 /* mapping of the OHCI CC status to error codes */ 149 static int cc_to_error[16] = { 150 /* No Error */ 0, 151 /* CRC Error */ USB_ST_CRC_ERR, 152 /* Bit Stuff */ USB_ST_BIT_ERR, 153 /* Data Togg */ USB_ST_CRC_ERR, 154 /* Stall */ USB_ST_STALLED, 155 /* DevNotResp */ -1, 156 /* PIDCheck */ USB_ST_BIT_ERR, 157 /* UnExpPID */ USB_ST_BIT_ERR, 158 /* DataOver */ USB_ST_BUF_ERR, 159 /* DataUnder */ USB_ST_BUF_ERR, 160 /* reservd */ -1, 161 /* reservd */ -1, 162 /* BufferOver */ USB_ST_BUF_ERR, 163 /* BuffUnder */ USB_ST_BUF_ERR, 164 /* Not Access */ -1, 165 /* Not Access */ -1 166 }; 167 168 static const char *cc_to_string[16] = { 169 "No Error", 170 "CRC: Last data packet from endpoint contained a CRC error.", 171 "BITSTUFFING: Last data packet from endpoint contained a bit " \ 172 "stuffing violation", 173 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ 174 "that did not match the expected value.", 175 "STALL: TD was moved to the Done Queue because the endpoint returned" \ 176 " a STALL PID", 177 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ 178 "not provide a handshake (OUT)", 179 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ 180 "(IN) or handshake (OUT)", 181 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ 182 "value is not defined.", 183 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ 184 "either the size of the maximum data packet allowed\n" \ 185 "from the endpoint (found in MaximumPacketSize field\n" \ 186 "of ED) or the remaining buffer size.", 187 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ 188 "and that amount was not sufficient to fill the\n" \ 189 "specified buffer", 190 "reserved1", 191 "reserved2", 192 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ 193 "than it could be written to system memory", 194 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ 195 "system memory fast enough to keep up with data USB " \ 196 "data rate.", 197 "NOT ACCESSED: This code is set by software before the TD is placed" \ 198 "on a list to be processed by the HC.(1)", 199 "NOT ACCESSED: This code is set by software before the TD is placed" \ 200 "on a list to be processed by the HC.(2)", 201 }; 202 203 static inline u32 roothub_a(struct ohci *hc) 204 { return ohci_readl(&hc->regs->roothub.a); } 205 static inline u32 roothub_b(struct ohci *hc) 206 { return ohci_readl(&hc->regs->roothub.b); } 207 static inline u32 roothub_status(struct ohci *hc) 208 { return ohci_readl(&hc->regs->roothub.status); } 209 static inline u32 roothub_portstatus(struct ohci *hc, int i) 210 { return ohci_readl(&hc->regs->roothub.portstatus[i]); } 211 212 /* forward declaration */ 213 static int hc_interrupt(ohci_t *ohci); 214 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 215 unsigned long pipe, void *buffer, int transfer_len, 216 struct devrequest *setup, urb_priv_t *urb, 217 int interval); 218 static int ep_link(ohci_t * ohci, ed_t * ed); 219 static int ep_unlink(ohci_t * ohci, ed_t * ed); 220 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 221 unsigned long pipe, int interval, int load); 222 223 /*-------------------------------------------------------------------------*/ 224 225 /* TDs ... */ 226 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) 227 { 228 int i; 229 struct td *td; 230 231 td = NULL; 232 for (i = 0; i < NUM_TD; i++) 233 { 234 if (ohci_dev->tds[i].usb_dev == NULL) 235 { 236 td = &ohci_dev->tds[i]; 237 td->usb_dev = usb_dev; 238 break; 239 } 240 } 241 242 return td; 243 } 244 245 static inline void ed_free(struct ed *ed) 246 { 247 ed->usb_dev = NULL; 248 } 249 250 /*-------------------------------------------------------------------------* 251 * URB support functions 252 *-------------------------------------------------------------------------*/ 253 254 /* free HCD-private data associated with this URB */ 255 256 static void urb_free_priv(urb_priv_t *urb) 257 { 258 int i; 259 int last; 260 struct td *td; 261 262 last = urb->length - 1; 263 if (last >= 0) { 264 for (i = 0; i <= last; i++) { 265 td = urb->td[i]; 266 if (td) { 267 td->usb_dev = NULL; 268 urb->td[i] = NULL; 269 } 270 } 271 } 272 free(urb); 273 } 274 275 /*-------------------------------------------------------------------------*/ 276 277 #ifdef DEBUG 278 static int sohci_get_current_frame_number(ohci_t *ohci); 279 280 /* debug| print the main components of an URB 281 * small: 0) header + data packets 1) just header */ 282 283 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, 284 unsigned long pipe, void *buffer, int transfer_len, 285 struct devrequest *setup, char *str, int small) 286 { 287 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", 288 str, 289 sohci_get_current_frame_number(ohci), 290 usb_pipedevice(pipe), 291 usb_pipeendpoint(pipe), 292 usb_pipeout(pipe)? 'O': 'I', 293 usb_pipetype(pipe) < 2 ? \ 294 (usb_pipeint(pipe)? "INTR": "ISOC"): \ 295 (usb_pipecontrol(pipe)? "CTRL": "BULK"), 296 (purb ? purb->actual_length : 0), 297 transfer_len, dev->status); 298 #ifdef OHCI_VERBOSE_DEBUG 299 if (!small) { 300 int i, len; 301 302 if (usb_pipecontrol(pipe)) { 303 printf(__FILE__ ": cmd(8):"); 304 for (i = 0; i < 8 ; i++) 305 printf(" %02x", ((__u8 *) setup) [i]); 306 printf("\n"); 307 } 308 if (transfer_len > 0 && buffer) { 309 printf(__FILE__ ": data(%d/%d):", 310 (purb ? purb->actual_length : 0), 311 transfer_len); 312 len = usb_pipeout(pipe)? transfer_len: 313 (purb ? purb->actual_length : 0); 314 for (i = 0; i < 16 && i < len; i++) 315 printf(" %02x", ((__u8 *) buffer) [i]); 316 printf("%s\n", i < len? "...": ""); 317 } 318 } 319 #endif 320 } 321 322 /* just for debugging; prints non-empty branches of the int ed tree 323 * inclusive iso eds */ 324 void ep_print_int_eds(ohci_t *ohci, char *str) 325 { 326 int i, j; 327 __u32 *ed_p; 328 for (i = 0; i < 32; i++) { 329 j = 5; 330 ed_p = &(ohci->hcca->int_table [i]); 331 if (*ed_p == 0) 332 continue; 333 invalidate_dcache_ed(ed_p); 334 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); 335 while (*ed_p != 0 && j--) { 336 ed_t *ed = (ed_t *)m32_swap(ed_p); 337 invalidate_dcache_ed(ed); 338 printf(" ed: %4x;", ed->hwINFO); 339 ed_p = &ed->hwNextED; 340 } 341 printf("\n"); 342 } 343 } 344 345 static void ohci_dump_intr_mask(char *label, __u32 mask) 346 { 347 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 348 label, 349 mask, 350 (mask & OHCI_INTR_MIE) ? " MIE" : "", 351 (mask & OHCI_INTR_OC) ? " OC" : "", 352 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 353 (mask & OHCI_INTR_FNO) ? " FNO" : "", 354 (mask & OHCI_INTR_UE) ? " UE" : "", 355 (mask & OHCI_INTR_RD) ? " RD" : "", 356 (mask & OHCI_INTR_SF) ? " SF" : "", 357 (mask & OHCI_INTR_WDH) ? " WDH" : "", 358 (mask & OHCI_INTR_SO) ? " SO" : "" 359 ); 360 } 361 362 static void maybe_print_eds(char *label, __u32 value) 363 { 364 ed_t *edp = (ed_t *)value; 365 366 if (value) { 367 dbg("%s %08x", label, value); 368 invalidate_dcache_ed(edp); 369 dbg("%08x", edp->hwINFO); 370 dbg("%08x", edp->hwTailP); 371 dbg("%08x", edp->hwHeadP); 372 dbg("%08x", edp->hwNextED); 373 } 374 } 375 376 static char *hcfs2string(int state) 377 { 378 switch (state) { 379 case OHCI_USB_RESET: return "reset"; 380 case OHCI_USB_RESUME: return "resume"; 381 case OHCI_USB_OPER: return "operational"; 382 case OHCI_USB_SUSPEND: return "suspend"; 383 } 384 return "?"; 385 } 386 387 /* dump control and status registers */ 388 static void ohci_dump_status(ohci_t *controller) 389 { 390 struct ohci_regs *regs = controller->regs; 391 __u32 temp; 392 393 temp = ohci_readl(®s->revision) & 0xff; 394 if (temp != 0x10) 395 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); 396 397 temp = ohci_readl(®s->control); 398 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 399 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 400 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 401 (temp & OHCI_CTRL_IR) ? " IR" : "", 402 hcfs2string(temp & OHCI_CTRL_HCFS), 403 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 404 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 405 (temp & OHCI_CTRL_IE) ? " IE" : "", 406 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 407 temp & OHCI_CTRL_CBSR 408 ); 409 410 temp = ohci_readl(®s->cmdstatus); 411 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 412 (temp & OHCI_SOC) >> 16, 413 (temp & OHCI_OCR) ? " OCR" : "", 414 (temp & OHCI_BLF) ? " BLF" : "", 415 (temp & OHCI_CLF) ? " CLF" : "", 416 (temp & OHCI_HCR) ? " HCR" : "" 417 ); 418 419 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); 420 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); 421 422 maybe_print_eds("ed_periodcurrent", 423 ohci_readl(®s->ed_periodcurrent)); 424 425 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); 426 maybe_print_eds("ed_controlcurrent", 427 ohci_readl(®s->ed_controlcurrent)); 428 429 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); 430 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); 431 432 maybe_print_eds("donehead", ohci_readl(®s->donehead)); 433 } 434 435 static void ohci_dump_roothub(ohci_t *controller, int verbose) 436 { 437 __u32 temp, ndp, i; 438 439 temp = roothub_a(controller); 440 ndp = (temp & RH_A_NDP); 441 #ifdef CONFIG_AT91C_PQFP_UHPBUG 442 ndp = (ndp == 2) ? 1:0; 443 #endif 444 if (verbose) { 445 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 446 ((temp & RH_A_POTPGT) >> 24) & 0xff, 447 (temp & RH_A_NOCP) ? " NOCP" : "", 448 (temp & RH_A_OCPM) ? " OCPM" : "", 449 (temp & RH_A_DT) ? " DT" : "", 450 (temp & RH_A_NPS) ? " NPS" : "", 451 (temp & RH_A_PSM) ? " PSM" : "", 452 ndp 453 ); 454 temp = roothub_b(controller); 455 dbg("roothub.b: %08x PPCM=%04x DR=%04x", 456 temp, 457 (temp & RH_B_PPCM) >> 16, 458 (temp & RH_B_DR) 459 ); 460 temp = roothub_status(controller); 461 dbg("roothub.status: %08x%s%s%s%s%s%s", 462 temp, 463 (temp & RH_HS_CRWE) ? " CRWE" : "", 464 (temp & RH_HS_OCIC) ? " OCIC" : "", 465 (temp & RH_HS_LPSC) ? " LPSC" : "", 466 (temp & RH_HS_DRWE) ? " DRWE" : "", 467 (temp & RH_HS_OCI) ? " OCI" : "", 468 (temp & RH_HS_LPS) ? " LPS" : "" 469 ); 470 } 471 472 for (i = 0; i < ndp; i++) { 473 temp = roothub_portstatus(controller, i); 474 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 475 i, 476 temp, 477 (temp & RH_PS_PRSC) ? " PRSC" : "", 478 (temp & RH_PS_OCIC) ? " OCIC" : "", 479 (temp & RH_PS_PSSC) ? " PSSC" : "", 480 (temp & RH_PS_PESC) ? " PESC" : "", 481 (temp & RH_PS_CSC) ? " CSC" : "", 482 483 (temp & RH_PS_LSDA) ? " LSDA" : "", 484 (temp & RH_PS_PPS) ? " PPS" : "", 485 (temp & RH_PS_PRS) ? " PRS" : "", 486 (temp & RH_PS_POCI) ? " POCI" : "", 487 (temp & RH_PS_PSS) ? " PSS" : "", 488 489 (temp & RH_PS_PES) ? " PES" : "", 490 (temp & RH_PS_CCS) ? " CCS" : "" 491 ); 492 } 493 } 494 495 static void ohci_dump(ohci_t *controller, int verbose) 496 { 497 dbg("OHCI controller usb-%s state", controller->slot_name); 498 499 /* dumps some of the state we know about */ 500 ohci_dump_status(controller); 501 if (verbose) 502 ep_print_int_eds(controller, "hcca"); 503 invalidate_dcache_hcca(controller->hcca); 504 dbg("hcca frame #%04x", controller->hcca->frame_no); 505 ohci_dump_roothub(controller, 1); 506 } 507 #endif /* DEBUG */ 508 509 /*-------------------------------------------------------------------------* 510 * Interface functions (URB) 511 *-------------------------------------------------------------------------*/ 512 513 /* get a transfer request */ 514 515 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, 516 struct devrequest *setup) 517 { 518 ed_t *ed; 519 urb_priv_t *purb_priv = urb; 520 int i, size = 0; 521 struct usb_device *dev = urb->dev; 522 unsigned long pipe = urb->pipe; 523 void *buffer = urb->transfer_buffer; 524 int transfer_len = urb->transfer_buffer_length; 525 int interval = urb->interval; 526 527 /* when controller's hung, permit only roothub cleanup attempts 528 * such as powering down ports */ 529 if (ohci->disabled) { 530 err("sohci_submit_job: EPIPE"); 531 return -1; 532 } 533 534 /* we're about to begin a new transaction here so mark the 535 * URB unfinished */ 536 urb->finished = 0; 537 538 /* every endpoint has a ed, locate and fill it */ 539 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); 540 if (!ed) { 541 err("sohci_submit_job: ENOMEM"); 542 return -1; 543 } 544 545 /* for the private part of the URB we need the number of TDs (size) */ 546 switch (usb_pipetype(pipe)) { 547 case PIPE_BULK: /* one TD for every 4096 Byte */ 548 size = (transfer_len - 1) / 4096 + 1; 549 break; 550 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 551 size = (transfer_len == 0)? 2: 552 (transfer_len - 1) / 4096 + 3; 553 break; 554 case PIPE_INTERRUPT: /* 1 TD */ 555 size = 1; 556 break; 557 } 558 559 ed->purb = urb; 560 561 if (size >= (N_URB_TD - 1)) { 562 err("need %d TDs, only have %d", size, N_URB_TD); 563 return -1; 564 } 565 purb_priv->pipe = pipe; 566 567 /* fill the private part of the URB */ 568 purb_priv->length = size; 569 purb_priv->ed = ed; 570 purb_priv->actual_length = 0; 571 572 /* allocate the TDs */ 573 /* note that td[0] was allocated in ep_add_ed */ 574 for (i = 0; i < size; i++) { 575 purb_priv->td[i] = td_alloc(ohci_dev, dev); 576 if (!purb_priv->td[i]) { 577 purb_priv->length = i; 578 urb_free_priv(purb_priv); 579 err("sohci_submit_job: ENOMEM"); 580 return -1; 581 } 582 } 583 584 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 585 urb_free_priv(purb_priv); 586 err("sohci_submit_job: EINVAL"); 587 return -1; 588 } 589 590 /* link the ed into a chain if is not already */ 591 if (ed->state != ED_OPER) 592 ep_link(ohci, ed); 593 594 /* fill the TDs and link it to the ed */ 595 td_submit_job(ohci, dev, pipe, buffer, transfer_len, 596 setup, purb_priv, interval); 597 598 return 0; 599 } 600 601 /*-------------------------------------------------------------------------*/ 602 603 #ifdef DEBUG 604 /* tell us the current USB frame number */ 605 static int sohci_get_current_frame_number(ohci_t *ohci) 606 { 607 invalidate_dcache_hcca(ohci->hcca); 608 return m16_swap(ohci->hcca->frame_no); 609 } 610 #endif 611 612 /*-------------------------------------------------------------------------* 613 * ED handling functions 614 *-------------------------------------------------------------------------*/ 615 616 /* search for the right branch to insert an interrupt ed into the int tree 617 * do some load ballancing; 618 * returns the branch and 619 * sets the interval to interval = 2^integer (ld (interval)) */ 620 621 static int ep_int_ballance(ohci_t *ohci, int interval, int load) 622 { 623 int i, branch = 0; 624 625 /* search for the least loaded interrupt endpoint 626 * branch of all 32 branches 627 */ 628 for (i = 0; i < 32; i++) 629 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) 630 branch = i; 631 632 branch = branch % interval; 633 for (i = branch; i < 32; i += interval) 634 ohci->ohci_int_load [i] += load; 635 636 return branch; 637 } 638 639 /*-------------------------------------------------------------------------*/ 640 641 /* 2^int( ld (inter)) */ 642 643 static int ep_2_n_interval(int inter) 644 { 645 int i; 646 for (i = 0; ((inter >> i) > 1) && (i < 5); i++); 647 return 1 << i; 648 } 649 650 /*-------------------------------------------------------------------------*/ 651 652 /* the int tree is a binary tree 653 * in order to process it sequentially the indexes of the branches have to 654 * be mapped the mapping reverses the bits of a word of num_bits length */ 655 static int ep_rev(int num_bits, int word) 656 { 657 int i, wout = 0; 658 659 for (i = 0; i < num_bits; i++) 660 wout |= (((word >> i) & 1) << (num_bits - i - 1)); 661 return wout; 662 } 663 664 /*-------------------------------------------------------------------------* 665 * ED handling functions 666 *-------------------------------------------------------------------------*/ 667 668 /* link an ed into one of the HC chains */ 669 670 static int ep_link(ohci_t *ohci, ed_t *edi) 671 { 672 volatile ed_t *ed = edi; 673 int int_branch; 674 int i; 675 int inter; 676 int interval; 677 int load; 678 __u32 *ed_p; 679 680 ed->state = ED_OPER; 681 ed->int_interval = 0; 682 683 switch (ed->type) { 684 case PIPE_CONTROL: 685 ed->hwNextED = 0; 686 flush_dcache_ed(ed); 687 if (ohci->ed_controltail == NULL) 688 ohci_writel(ed, &ohci->regs->ed_controlhead); 689 else 690 ohci->ed_controltail->hwNextED = 691 m32_swap((unsigned long)ed); 692 693 ed->ed_prev = ohci->ed_controltail; 694 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 695 !ohci->ed_rm_list[1] && !ohci->sleeping) { 696 ohci->hc_control |= OHCI_CTRL_CLE; 697 ohci_writel(ohci->hc_control, &ohci->regs->control); 698 } 699 ohci->ed_controltail = edi; 700 break; 701 702 case PIPE_BULK: 703 ed->hwNextED = 0; 704 flush_dcache_ed(ed); 705 if (ohci->ed_bulktail == NULL) 706 ohci_writel(ed, &ohci->regs->ed_bulkhead); 707 else 708 ohci->ed_bulktail->hwNextED = 709 m32_swap((unsigned long)ed); 710 711 ed->ed_prev = ohci->ed_bulktail; 712 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 713 !ohci->ed_rm_list[1] && !ohci->sleeping) { 714 ohci->hc_control |= OHCI_CTRL_BLE; 715 ohci_writel(ohci->hc_control, &ohci->regs->control); 716 } 717 ohci->ed_bulktail = edi; 718 break; 719 720 case PIPE_INTERRUPT: 721 load = ed->int_load; 722 interval = ep_2_n_interval(ed->int_period); 723 ed->int_interval = interval; 724 int_branch = ep_int_ballance(ohci, interval, load); 725 ed->int_branch = int_branch; 726 727 for (i = 0; i < ep_rev(6, interval); i += inter) { 728 inter = 1; 729 for (ed_p = &(ohci->hcca->int_table[\ 730 ep_rev(5, i) + int_branch]); 731 (*ed_p != 0) && 732 (((ed_t *)ed_p)->int_interval >= interval); 733 ed_p = &(((ed_t *)ed_p)->hwNextED)) 734 inter = ep_rev(6, 735 ((ed_t *)ed_p)->int_interval); 736 ed->hwNextED = *ed_p; 737 flush_dcache_ed(ed); 738 *ed_p = m32_swap((unsigned long)ed); 739 flush_dcache_hcca(ohci->hcca); 740 } 741 break; 742 } 743 return 0; 744 } 745 746 /*-------------------------------------------------------------------------*/ 747 748 /* scan the periodic table to find and unlink this ED */ 749 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, 750 unsigned index, unsigned period) 751 { 752 __maybe_unused unsigned long aligned_ed_p; 753 754 for (; index < NUM_INTS; index += period) { 755 __u32 *ed_p = &ohci->hcca->int_table [index]; 756 757 /* ED might have been unlinked through another path */ 758 while (*ed_p != 0) { 759 if (((struct ed *) 760 m32_swap((unsigned long)ed_p)) == ed) { 761 *ed_p = ed->hwNextED; 762 #ifdef CONFIG_DM_USB 763 aligned_ed_p = (unsigned long)ed_p; 764 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); 765 flush_dcache_range(aligned_ed_p, 766 aligned_ed_p + ARCH_DMA_MINALIGN); 767 #endif 768 break; 769 } 770 ed_p = &(((struct ed *) 771 m32_swap((unsigned long)ed_p))->hwNextED); 772 } 773 } 774 } 775 776 /* unlink an ed from one of the HC chains. 777 * just the link to the ed is unlinked. 778 * the link from the ed still points to another operational ed or 0 779 * so the HC can eventually finish the processing of the unlinked ed */ 780 781 static int ep_unlink(ohci_t *ohci, ed_t *edi) 782 { 783 volatile ed_t *ed = edi; 784 int i; 785 786 ed->hwINFO |= m32_swap(OHCI_ED_SKIP); 787 flush_dcache_ed(ed); 788 789 switch (ed->type) { 790 case PIPE_CONTROL: 791 if (ed->ed_prev == NULL) { 792 if (!ed->hwNextED) { 793 ohci->hc_control &= ~OHCI_CTRL_CLE; 794 ohci_writel(ohci->hc_control, 795 &ohci->regs->control); 796 } 797 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 798 &ohci->regs->ed_controlhead); 799 } else { 800 ed->ed_prev->hwNextED = ed->hwNextED; 801 flush_dcache_ed(ed->ed_prev); 802 } 803 if (ohci->ed_controltail == ed) { 804 ohci->ed_controltail = ed->ed_prev; 805 } else { 806 ((ed_t *)m32_swap( 807 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 808 } 809 break; 810 811 case PIPE_BULK: 812 if (ed->ed_prev == NULL) { 813 if (!ed->hwNextED) { 814 ohci->hc_control &= ~OHCI_CTRL_BLE; 815 ohci_writel(ohci->hc_control, 816 &ohci->regs->control); 817 } 818 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 819 &ohci->regs->ed_bulkhead); 820 } else { 821 ed->ed_prev->hwNextED = ed->hwNextED; 822 flush_dcache_ed(ed->ed_prev); 823 } 824 if (ohci->ed_bulktail == ed) { 825 ohci->ed_bulktail = ed->ed_prev; 826 } else { 827 ((ed_t *)m32_swap( 828 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 829 } 830 break; 831 832 case PIPE_INTERRUPT: 833 periodic_unlink(ohci, ed, 0, 1); 834 for (i = ed->int_branch; i < 32; i += ed->int_interval) 835 ohci->ohci_int_load[i] -= ed->int_load; 836 break; 837 } 838 ed->state = ED_UNLINK; 839 return 0; 840 } 841 842 /*-------------------------------------------------------------------------*/ 843 844 /* add/reinit an endpoint; this should be done once at the 845 * usb_set_configuration command, but the USB stack is a little bit 846 * stateless so we do it at every transaction if the state of the ed 847 * is ED_NEW then a dummy td is added and the state is changed to 848 * ED_UNLINK in all other cases the state is left unchanged the ed 849 * info fields are setted anyway even though most of them should not 850 * change 851 */ 852 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 853 unsigned long pipe, int interval, int load) 854 { 855 td_t *td; 856 ed_t *ed_ret; 857 volatile ed_t *ed; 858 859 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | 860 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; 861 862 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 863 err("ep_add_ed: pending delete"); 864 /* pending delete request */ 865 return NULL; 866 } 867 868 if (ed->state == ED_NEW) { 869 /* dummy td; end of td list for ed */ 870 td = td_alloc(ohci_dev, usb_dev); 871 ed->hwTailP = m32_swap((unsigned long)td); 872 ed->hwHeadP = ed->hwTailP; 873 ed->state = ED_UNLINK; 874 ed->type = usb_pipetype(pipe); 875 ohci_dev->ed_cnt++; 876 } 877 878 ed->hwINFO = m32_swap(usb_pipedevice(pipe) 879 | usb_pipeendpoint(pipe) << 7 880 | (usb_pipeisoc(pipe)? 0x8000: 0) 881 | (usb_pipecontrol(pipe)? 0: \ 882 (usb_pipeout(pipe)? 0x800: 0x1000)) 883 | (usb_dev->speed == USB_SPEED_LOW) << 13 884 | usb_maxpacket(usb_dev, pipe) << 16); 885 886 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { 887 ed->int_period = interval; 888 ed->int_load = load; 889 } 890 891 flush_dcache_ed(ed); 892 893 return ed_ret; 894 } 895 896 /*-------------------------------------------------------------------------* 897 * TD handling functions 898 *-------------------------------------------------------------------------*/ 899 900 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 901 902 static void td_fill(ohci_t *ohci, unsigned int info, 903 void *data, int len, 904 struct usb_device *dev, int index, urb_priv_t *urb_priv) 905 { 906 volatile td_t *td, *td_pt; 907 #ifdef OHCI_FILL_TRACE 908 int i; 909 #endif 910 911 if (index > urb_priv->length) { 912 err("index > length"); 913 return; 914 } 915 /* use this td as the next dummy */ 916 td_pt = urb_priv->td [index]; 917 td_pt->hwNextTD = 0; 918 flush_dcache_td(td_pt); 919 920 /* fill the old dummy TD */ 921 td = urb_priv->td [index] = 922 (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); 923 924 td->ed = urb_priv->ed; 925 td->next_dl_td = NULL; 926 td->index = index; 927 td->data = (__u32)data; 928 #ifdef OHCI_FILL_TRACE 929 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { 930 for (i = 0; i < len; i++) 931 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); 932 printf("\n"); 933 } 934 #endif 935 if (!len) 936 data = 0; 937 938 td->hwINFO = m32_swap(info); 939 td->hwCBP = m32_swap((unsigned long)data); 940 if (data) 941 td->hwBE = m32_swap((unsigned long)(data + len - 1)); 942 else 943 td->hwBE = 0; 944 945 td->hwNextTD = m32_swap((unsigned long)td_pt); 946 flush_dcache_td(td); 947 948 /* append to queue */ 949 td->ed->hwTailP = td->hwNextTD; 950 flush_dcache_ed(td->ed); 951 } 952 953 /*-------------------------------------------------------------------------*/ 954 955 /* prepare all TDs of a transfer */ 956 957 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 958 unsigned long pipe, void *buffer, int transfer_len, 959 struct devrequest *setup, urb_priv_t *urb, 960 int interval) 961 { 962 int data_len = transfer_len; 963 void *data; 964 int cnt = 0; 965 __u32 info = 0; 966 unsigned int toggle = 0; 967 968 flush_dcache_buffer(buffer, data_len); 969 970 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle 971 * bits for reseting */ 972 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 973 toggle = TD_T_TOGGLE; 974 } else { 975 toggle = TD_T_DATA0; 976 usb_settoggle(dev, usb_pipeendpoint(pipe), 977 usb_pipeout(pipe), 1); 978 } 979 urb->td_cnt = 0; 980 if (data_len) 981 data = buffer; 982 else 983 data = 0; 984 985 switch (usb_pipetype(pipe)) { 986 case PIPE_BULK: 987 info = usb_pipeout(pipe)? 988 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 989 while (data_len > 4096) { 990 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), 991 data, 4096, dev, cnt, urb); 992 data += 4096; data_len -= 4096; cnt++; 993 } 994 info = usb_pipeout(pipe)? 995 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 996 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 997 data_len, dev, cnt, urb); 998 cnt++; 999 1000 if (!ohci->sleeping) { 1001 /* start bulk list */ 1002 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); 1003 } 1004 break; 1005 1006 case PIPE_CONTROL: 1007 /* Setup phase */ 1008 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 1009 flush_dcache_buffer(setup, 8); 1010 td_fill(ohci, info, setup, 8, dev, cnt++, urb); 1011 1012 /* Optional Data phase */ 1013 if (data_len > 0) { 1014 info = usb_pipeout(pipe)? 1015 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : 1016 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 1017 /* NOTE: mishandles transfers >8K, some >4K */ 1018 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1019 } 1020 1021 /* Status phase */ 1022 info = (usb_pipeout(pipe) || data_len == 0) ? 1023 TD_CC | TD_DP_IN | TD_T_DATA1: 1024 TD_CC | TD_DP_OUT | TD_T_DATA1; 1025 td_fill(ohci, info, data, 0, dev, cnt++, urb); 1026 1027 if (!ohci->sleeping) { 1028 /* start Control list */ 1029 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); 1030 } 1031 break; 1032 1033 case PIPE_INTERRUPT: 1034 info = usb_pipeout(urb->pipe)? 1035 TD_CC | TD_DP_OUT | toggle: 1036 TD_CC | TD_R | TD_DP_IN | toggle; 1037 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1038 break; 1039 } 1040 if (urb->length != cnt) 1041 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 1042 } 1043 1044 /*-------------------------------------------------------------------------* 1045 * Done List handling functions 1046 *-------------------------------------------------------------------------*/ 1047 1048 /* calculate the transfer length and update the urb */ 1049 1050 static void dl_transfer_length(td_t *td) 1051 { 1052 __u32 tdBE, tdCBP; 1053 urb_priv_t *lurb_priv = td->ed->purb; 1054 1055 tdBE = m32_swap(td->hwBE); 1056 tdCBP = m32_swap(td->hwCBP); 1057 1058 if (!(usb_pipecontrol(lurb_priv->pipe) && 1059 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 1060 if (tdBE != 0) { 1061 if (td->hwCBP == 0) 1062 lurb_priv->actual_length += tdBE - td->data + 1; 1063 else 1064 lurb_priv->actual_length += tdCBP - td->data; 1065 } 1066 } 1067 } 1068 1069 /*-------------------------------------------------------------------------*/ 1070 static void check_status(td_t *td_list) 1071 { 1072 urb_priv_t *lurb_priv = td_list->ed->purb; 1073 int urb_len = lurb_priv->length; 1074 __u32 *phwHeadP = &td_list->ed->hwHeadP; 1075 int cc; 1076 1077 cc = TD_CC_GET(m32_swap(td_list->hwINFO)); 1078 if (cc) { 1079 err(" USB-error: %s (%x)", cc_to_string[cc], cc); 1080 1081 invalidate_dcache_ed(td_list->ed); 1082 if (*phwHeadP & m32_swap(0x1)) { 1083 if (lurb_priv && 1084 ((td_list->index + 1) < urb_len)) { 1085 *phwHeadP = 1086 (lurb_priv->td[urb_len - 1]->hwNextTD &\ 1087 m32_swap(0xfffffff0)) | 1088 (*phwHeadP & m32_swap(0x2)); 1089 1090 lurb_priv->td_cnt += urb_len - 1091 td_list->index - 1; 1092 } else 1093 *phwHeadP &= m32_swap(0xfffffff2); 1094 flush_dcache_ed(td_list->ed); 1095 } 1096 #ifdef CONFIG_MPC5200 1097 td_list->hwNextTD = 0; 1098 flush_dcache_td(td_list); 1099 #endif 1100 } 1101 } 1102 1103 /* replies to the request have to be on a FIFO basis so 1104 * we reverse the reversed done-list */ 1105 static td_t *dl_reverse_done_list(ohci_t *ohci) 1106 { 1107 __u32 td_list_hc; 1108 td_t *td_rev = NULL; 1109 td_t *td_list = NULL; 1110 1111 invalidate_dcache_hcca(ohci->hcca); 1112 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; 1113 ohci->hcca->done_head = 0; 1114 flush_dcache_hcca(ohci->hcca); 1115 1116 while (td_list_hc) { 1117 td_list = (td_t *)td_list_hc; 1118 invalidate_dcache_td(td_list); 1119 check_status(td_list); 1120 td_list->next_dl_td = td_rev; 1121 td_rev = td_list; 1122 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; 1123 } 1124 return td_list; 1125 } 1126 1127 /*-------------------------------------------------------------------------*/ 1128 /*-------------------------------------------------------------------------*/ 1129 1130 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) 1131 { 1132 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) 1133 urb->finished = 1; 1134 else 1135 dbg("finish_urb: strange.., ED state %x, \n", status); 1136 } 1137 1138 /* 1139 * Used to take back a TD from the host controller. This would normally be 1140 * called from within dl_done_list, however it may be called directly if the 1141 * HC no longer sees the TD and it has not appeared on the donelist (after 1142 * two frames). This bug has been observed on ZF Micro systems. 1143 */ 1144 static int takeback_td(ohci_t *ohci, td_t *td_list) 1145 { 1146 ed_t *ed; 1147 int cc; 1148 int stat = 0; 1149 /* urb_t *urb; */ 1150 urb_priv_t *lurb_priv; 1151 __u32 tdINFO, edHeadP, edTailP; 1152 1153 invalidate_dcache_td(td_list); 1154 tdINFO = m32_swap(td_list->hwINFO); 1155 1156 ed = td_list->ed; 1157 lurb_priv = ed->purb; 1158 1159 dl_transfer_length(td_list); 1160 1161 lurb_priv->td_cnt++; 1162 1163 /* error code of transfer */ 1164 cc = TD_CC_GET(tdINFO); 1165 if (cc) { 1166 err("USB-error: %s (%x)", cc_to_string[cc], cc); 1167 stat = cc_to_error[cc]; 1168 } 1169 1170 /* see if this done list makes for all TD's of current URB, 1171 * and mark the URB finished if so */ 1172 if (lurb_priv->td_cnt == lurb_priv->length) 1173 finish_urb(ohci, lurb_priv, ed->state); 1174 1175 dbg("dl_done_list: processing TD %x, len %x\n", 1176 lurb_priv->td_cnt, lurb_priv->length); 1177 1178 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { 1179 invalidate_dcache_ed(ed); 1180 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; 1181 edTailP = m32_swap(ed->hwTailP); 1182 1183 /* unlink eds if they are not busy */ 1184 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 1185 ep_unlink(ohci, ed); 1186 } 1187 return stat; 1188 } 1189 1190 static int dl_done_list(ohci_t *ohci) 1191 { 1192 int stat = 0; 1193 td_t *td_list = dl_reverse_done_list(ohci); 1194 1195 while (td_list) { 1196 td_t *td_next = td_list->next_dl_td; 1197 stat = takeback_td(ohci, td_list); 1198 td_list = td_next; 1199 } 1200 return stat; 1201 } 1202 1203 /*-------------------------------------------------------------------------* 1204 * Virtual Root Hub 1205 *-------------------------------------------------------------------------*/ 1206 1207 #include <usbroothubdes.h> 1208 1209 /* Hub class-specific descriptor is constructed dynamically */ 1210 1211 /*-------------------------------------------------------------------------*/ 1212 1213 #define OK(x) len = (x); break 1214 #ifdef DEBUG 1215 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ 1216 &ohci->regs->roothub.status); } 1217 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ 1218 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } 1219 #else 1220 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) 1221 #define WR_RH_PORTSTAT(x) ohci_writel((x), \ 1222 &ohci->regs->roothub.portstatus[wIndex-1]) 1223 #endif 1224 #define RD_RH_STAT roothub_status(ohci) 1225 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) 1226 1227 /* request to virtual root hub */ 1228 1229 int rh_check_port_status(ohci_t *controller) 1230 { 1231 __u32 temp, ndp, i; 1232 int res; 1233 1234 res = -1; 1235 temp = roothub_a(controller); 1236 ndp = (temp & RH_A_NDP); 1237 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1238 ndp = (ndp == 2) ? 1:0; 1239 #endif 1240 for (i = 0; i < ndp; i++) { 1241 temp = roothub_portstatus(controller, i); 1242 /* check for a device disconnect */ 1243 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 1244 (RH_PS_PESC | RH_PS_CSC)) && 1245 ((temp & RH_PS_CCS) == 0)) { 1246 res = i; 1247 break; 1248 } 1249 } 1250 return res; 1251 } 1252 1253 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, 1254 unsigned long pipe, void *buffer, int transfer_len, 1255 struct devrequest *cmd) 1256 { 1257 void *data = buffer; 1258 int leni = transfer_len; 1259 int len = 0; 1260 int stat = 0; 1261 __u16 bmRType_bReq; 1262 __u16 wValue; 1263 __u16 wIndex; 1264 __u16 wLength; 1265 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); 1266 1267 #ifdef DEBUG 1268 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1269 cmd, "SUB(rh)", usb_pipein(pipe)); 1270 #else 1271 ohci_mdelay(1); 1272 #endif 1273 if (usb_pipeint(pipe)) { 1274 info("Root-Hub submit IRQ: NOT implemented"); 1275 return 0; 1276 } 1277 1278 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 1279 wValue = le16_to_cpu(cmd->value); 1280 wIndex = le16_to_cpu(cmd->index); 1281 wLength = le16_to_cpu(cmd->length); 1282 1283 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 1284 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 1285 1286 switch (bmRType_bReq) { 1287 /* Request Destination: 1288 without flags: Device, 1289 RH_INTERFACE: interface, 1290 RH_ENDPOINT: endpoint, 1291 RH_CLASS means HUB here, 1292 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 1293 */ 1294 1295 case RH_GET_STATUS: 1296 *(u16 *)databuf = cpu_to_le16(1); 1297 OK(2); 1298 case RH_GET_STATUS | RH_INTERFACE: 1299 *(u16 *)databuf = cpu_to_le16(0); 1300 OK(2); 1301 case RH_GET_STATUS | RH_ENDPOINT: 1302 *(u16 *)databuf = cpu_to_le16(0); 1303 OK(2); 1304 case RH_GET_STATUS | RH_CLASS: 1305 *(u32 *)databuf = cpu_to_le32( 1306 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 1307 OK(4); 1308 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 1309 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); 1310 OK(4); 1311 1312 case RH_CLEAR_FEATURE | RH_ENDPOINT: 1313 switch (wValue) { 1314 case (RH_ENDPOINT_STALL): 1315 OK(0); 1316 } 1317 break; 1318 1319 case RH_CLEAR_FEATURE | RH_CLASS: 1320 switch (wValue) { 1321 case RH_C_HUB_LOCAL_POWER: 1322 OK(0); 1323 case (RH_C_HUB_OVER_CURRENT): 1324 WR_RH_STAT(RH_HS_OCIC); 1325 OK(0); 1326 } 1327 break; 1328 1329 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 1330 switch (wValue) { 1331 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); 1332 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); 1333 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); 1334 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); 1335 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); 1336 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); 1337 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); 1338 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); 1339 } 1340 break; 1341 1342 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 1343 switch (wValue) { 1344 case (RH_PORT_SUSPEND): 1345 WR_RH_PORTSTAT(RH_PS_PSS); OK(0); 1346 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 1347 if (RD_RH_PORTSTAT & RH_PS_CCS) 1348 WR_RH_PORTSTAT(RH_PS_PRS); 1349 OK(0); 1350 case (RH_PORT_POWER): 1351 WR_RH_PORTSTAT(RH_PS_PPS); 1352 OK(0); 1353 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 1354 if (RD_RH_PORTSTAT & RH_PS_CCS) 1355 WR_RH_PORTSTAT(RH_PS_PES); 1356 OK(0); 1357 } 1358 break; 1359 1360 case RH_SET_ADDRESS: 1361 ohci->rh.devnum = wValue; 1362 OK(0); 1363 1364 case RH_GET_DESCRIPTOR: 1365 switch ((wValue & 0xff00) >> 8) { 1366 case (0x01): /* device descriptor */ 1367 len = min_t(unsigned int, 1368 leni, 1369 min_t(unsigned int, 1370 sizeof(root_hub_dev_des), 1371 wLength)); 1372 databuf = root_hub_dev_des; OK(len); 1373 case (0x02): /* configuration descriptor */ 1374 len = min_t(unsigned int, 1375 leni, 1376 min_t(unsigned int, 1377 sizeof(root_hub_config_des), 1378 wLength)); 1379 databuf = root_hub_config_des; OK(len); 1380 case (0x03): /* string descriptors */ 1381 if (wValue == 0x0300) { 1382 len = min_t(unsigned int, 1383 leni, 1384 min_t(unsigned int, 1385 sizeof(root_hub_str_index0), 1386 wLength)); 1387 databuf = root_hub_str_index0; 1388 OK(len); 1389 } 1390 if (wValue == 0x0301) { 1391 len = min_t(unsigned int, 1392 leni, 1393 min_t(unsigned int, 1394 sizeof(root_hub_str_index1), 1395 wLength)); 1396 databuf = root_hub_str_index1; 1397 OK(len); 1398 } 1399 default: 1400 stat = USB_ST_STALLED; 1401 } 1402 break; 1403 1404 case RH_GET_DESCRIPTOR | RH_CLASS: 1405 { 1406 __u32 temp = roothub_a(ohci); 1407 1408 databuf[0] = 9; /* min length; */ 1409 databuf[1] = 0x29; 1410 databuf[2] = temp & RH_A_NDP; 1411 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1412 databuf[2] = (databuf[2] == 2) ? 1 : 0; 1413 #endif 1414 databuf[3] = 0; 1415 if (temp & RH_A_PSM) /* per-port power switching? */ 1416 databuf[3] |= 0x1; 1417 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1418 databuf[3] |= 0x10; 1419 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ 1420 databuf[3] |= 0x8; 1421 1422 databuf[4] = 0; 1423 databuf[5] = (temp & RH_A_POTPGT) >> 24; 1424 databuf[6] = 0; 1425 temp = roothub_b(ohci); 1426 databuf[7] = temp & RH_B_DR; 1427 if (databuf[2] < 7) { 1428 databuf[8] = 0xff; 1429 } else { 1430 databuf[0] += 2; 1431 databuf[8] = (temp & RH_B_DR) >> 8; 1432 databuf[10] = databuf[9] = 0xff; 1433 } 1434 1435 len = min_t(unsigned int, leni, 1436 min_t(unsigned int, databuf[0], wLength)); 1437 OK(len); 1438 } 1439 1440 case RH_GET_CONFIGURATION: 1441 databuf[0] = 0x01; 1442 OK(1); 1443 1444 case RH_SET_CONFIGURATION: 1445 WR_RH_STAT(0x10000); 1446 OK(0); 1447 1448 default: 1449 dbg("unsupported root hub command"); 1450 stat = USB_ST_STALLED; 1451 } 1452 1453 #ifdef DEBUG 1454 ohci_dump_roothub(ohci, 1); 1455 #else 1456 ohci_mdelay(1); 1457 #endif 1458 1459 len = min_t(int, len, leni); 1460 if (data != databuf) 1461 memcpy(data, databuf, len); 1462 dev->act_len = len; 1463 dev->status = stat; 1464 1465 #ifdef DEBUG 1466 pkt_print(ohci, NULL, dev, pipe, buffer, 1467 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1468 #else 1469 ohci_mdelay(1); 1470 #endif 1471 1472 return stat; 1473 } 1474 1475 /*-------------------------------------------------------------------------*/ 1476 1477 /* common code for handling submit messages - used for all but root hub */ 1478 /* accesses. */ 1479 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, 1480 unsigned long pipe, void *buffer, int transfer_len, 1481 struct devrequest *setup, int interval) 1482 { 1483 int stat = 0; 1484 int maxsize = usb_maxpacket(dev, pipe); 1485 int timeout; 1486 urb_priv_t *urb; 1487 1488 urb = malloc(sizeof(urb_priv_t)); 1489 memset(urb, 0, sizeof(urb_priv_t)); 1490 1491 urb->dev = dev; 1492 urb->pipe = pipe; 1493 urb->transfer_buffer = buffer; 1494 urb->transfer_buffer_length = transfer_len; 1495 urb->interval = interval; 1496 1497 #ifdef DEBUG 1498 urb->actual_length = 0; 1499 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1500 setup, "SUB", usb_pipein(pipe)); 1501 #else 1502 ohci_mdelay(1); 1503 #endif 1504 if (!maxsize) { 1505 err("submit_common_message: pipesize for pipe %lx is zero", 1506 pipe); 1507 return -1; 1508 } 1509 1510 if (sohci_submit_job(ohci, &ohci->ohci_dev, urb, setup) < 0) { 1511 err("sohci_submit_job failed"); 1512 return -1; 1513 } 1514 1515 #if 0 1516 mdelay(10); 1517 /* ohci_dump_status(ohci); */ 1518 #endif 1519 1520 timeout = USB_TIMEOUT_MS(pipe); 1521 1522 /* wait for it to complete */ 1523 for (;;) { 1524 /* check whether the controller is done */ 1525 stat = hc_interrupt(ohci); 1526 if (stat < 0) { 1527 stat = USB_ST_CRC_ERR; 1528 break; 1529 } 1530 1531 /* NOTE: since we are not interrupt driven in U-Boot and always 1532 * handle only one URB at a time, we cannot assume the 1533 * transaction finished on the first successful return from 1534 * hc_interrupt().. unless the flag for current URB is set, 1535 * meaning that all TD's to/from device got actually 1536 * transferred and processed. If the current URB is not 1537 * finished we need to re-iterate this loop so as 1538 * hc_interrupt() gets called again as there needs to be some 1539 * more TD's to process still */ 1540 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { 1541 /* 0xff is returned for an SF-interrupt */ 1542 break; 1543 } 1544 1545 if (--timeout) { 1546 mdelay(1); 1547 if (!urb->finished) 1548 dbg("*"); 1549 1550 } else { 1551 if (!usb_pipeint(pipe)) 1552 err("CTL:TIMEOUT "); 1553 dbg("submit_common_msg: TO status %x\n", stat); 1554 urb->finished = 1; 1555 stat = USB_ST_CRC_ERR; 1556 break; 1557 } 1558 } 1559 1560 dev->status = stat; 1561 dev->act_len = urb->actual_length; 1562 1563 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) 1564 invalidate_dcache_buffer(buffer, dev->act_len); 1565 1566 #ifdef DEBUG 1567 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1568 setup, "RET(ctlr)", usb_pipein(pipe)); 1569 #else 1570 ohci_mdelay(1); 1571 #endif 1572 urb_free_priv(urb); 1573 return 0; 1574 } 1575 1576 /* submit routines called from usb.c */ 1577 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1578 int transfer_len) 1579 { 1580 info("submit_bulk_msg"); 1581 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, 1582 NULL, 0); 1583 } 1584 1585 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1586 int transfer_len, int interval) 1587 { 1588 info("submit_int_msg"); 1589 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, 1590 interval); 1591 } 1592 1593 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, 1594 unsigned long pipe, void *buffer, int transfer_len, 1595 struct devrequest *setup) 1596 { 1597 int maxsize = usb_maxpacket(dev, pipe); 1598 1599 info("submit_control_msg"); 1600 #ifdef DEBUG 1601 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1602 setup, "SUB", usb_pipein(pipe)); 1603 #else 1604 ohci_mdelay(1); 1605 #endif 1606 if (!maxsize) { 1607 err("submit_control_message: pipesize for pipe %lx is zero", 1608 pipe); 1609 return -1; 1610 } 1611 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { 1612 ohci->rh.dev = dev; 1613 /* root hub - redirect */ 1614 return ohci_submit_rh_msg(ohci, dev, pipe, buffer, 1615 transfer_len, setup); 1616 } 1617 1618 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, 1619 setup, 0); 1620 } 1621 1622 /*-------------------------------------------------------------------------* 1623 * HC functions 1624 *-------------------------------------------------------------------------*/ 1625 1626 /* reset the HC and BUS */ 1627 1628 static int hc_reset(ohci_t *ohci) 1629 { 1630 #ifdef CONFIG_PCI_EHCI_DEVNO 1631 pci_dev_t pdev; 1632 #endif 1633 int timeout = 30; 1634 int smm_timeout = 50; /* 0,5 sec */ 1635 1636 dbg("%s\n", __FUNCTION__); 1637 1638 #ifdef CONFIG_PCI_EHCI_DEVNO 1639 /* 1640 * Some multi-function controllers (e.g. ISP1562) allow root hub 1641 * resetting via EHCI registers only. 1642 */ 1643 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); 1644 if (pdev != -1) { 1645 u32 base; 1646 int timeout = 1000; 1647 1648 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1649 base += EHCI_USBCMD_OFF; 1650 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); 1651 1652 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { 1653 if (timeout-- <= 0) { 1654 printf("USB RootHub reset timed out!"); 1655 break; 1656 } 1657 udelay(1); 1658 } 1659 } else 1660 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); 1661 #endif 1662 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1663 /* SMM owns the HC, request ownership */ 1664 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); 1665 info("USB HC TakeOver from SMM"); 1666 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1667 mdelay(10); 1668 if (--smm_timeout == 0) { 1669 err("USB HC TakeOver failed!"); 1670 return -1; 1671 } 1672 } 1673 } 1674 1675 /* Disable HC interrupts */ 1676 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); 1677 1678 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", 1679 ohci->slot_name, 1680 ohci_readl(&ohci->regs->control)); 1681 1682 /* Reset USB (needed by some controllers) */ 1683 ohci->hc_control = 0; 1684 ohci_writel(ohci->hc_control, &ohci->regs->control); 1685 1686 /* HC Reset requires max 10 us delay */ 1687 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); 1688 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1689 if (--timeout == 0) { 1690 err("USB HC reset timed out!"); 1691 return -1; 1692 } 1693 udelay(1); 1694 } 1695 return 0; 1696 } 1697 1698 /*-------------------------------------------------------------------------*/ 1699 1700 /* Start an OHCI controller, set the BUS operational 1701 * enable interrupts 1702 * connect the virtual root hub */ 1703 1704 static int hc_start(ohci_t *ohci) 1705 { 1706 __u32 mask; 1707 unsigned int fminterval; 1708 1709 ohci->disabled = 1; 1710 1711 /* Tell the controller where the control and bulk lists are 1712 * The lists are empty now. */ 1713 1714 ohci_writel(0, &ohci->regs->ed_controlhead); 1715 ohci_writel(0, &ohci->regs->ed_bulkhead); 1716 1717 ohci_writel((__u32)ohci->hcca, 1718 &ohci->regs->hcca); /* reset clears this */ 1719 1720 fminterval = 0x2edf; 1721 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); 1722 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1723 ohci_writel(fminterval, &ohci->regs->fminterval); 1724 ohci_writel(0x628, &ohci->regs->lsthresh); 1725 1726 /* start controller operations */ 1727 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1728 ohci->disabled = 0; 1729 ohci_writel(ohci->hc_control, &ohci->regs->control); 1730 1731 /* disable all interrupts */ 1732 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1733 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1734 OHCI_INTR_OC | OHCI_INTR_MIE); 1735 ohci_writel(mask, &ohci->regs->intrdisable); 1736 /* clear all interrupts */ 1737 mask &= ~OHCI_INTR_MIE; 1738 ohci_writel(mask, &ohci->regs->intrstatus); 1739 /* Choose the interrupts we care about now - but w/o MIE */ 1740 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1741 ohci_writel(mask, &ohci->regs->intrenable); 1742 1743 #ifdef OHCI_USE_NPS 1744 /* required for AMD-756 and some Mac platforms */ 1745 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, 1746 &ohci->regs->roothub.a); 1747 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); 1748 #endif /* OHCI_USE_NPS */ 1749 1750 /* connect the virtual root hub */ 1751 ohci->rh.devnum = 0; 1752 1753 return 0; 1754 } 1755 1756 /*-------------------------------------------------------------------------*/ 1757 1758 /* an interrupt happens */ 1759 1760 static int hc_interrupt(ohci_t *ohci) 1761 { 1762 struct ohci_regs *regs = ohci->regs; 1763 int ints; 1764 int stat = -1; 1765 1766 invalidate_dcache_hcca(ohci->hcca); 1767 1768 if ((ohci->hcca->done_head != 0) && 1769 !(m32_swap(ohci->hcca->done_head) & 0x01)) { 1770 ints = OHCI_INTR_WDH; 1771 } else { 1772 ints = ohci_readl(®s->intrstatus); 1773 if (ints == ~(u32)0) { 1774 ohci->disabled++; 1775 err("%s device removed!", ohci->slot_name); 1776 return -1; 1777 } else { 1778 ints &= ohci_readl(®s->intrenable); 1779 if (ints == 0) { 1780 dbg("hc_interrupt: returning..\n"); 1781 return 0xff; 1782 } 1783 } 1784 } 1785 1786 /* dbg("Interrupt: %x frame: %x", ints, 1787 le16_to_cpu(ohci->hcca->frame_no)); */ 1788 1789 if (ints & OHCI_INTR_RHSC) 1790 stat = 0xff; 1791 1792 if (ints & OHCI_INTR_UE) { 1793 ohci->disabled++; 1794 err("OHCI Unrecoverable Error, controller usb-%s disabled", 1795 ohci->slot_name); 1796 /* e.g. due to PCI Master/Target Abort */ 1797 1798 #ifdef DEBUG 1799 ohci_dump(ohci, 1); 1800 #else 1801 ohci_mdelay(1); 1802 #endif 1803 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1804 /* Make some non-interrupt context restart the controller. */ 1805 /* Count and limit the retries though; either hardware or */ 1806 /* software errors can go forever... */ 1807 hc_reset(ohci); 1808 return -1; 1809 } 1810 1811 if (ints & OHCI_INTR_WDH) { 1812 ohci_mdelay(1); 1813 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 1814 (void)ohci_readl(®s->intrdisable); /* flush */ 1815 stat = dl_done_list(ohci); 1816 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 1817 (void)ohci_readl(®s->intrdisable); /* flush */ 1818 } 1819 1820 if (ints & OHCI_INTR_SO) { 1821 dbg("USB Schedule overrun\n"); 1822 ohci_writel(OHCI_INTR_SO, ®s->intrenable); 1823 stat = -1; 1824 } 1825 1826 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1827 if (ints & OHCI_INTR_SF) { 1828 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; 1829 mdelay(1); 1830 ohci_writel(OHCI_INTR_SF, ®s->intrdisable); 1831 if (ohci->ed_rm_list[frame] != NULL) 1832 ohci_writel(OHCI_INTR_SF, ®s->intrenable); 1833 stat = 0xff; 1834 } 1835 1836 ohci_writel(ints, ®s->intrstatus); 1837 return stat; 1838 } 1839 1840 /*-------------------------------------------------------------------------*/ 1841 1842 /*-------------------------------------------------------------------------*/ 1843 1844 /* De-allocate all resources.. */ 1845 1846 static void hc_release_ohci(ohci_t *ohci) 1847 { 1848 dbg("USB HC release ohci usb-%s", ohci->slot_name); 1849 1850 if (!ohci->disabled) 1851 hc_reset(ohci); 1852 } 1853 1854 /*-------------------------------------------------------------------------*/ 1855 1856 /* 1857 * low level initalisation routine, called from usb.c 1858 */ 1859 static char ohci_inited = 0; 1860 1861 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1862 { 1863 #ifdef CONFIG_PCI_OHCI 1864 pci_dev_t pdev; 1865 #endif 1866 1867 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1868 /* cpu dependant init */ 1869 if (usb_cpu_init()) 1870 return -1; 1871 #endif 1872 1873 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1874 /* board dependant init */ 1875 if (board_usb_init(index, USB_INIT_HOST)) 1876 return -1; 1877 #endif 1878 memset(&gohci, 0, sizeof(ohci_t)); 1879 1880 /* align the storage */ 1881 if ((__u32)&ghcca[0] & 0xff) { 1882 err("HCCA not aligned!!"); 1883 return -1; 1884 } 1885 gohci.hcca = &ghcca[0]; 1886 info("aligned ghcca %p", gohci.hcca); 1887 memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); 1888 1889 gohci.disabled = 1; 1890 gohci.sleeping = 0; 1891 gohci.irq = -1; 1892 #ifdef CONFIG_PCI_OHCI 1893 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); 1894 1895 if (pdev != -1) { 1896 u16 vid, did; 1897 u32 base; 1898 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); 1899 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 1900 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", 1901 vid, did, (pdev >> 16) & 0xff, 1902 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 1903 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1904 printf("OHCI regs address 0x%08x\n", base); 1905 gohci.regs = (struct ohci_regs *)base; 1906 } else 1907 return -1; 1908 #else 1909 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; 1910 #endif 1911 1912 gohci.flags = 0; 1913 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; 1914 1915 if (hc_reset (&gohci) < 0) { 1916 hc_release_ohci (&gohci); 1917 err ("can't reset usb-%s", gohci.slot_name); 1918 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1919 /* board dependant cleanup */ 1920 board_usb_cleanup(index, USB_INIT_HOST); 1921 #endif 1922 1923 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1924 /* cpu dependant cleanup */ 1925 usb_cpu_init_fail(); 1926 #endif 1927 return -1; 1928 } 1929 1930 if (hc_start(&gohci) < 0) { 1931 err("can't start usb-%s", gohci.slot_name); 1932 hc_release_ohci(&gohci); 1933 /* Initialization failed */ 1934 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1935 /* board dependant cleanup */ 1936 usb_board_stop(); 1937 #endif 1938 1939 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1940 /* cpu dependant cleanup */ 1941 usb_cpu_stop(); 1942 #endif 1943 return -1; 1944 } 1945 1946 #ifdef DEBUG 1947 ohci_dump(&gohci, 1); 1948 #else 1949 ohci_mdelay(1); 1950 #endif 1951 ohci_inited = 1; 1952 return 0; 1953 } 1954 1955 int usb_lowlevel_stop(int index) 1956 { 1957 /* this gets called really early - before the controller has */ 1958 /* even been initialized! */ 1959 if (!ohci_inited) 1960 return 0; 1961 /* TODO release any interrupts, etc. */ 1962 /* call hc_release_ohci() here ? */ 1963 hc_reset(&gohci); 1964 1965 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1966 /* board dependant cleanup */ 1967 if (usb_board_stop()) 1968 return -1; 1969 #endif 1970 1971 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1972 /* cpu dependant cleanup */ 1973 if (usb_cpu_stop()) 1974 return -1; 1975 #endif 1976 /* This driver is no longer initialised. It needs a new low-level 1977 * init (board/cpu) before it can be used again. */ 1978 ohci_inited = 0; 1979 return 0; 1980 } 1981 1982 int submit_control_msg(struct usb_device *dev, unsigned long pipe, 1983 void *buffer, int transfer_len, struct devrequest *setup) 1984 { 1985 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, 1986 transfer_len, setup); 1987 } 1988