1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <wait_bit.h> 12 #include <linux/compiler.h> 13 #include <usb/ehci-ci.h> 14 #include <asm/io.h> 15 #include <asm/arch/imx-regs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/imx-common/iomux-v3.h> 18 19 #include "ehci.h" 20 21 #define USB_OTGREGS_OFFSET 0x000 22 #define USB_H1REGS_OFFSET 0x200 23 #define USB_H2REGS_OFFSET 0x400 24 #define USB_H3REGS_OFFSET 0x600 25 #define USB_OTHERREGS_OFFSET 0x800 26 27 #define USB_H1_CTRL_OFFSET 0x04 28 29 #define USBPHY_CTRL 0x00000030 30 #define USBPHY_CTRL_SET 0x00000034 31 #define USBPHY_CTRL_CLR 0x00000038 32 #define USBPHY_CTRL_TOG 0x0000003c 33 34 #define USBPHY_PWD 0x00000000 35 #define USBPHY_CTRL_SFTRST 0x80000000 36 #define USBPHY_CTRL_CLKGATE 0x40000000 37 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 38 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 39 #define USBPHY_CTRL_OTG_ID 0x08000000 40 41 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 42 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 43 44 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 45 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 46 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 47 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 48 49 #define USBNC_OFFSET 0x200 50 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ 51 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ 52 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ 53 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 54 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 55 56 /* USBCMD */ 57 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 58 #define UCMD_RESET (1 << 1) /* controller reset */ 59 60 #if defined(CONFIG_MX6) 61 static const unsigned phy_bases[] = { 62 USB_PHY0_BASE_ADDR, 63 USB_PHY1_BASE_ADDR, 64 }; 65 66 static void usb_internal_phy_clock_gate(int index, int on) 67 { 68 void __iomem *phy_reg; 69 70 if (index >= ARRAY_SIZE(phy_bases)) 71 return; 72 73 phy_reg = (void __iomem *)phy_bases[index]; 74 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; 75 writel(USBPHY_CTRL_CLKGATE, phy_reg); 76 } 77 78 static void usb_power_config(int index) 79 { 80 struct anatop_regs __iomem *anatop = 81 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 82 void __iomem *chrg_detect; 83 void __iomem *pll_480_ctrl_clr; 84 void __iomem *pll_480_ctrl_set; 85 86 switch (index) { 87 case 0: 88 chrg_detect = &anatop->usb1_chrg_detect; 89 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; 90 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; 91 break; 92 case 1: 93 chrg_detect = &anatop->usb2_chrg_detect; 94 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; 95 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; 96 break; 97 default: 98 return; 99 } 100 /* 101 * Some phy and power's special controls 102 * 1. The external charger detector needs to be disabled 103 * or the signal at DP will be poor 104 * 2. The PLL's power and output to usb 105 * is totally controlled by IC, so the Software only needs 106 * to enable them at initializtion. 107 */ 108 writel(ANADIG_USB2_CHRG_DETECT_EN_B | 109 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, 110 chrg_detect); 111 112 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, 113 pll_480_ctrl_clr); 114 115 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | 116 ANADIG_USB2_PLL_480_CTRL_POWER | 117 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, 118 pll_480_ctrl_set); 119 } 120 121 /* Return 0 : host node, <>0 : device mode */ 122 static int usb_phy_enable(int index, struct usb_ehci *ehci) 123 { 124 void __iomem *phy_reg; 125 void __iomem *phy_ctrl; 126 void __iomem *usb_cmd; 127 int ret; 128 129 if (index >= ARRAY_SIZE(phy_bases)) 130 return 0; 131 132 phy_reg = (void __iomem *)phy_bases[index]; 133 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 134 usb_cmd = (void __iomem *)&ehci->usbcmd; 135 136 /* Stop then Reset */ 137 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 138 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000, 139 false); 140 if (ret) 141 return ret; 142 143 setbits_le32(usb_cmd, UCMD_RESET); 144 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false); 145 if (ret) 146 return ret; 147 148 /* Reset USBPHY module */ 149 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 150 udelay(10); 151 152 /* Remove CLKGATE and SFTRST */ 153 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 154 udelay(10); 155 156 /* Power up the PHY */ 157 writel(0, phy_reg + USBPHY_PWD); 158 /* enable FS/LS device */ 159 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 160 USBPHY_CTRL_ENUTMILEVEL3); 161 162 return 0; 163 } 164 165 int usb_phy_mode(int port) 166 { 167 void __iomem *phy_reg; 168 void __iomem *phy_ctrl; 169 u32 val; 170 171 phy_reg = (void __iomem *)phy_bases[port]; 172 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 173 174 val = readl(phy_ctrl); 175 176 if (val & USBPHY_CTRL_OTG_ID) 177 return USB_INIT_DEVICE; 178 else 179 return USB_INIT_HOST; 180 } 181 182 /* Base address for this IP block is 0x02184800 */ 183 struct usbnc_regs { 184 u32 ctrl[4]; /* otg/host1-3 */ 185 u32 uh2_hsic_ctrl; 186 u32 uh3_hsic_ctrl; 187 u32 otg_phy_ctrl_0; 188 u32 uh1_phy_ctrl_0; 189 }; 190 #elif defined(CONFIG_MX7) 191 struct usbnc_regs { 192 u32 ctrl1; 193 u32 ctrl2; 194 u32 reserve1[10]; 195 u32 phy_cfg1; 196 u32 phy_cfg2; 197 u32 reserve2; 198 u32 phy_status; 199 u32 reserve3[4]; 200 u32 adp_cfg1; 201 u32 adp_cfg2; 202 u32 adp_status; 203 }; 204 205 static void usb_power_config(int index) 206 { 207 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 208 (0x10000 * index) + USBNC_OFFSET); 209 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); 210 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 211 212 /* 213 * Clear the ACAENB to enable usb_otg_id detection, 214 * otherwise it is the ACA detection enabled. 215 */ 216 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); 217 218 /* Set power polarity to high active */ 219 #ifdef CONFIG_MXC_USB_OTG_HACTIVE 220 setbits_le32(ctrl, UCTRL_PWR_POL); 221 #else 222 clrbits_le32(ctrl, UCTRL_PWR_POL); 223 #endif 224 } 225 226 int usb_phy_mode(int port) 227 { 228 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 229 (0x10000 * port) + USBNC_OFFSET); 230 void __iomem *status = (void __iomem *)(&usbnc->phy_status); 231 u32 val; 232 233 val = readl(status); 234 235 if (val & USBNC_PHYSTATUS_ID_DIG) 236 return USB_INIT_DEVICE; 237 else 238 return USB_INIT_HOST; 239 } 240 #endif 241 242 static void usb_oc_config(int index) 243 { 244 #if defined(CONFIG_MX6) 245 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 246 USB_OTHERREGS_OFFSET); 247 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); 248 #elif defined(CONFIG_MX7) 249 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 250 (0x10000 * index) + USBNC_OFFSET); 251 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 252 #endif 253 254 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 255 /* mx6qarm2 seems to required a different setting*/ 256 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); 257 #else 258 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 259 #endif 260 261 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 262 } 263 264 /** 265 * board_usb_phy_mode - override usb phy mode 266 * @port: usb host/otg port 267 * 268 * Target board specific, override usb_phy_mode. 269 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be 270 * left disconnected in this case usb_phy_mode will not be able to identify 271 * the phy mode that usb port is used. 272 * Machine file overrides board_usb_phy_mode. 273 * 274 * Return: USB_INIT_DEVICE or USB_INIT_HOST 275 */ 276 int __weak board_usb_phy_mode(int port) 277 { 278 return usb_phy_mode(port); 279 } 280 281 /** 282 * board_ehci_hcd_init - set usb vbus voltage 283 * @port: usb otg port 284 * 285 * Target board specific, setup iomux pad to setup supply vbus voltage 286 * for usb otg port. Machine board file overrides board_ehci_hcd_init 287 * 288 * Return: 0 Success 289 */ 290 int __weak board_ehci_hcd_init(int port) 291 { 292 return 0; 293 } 294 295 /** 296 * board_ehci_power - enables/disables usb vbus voltage 297 * @port: usb otg port 298 * @on: on/off vbus voltage 299 * 300 * Enables/disables supply vbus voltage for usb otg port. 301 * Machine board file overrides board_ehci_power 302 * 303 * Return: 0 Success 304 */ 305 int __weak board_ehci_power(int port, int on) 306 { 307 return 0; 308 } 309 310 int ehci_hcd_init(int index, enum usb_init_type init, 311 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 312 { 313 enum usb_init_type type; 314 #if defined(CONFIG_MX6) 315 u32 controller_spacing = 0x200; 316 #elif defined(CONFIG_MX7) 317 u32 controller_spacing = 0x10000; 318 #endif 319 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + 320 (controller_spacing * index)); 321 int ret; 322 323 if (index > 3) 324 return -EINVAL; 325 enable_usboh3_clk(1); 326 mdelay(1); 327 328 /* Do board specific initialization */ 329 ret = board_ehci_hcd_init(index); 330 if (ret) 331 return ret; 332 333 usb_power_config(index); 334 usb_oc_config(index); 335 336 #if defined(CONFIG_MX6) 337 usb_internal_phy_clock_gate(index, 1); 338 usb_phy_enable(index, ehci); 339 #endif 340 type = board_usb_phy_mode(index); 341 342 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 343 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 344 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 345 346 if ((type == init) || (type == USB_INIT_DEVICE)) 347 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); 348 if (type != init) 349 return -ENODEV; 350 if (type == USB_INIT_DEVICE) 351 return 0; 352 353 setbits_le32(&ehci->usbmode, CM_HOST); 354 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 355 setbits_le32(&ehci->portsc, USB_EN); 356 357 mdelay(10); 358 359 return 0; 360 } 361 362 int ehci_hcd_stop(int index) 363 { 364 return 0; 365 } 366