1 /* 2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB 5 * 6 * Author: Tor Krill tor@excito.com 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <pci.h> 13 #include <usb.h> 14 #include <asm/io.h> 15 #include <usb/ehci-ci.h> 16 #include <hwconfig.h> 17 #include <fsl_usb.h> 18 #include <fdt_support.h> 19 20 #include "ehci.h" 21 22 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 23 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 24 #endif 25 26 static void set_txfifothresh(struct usb_ehci *, u32); 27 28 /* Check USB PHY clock valid */ 29 static int usb_phy_clk_valid(struct usb_ehci *ehci) 30 { 31 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || 32 in_be32(&ehci->prictrl))) { 33 printf("USB PHY clock invalid!\n"); 34 return 0; 35 } else { 36 return 1; 37 } 38 } 39 40 /* 41 * Create the appropriate control structures to manage 42 * a new EHCI host controller. 43 * 44 * Excerpts from linux ehci fsl driver. 45 */ 46 int ehci_hcd_init(int index, enum usb_init_type init, 47 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 48 { 49 struct usb_ehci *ehci = NULL; 50 const char *phy_type = NULL; 51 size_t len; 52 char current_usb_controller[5]; 53 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 54 char usb_phy[5]; 55 56 usb_phy[0] = '\0'; 57 #endif 58 if (has_erratum_a007075()) { 59 /* 60 * A 5ms delay is needed after applying soft-reset to the 61 * controller to let external ULPI phy come out of reset. 62 * This delay needs to be added before re-initializing 63 * the controller after soft-resetting completes 64 */ 65 mdelay(5); 66 } 67 memset(current_usb_controller, '\0', 5); 68 snprintf(current_usb_controller, sizeof(current_usb_controller), 69 "usb%d", index+1); 70 71 switch (index) { 72 case 0: 73 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; 74 break; 75 case 1: 76 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; 77 break; 78 default: 79 printf("ERROR: wrong controller index!!\n"); 80 return -EINVAL; 81 }; 82 83 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 84 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 85 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 86 87 /* Set to Host mode */ 88 setbits_le32(&ehci->usbmode, CM_HOST); 89 90 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); 91 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); 92 93 /* Init phy */ 94 if (hwconfig_sub(current_usb_controller, "phy_type")) 95 phy_type = hwconfig_subarg(current_usb_controller, 96 "phy_type", &len); 97 else 98 phy_type = getenv("usb_phy_type"); 99 100 if (!phy_type) { 101 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 102 /* if none specified assume internal UTMI */ 103 strcpy(usb_phy, "utmi"); 104 phy_type = usb_phy; 105 #else 106 printf("WARNING: USB phy type not defined !!\n"); 107 return -1; 108 #endif 109 } 110 111 if (!strncmp(phy_type, "utmi", 4)) { 112 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) 113 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 114 PHY_CLK_SEL_UTMI); 115 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 116 UTMI_PHY_EN); 117 udelay(1000); /* delay required for PHY Clk to appear */ 118 #endif 119 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); 120 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 121 USB_EN); 122 } else { 123 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 124 PHY_CLK_SEL_ULPI); 125 clrsetbits_be32(&ehci->control, UTMI_PHY_EN | 126 CONTROL_REGISTER_W1C_MASK, USB_EN); 127 udelay(1000); /* delay required for PHY Clk to appear */ 128 if (!usb_phy_clk_valid(ehci)) 129 return -EINVAL; 130 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); 131 } 132 133 out_be32(&ehci->prictrl, 0x0000000c); 134 out_be32(&ehci->age_cnt_limit, 0x00000040); 135 out_be32(&ehci->sictrl, 0x00000001); 136 137 in_le32(&ehci->usbmode); 138 139 if (has_erratum_a007798()) 140 set_txfifothresh(ehci, TXFIFOTHRESH); 141 142 if (has_erratum_a004477()) { 143 /* 144 * When reset is issued while any ULPI transaction is ongoing 145 * then it may result to corruption of ULPI Function Control 146 * Register which eventually causes phy clock to enter low 147 * power mode which stops the clock. Thus delay is required 148 * before reset to let ongoing ULPI transaction complete. 149 */ 150 udelay(1); 151 } 152 return 0; 153 } 154 155 /* 156 * Destroy the appropriate control structures corresponding 157 * the the EHCI host controller. 158 */ 159 int ehci_hcd_stop(int index) 160 { 161 return 0; 162 } 163 164 /* 165 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register 166 * to counter DDR latencies in writing data into Tx buffer. 167 * This prevents Tx buffer from getting underrun 168 */ 169 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) 170 { 171 u32 cmd; 172 cmd = ehci_readl(&ehci->txfilltuning); 173 cmd &= ~TXFIFO_THRESH_MASK; 174 cmd |= TXFIFO_THRESH(txfifo_thresh); 175 ehci_writel(&ehci->txfilltuning, cmd); 176 } 177