1*e9954b86SRene Griessl /* 2*e9954b86SRene Griessl * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> 3*e9954b86SRene Griessl * based on the U-Boot Asix driver as well as information 4*e9954b86SRene Griessl * from the Linux AX88179_178a driver 5*e9954b86SRene Griessl * 6*e9954b86SRene Griessl * SPDX-License-Identifier: GPL-2.0+ 7*e9954b86SRene Griessl */ 8*e9954b86SRene Griessl 9*e9954b86SRene Griessl #include <common.h> 10*e9954b86SRene Griessl #include <usb.h> 11*e9954b86SRene Griessl #include <net.h> 12*e9954b86SRene Griessl #include <linux/mii.h> 13*e9954b86SRene Griessl #include "usb_ether.h" 14*e9954b86SRene Griessl #include <malloc.h> 15*e9954b86SRene Griessl #include <errno.h> 16*e9954b86SRene Griessl 17*e9954b86SRene Griessl /* ASIX AX88179 based USB 3.0 Ethernet Devices */ 18*e9954b86SRene Griessl #define AX88179_PHY_ID 0x03 19*e9954b86SRene Griessl #define AX_EEPROM_LEN 0x100 20*e9954b86SRene Griessl #define AX88179_EEPROM_MAGIC 0x17900b95 21*e9954b86SRene Griessl #define AX_MCAST_FLTSIZE 8 22*e9954b86SRene Griessl #define AX_MAX_MCAST 64 23*e9954b86SRene Griessl #define AX_INT_PPLS_LINK (1 << 16) 24*e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_MASK 0x1c 25*e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_UDP 4 26*e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_TCP 16 27*e9954b86SRene Griessl #define AX_RXHDR_L3CSUM_ERR 2 28*e9954b86SRene Griessl #define AX_RXHDR_L4CSUM_ERR 1 29*e9954b86SRene Griessl #define AX_RXHDR_CRC_ERR (1 << 29) 30*e9954b86SRene Griessl #define AX_RXHDR_DROP_ERR (1 << 31) 31*e9954b86SRene Griessl #define AX_ENDPOINT_INT 0x01 32*e9954b86SRene Griessl #define AX_ENDPOINT_IN 0x02 33*e9954b86SRene Griessl #define AX_ENDPOINT_OUT 0x03 34*e9954b86SRene Griessl #define AX_ACCESS_MAC 0x01 35*e9954b86SRene Griessl #define AX_ACCESS_PHY 0x02 36*e9954b86SRene Griessl #define AX_ACCESS_EEPROM 0x04 37*e9954b86SRene Griessl #define AX_ACCESS_EFUS 0x05 38*e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_HIGH 0x54 39*e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_LOW 0x55 40*e9954b86SRene Griessl 41*e9954b86SRene Griessl #define PHYSICAL_LINK_STATUS 0x02 42*e9954b86SRene Griessl #define AX_USB_SS (1 << 2) 43*e9954b86SRene Griessl #define AX_USB_HS (1 << 1) 44*e9954b86SRene Griessl 45*e9954b86SRene Griessl #define GENERAL_STATUS 0x03 46*e9954b86SRene Griessl #define AX_SECLD (1 << 2) 47*e9954b86SRene Griessl 48*e9954b86SRene Griessl #define AX_SROM_ADDR 0x07 49*e9954b86SRene Griessl #define AX_SROM_CMD 0x0a 50*e9954b86SRene Griessl #define EEP_RD (1 << 2) 51*e9954b86SRene Griessl #define EEP_BUSY (1 << 4) 52*e9954b86SRene Griessl 53*e9954b86SRene Griessl #define AX_SROM_DATA_LOW 0x08 54*e9954b86SRene Griessl #define AX_SROM_DATA_HIGH 0x09 55*e9954b86SRene Griessl 56*e9954b86SRene Griessl #define AX_RX_CTL 0x0b 57*e9954b86SRene Griessl #define AX_RX_CTL_DROPCRCERR (1 << 8) 58*e9954b86SRene Griessl #define AX_RX_CTL_IPE (1 << 9) 59*e9954b86SRene Griessl #define AX_RX_CTL_START (1 << 7) 60*e9954b86SRene Griessl #define AX_RX_CTL_AP (1 << 5) 61*e9954b86SRene Griessl #define AX_RX_CTL_AM (1 << 4) 62*e9954b86SRene Griessl #define AX_RX_CTL_AB (1 << 3) 63*e9954b86SRene Griessl #define AX_RX_CTL_AMALL (1 << 1) 64*e9954b86SRene Griessl #define AX_RX_CTL_PRO (1 << 0) 65*e9954b86SRene Griessl #define AX_RX_CTL_STOP 0 66*e9954b86SRene Griessl 67*e9954b86SRene Griessl #define AX_NODE_ID 0x10 68*e9954b86SRene Griessl #define AX_MULFLTARY 0x16 69*e9954b86SRene Griessl 70*e9954b86SRene Griessl #define AX_MEDIUM_STATUS_MODE 0x22 71*e9954b86SRene Griessl #define AX_MEDIUM_GIGAMODE (1 << 0) 72*e9954b86SRene Griessl #define AX_MEDIUM_FULL_DUPLEX (1 << 1) 73*e9954b86SRene Griessl #define AX_MEDIUM_EN_125MHZ (1 << 3) 74*e9954b86SRene Griessl #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) 75*e9954b86SRene Griessl #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) 76*e9954b86SRene Griessl #define AX_MEDIUM_RECEIVE_EN (1 << 8) 77*e9954b86SRene Griessl #define AX_MEDIUM_PS (1 << 9) 78*e9954b86SRene Griessl #define AX_MEDIUM_JUMBO_EN 0x8040 79*e9954b86SRene Griessl 80*e9954b86SRene Griessl #define AX_MONITOR_MOD 0x24 81*e9954b86SRene Griessl #define AX_MONITOR_MODE_RWLC (1 << 1) 82*e9954b86SRene Griessl #define AX_MONITOR_MODE_RWMP (1 << 2) 83*e9954b86SRene Griessl #define AX_MONITOR_MODE_PMEPOL (1 << 5) 84*e9954b86SRene Griessl #define AX_MONITOR_MODE_PMETYPE (1 << 6) 85*e9954b86SRene Griessl 86*e9954b86SRene Griessl #define AX_GPIO_CTRL 0x25 87*e9954b86SRene Griessl #define AX_GPIO_CTRL_GPIO3EN (1 << 7) 88*e9954b86SRene Griessl #define AX_GPIO_CTRL_GPIO2EN (1 << 6) 89*e9954b86SRene Griessl #define AX_GPIO_CTRL_GPIO1EN (1 << 5) 90*e9954b86SRene Griessl 91*e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL 0x26 92*e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL_BZ (1 << 4) 93*e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) 94*e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL_AT (1 << 12) 95*e9954b86SRene Griessl 96*e9954b86SRene Griessl #define AX_RX_BULKIN_QCTRL 0x2e 97*e9954b86SRene Griessl #define AX_CLK_SELECT 0x33 98*e9954b86SRene Griessl #define AX_CLK_SELECT_BCS (1 << 0) 99*e9954b86SRene Griessl #define AX_CLK_SELECT_ACS (1 << 1) 100*e9954b86SRene Griessl #define AX_CLK_SELECT_ULR (1 << 3) 101*e9954b86SRene Griessl 102*e9954b86SRene Griessl #define AX_RXCOE_CTL 0x34 103*e9954b86SRene Griessl #define AX_RXCOE_IP (1 << 0) 104*e9954b86SRene Griessl #define AX_RXCOE_TCP (1 << 1) 105*e9954b86SRene Griessl #define AX_RXCOE_UDP (1 << 2) 106*e9954b86SRene Griessl #define AX_RXCOE_TCPV6 (1 << 5) 107*e9954b86SRene Griessl #define AX_RXCOE_UDPV6 (1 << 6) 108*e9954b86SRene Griessl 109*e9954b86SRene Griessl #define AX_TXCOE_CTL 0x35 110*e9954b86SRene Griessl #define AX_TXCOE_IP (1 << 0) 111*e9954b86SRene Griessl #define AX_TXCOE_TCP (1 << 1) 112*e9954b86SRene Griessl #define AX_TXCOE_UDP (1 << 2) 113*e9954b86SRene Griessl #define AX_TXCOE_TCPV6 (1 << 5) 114*e9954b86SRene Griessl #define AX_TXCOE_UDPV6 (1 << 6) 115*e9954b86SRene Griessl 116*e9954b86SRene Griessl #define AX_LEDCTRL 0x73 117*e9954b86SRene Griessl 118*e9954b86SRene Griessl #define GMII_PHY_PHYSR 0x11 119*e9954b86SRene Griessl #define GMII_PHY_PHYSR_SMASK 0xc000 120*e9954b86SRene Griessl #define GMII_PHY_PHYSR_GIGA (1 << 15) 121*e9954b86SRene Griessl #define GMII_PHY_PHYSR_100 (1 << 14) 122*e9954b86SRene Griessl #define GMII_PHY_PHYSR_FULL (1 << 13) 123*e9954b86SRene Griessl #define GMII_PHY_PHYSR_LINK (1 << 10) 124*e9954b86SRene Griessl 125*e9954b86SRene Griessl #define GMII_LED_ACT 0x1a 126*e9954b86SRene Griessl #define GMII_LED_ACTIVE_MASK 0xff8f 127*e9954b86SRene Griessl #define GMII_LED0_ACTIVE (1 << 4) 128*e9954b86SRene Griessl #define GMII_LED1_ACTIVE (1 << 5) 129*e9954b86SRene Griessl #define GMII_LED2_ACTIVE (1 << 6) 130*e9954b86SRene Griessl 131*e9954b86SRene Griessl #define GMII_LED_LINK 0x1c 132*e9954b86SRene Griessl #define GMII_LED_LINK_MASK 0xf888 133*e9954b86SRene Griessl #define GMII_LED0_LINK_10 (1 << 0) 134*e9954b86SRene Griessl #define GMII_LED0_LINK_100 (1 << 1) 135*e9954b86SRene Griessl #define GMII_LED0_LINK_1000 (1 << 2) 136*e9954b86SRene Griessl #define GMII_LED1_LINK_10 (1 << 4) 137*e9954b86SRene Griessl #define GMII_LED1_LINK_100 (1 << 5) 138*e9954b86SRene Griessl #define GMII_LED1_LINK_1000 (1 << 6) 139*e9954b86SRene Griessl #define GMII_LED2_LINK_10 (1 << 8) 140*e9954b86SRene Griessl #define GMII_LED2_LINK_100 (1 << 9) 141*e9954b86SRene Griessl #define GMII_LED2_LINK_1000 (1 << 10) 142*e9954b86SRene Griessl #define LED0_ACTIVE (1 << 0) 143*e9954b86SRene Griessl #define LED0_LINK_10 (1 << 1) 144*e9954b86SRene Griessl #define LED0_LINK_100 (1 << 2) 145*e9954b86SRene Griessl #define LED0_LINK_1000 (1 << 3) 146*e9954b86SRene Griessl #define LED0_FD (1 << 4) 147*e9954b86SRene Griessl #define LED0_USB3_MASK 0x001f 148*e9954b86SRene Griessl #define LED1_ACTIVE (1 << 5) 149*e9954b86SRene Griessl #define LED1_LINK_10 (1 << 6) 150*e9954b86SRene Griessl #define LED1_LINK_100 (1 << 7) 151*e9954b86SRene Griessl #define LED1_LINK_1000 (1 << 8) 152*e9954b86SRene Griessl #define LED1_FD (1 << 9) 153*e9954b86SRene Griessl #define LED1_USB3_MASK 0x03e0 154*e9954b86SRene Griessl #define LED2_ACTIVE (1 << 10) 155*e9954b86SRene Griessl #define LED2_LINK_1000 (1 << 13) 156*e9954b86SRene Griessl #define LED2_LINK_100 (1 << 12) 157*e9954b86SRene Griessl #define LED2_LINK_10 (1 << 11) 158*e9954b86SRene Griessl #define LED2_FD (1 << 14) 159*e9954b86SRene Griessl #define LED_VALID (1 << 15) 160*e9954b86SRene Griessl #define LED2_USB3_MASK 0x7c00 161*e9954b86SRene Griessl 162*e9954b86SRene Griessl #define GMII_PHYPAGE 0x1e 163*e9954b86SRene Griessl #define GMII_PHY_PAGE_SELECT 0x1f 164*e9954b86SRene Griessl #define GMII_PHY_PGSEL_EXT 0x0007 165*e9954b86SRene Griessl #define GMII_PHY_PGSEL_PAGE0 0x0000 166*e9954b86SRene Griessl 167*e9954b86SRene Griessl /* local defines */ 168*e9954b86SRene Griessl #define ASIX_BASE_NAME "axg" 169*e9954b86SRene Griessl #define USB_CTRL_SET_TIMEOUT 5000 170*e9954b86SRene Griessl #define USB_CTRL_GET_TIMEOUT 5000 171*e9954b86SRene Griessl #define USB_BULK_SEND_TIMEOUT 5000 172*e9954b86SRene Griessl #define USB_BULK_RECV_TIMEOUT 5000 173*e9954b86SRene Griessl 174*e9954b86SRene Griessl #define AX_RX_URB_SIZE 1024 * 0x12 175*e9954b86SRene Griessl #define BLK_FRAME_SIZE 0x200 176*e9954b86SRene Griessl #define PHY_CONNECT_TIMEOUT 5000 177*e9954b86SRene Griessl 178*e9954b86SRene Griessl #define TIMEOUT_RESOLUTION 50 /* ms */ 179*e9954b86SRene Griessl 180*e9954b86SRene Griessl #define FLAG_NONE 0 181*e9954b86SRene Griessl #define FLAG_TYPE_AX88179 (1U << 0) 182*e9954b86SRene Griessl #define FLAG_TYPE_AX88178a (1U << 1) 183*e9954b86SRene Griessl #define FLAG_TYPE_DLINK_DUB1312 (1U << 2) 184*e9954b86SRene Griessl #define FLAG_TYPE_SITECOM (1U << 3) 185*e9954b86SRene Griessl #define FLAG_TYPE_SAMSUNG (1U << 4) 186*e9954b86SRene Griessl #define FLAG_TYPE_LENOVO (1U << 5) 187*e9954b86SRene Griessl 188*e9954b86SRene Griessl /* local vars */ 189*e9954b86SRene Griessl static const struct { 190*e9954b86SRene Griessl unsigned char ctrl, timer_l, timer_h, size, ifg; 191*e9954b86SRene Griessl } AX88179_BULKIN_SIZE[] = { 192*e9954b86SRene Griessl {7, 0x4f, 0, 0x02, 0xff}, 193*e9954b86SRene Griessl {7, 0x20, 3, 0x03, 0xff}, 194*e9954b86SRene Griessl {7, 0xae, 7, 0x04, 0xff}, 195*e9954b86SRene Griessl {7, 0xcc, 0x4c, 0x04, 8}, 196*e9954b86SRene Griessl }; 197*e9954b86SRene Griessl 198*e9954b86SRene Griessl static int curr_eth_dev; /* index for name of next device detected */ 199*e9954b86SRene Griessl 200*e9954b86SRene Griessl /* driver private */ 201*e9954b86SRene Griessl struct asix_private { 202*e9954b86SRene Griessl int flags; 203*e9954b86SRene Griessl int rx_urb_size; 204*e9954b86SRene Griessl int maxpacketsize; 205*e9954b86SRene Griessl }; 206*e9954b86SRene Griessl 207*e9954b86SRene Griessl /* 208*e9954b86SRene Griessl * Asix infrastructure commands 209*e9954b86SRene Griessl */ 210*e9954b86SRene Griessl static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 211*e9954b86SRene Griessl u16 size, void *data) 212*e9954b86SRene Griessl { 213*e9954b86SRene Griessl int len; 214*e9954b86SRene Griessl ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 215*e9954b86SRene Griessl 216*e9954b86SRene Griessl debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 217*e9954b86SRene Griessl cmd, value, index, size); 218*e9954b86SRene Griessl 219*e9954b86SRene Griessl memcpy(buf, data, size); 220*e9954b86SRene Griessl 221*e9954b86SRene Griessl len = usb_control_msg( 222*e9954b86SRene Griessl dev->pusb_dev, 223*e9954b86SRene Griessl usb_sndctrlpipe(dev->pusb_dev, 0), 224*e9954b86SRene Griessl cmd, 225*e9954b86SRene Griessl USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 226*e9954b86SRene Griessl value, 227*e9954b86SRene Griessl index, 228*e9954b86SRene Griessl buf, 229*e9954b86SRene Griessl size, 230*e9954b86SRene Griessl USB_CTRL_SET_TIMEOUT); 231*e9954b86SRene Griessl 232*e9954b86SRene Griessl return len == size ? 0 : ECOMM; 233*e9954b86SRene Griessl } 234*e9954b86SRene Griessl 235*e9954b86SRene Griessl static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 236*e9954b86SRene Griessl u16 size, void *data) 237*e9954b86SRene Griessl { 238*e9954b86SRene Griessl int len; 239*e9954b86SRene Griessl ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 240*e9954b86SRene Griessl 241*e9954b86SRene Griessl debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 242*e9954b86SRene Griessl cmd, value, index, size); 243*e9954b86SRene Griessl 244*e9954b86SRene Griessl len = usb_control_msg( 245*e9954b86SRene Griessl dev->pusb_dev, 246*e9954b86SRene Griessl usb_rcvctrlpipe(dev->pusb_dev, 0), 247*e9954b86SRene Griessl cmd, 248*e9954b86SRene Griessl USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 249*e9954b86SRene Griessl value, 250*e9954b86SRene Griessl index, 251*e9954b86SRene Griessl buf, 252*e9954b86SRene Griessl size, 253*e9954b86SRene Griessl USB_CTRL_GET_TIMEOUT); 254*e9954b86SRene Griessl 255*e9954b86SRene Griessl memcpy(data, buf, size); 256*e9954b86SRene Griessl 257*e9954b86SRene Griessl return len == size ? 0 : ECOMM; 258*e9954b86SRene Griessl } 259*e9954b86SRene Griessl 260*e9954b86SRene Griessl static int asix_read_mac(struct eth_device *eth) 261*e9954b86SRene Griessl { 262*e9954b86SRene Griessl struct ueth_data *dev = (struct ueth_data *)eth->priv; 263*e9954b86SRene Griessl u8 buf[ETH_ALEN]; 264*e9954b86SRene Griessl 265*e9954b86SRene Griessl asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); 266*e9954b86SRene Griessl debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", 267*e9954b86SRene Griessl buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); 268*e9954b86SRene Griessl 269*e9954b86SRene Griessl memcpy(eth->enetaddr, buf, ETH_ALEN); 270*e9954b86SRene Griessl 271*e9954b86SRene Griessl return 0; 272*e9954b86SRene Griessl } 273*e9954b86SRene Griessl 274*e9954b86SRene Griessl static int asix_basic_reset(struct ueth_data *dev) 275*e9954b86SRene Griessl { 276*e9954b86SRene Griessl struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 277*e9954b86SRene Griessl u8 buf[5]; 278*e9954b86SRene Griessl u16 *tmp16; 279*e9954b86SRene Griessl u8 *tmp; 280*e9954b86SRene Griessl 281*e9954b86SRene Griessl tmp16 = (u16 *)buf; 282*e9954b86SRene Griessl tmp = (u8 *)buf; 283*e9954b86SRene Griessl 284*e9954b86SRene Griessl /* Power up ethernet PHY */ 285*e9954b86SRene Griessl *tmp16 = 0; 286*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 287*e9954b86SRene Griessl 288*e9954b86SRene Griessl *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 289*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 290*e9954b86SRene Griessl mdelay(200); 291*e9954b86SRene Griessl 292*e9954b86SRene Griessl *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 293*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 294*e9954b86SRene Griessl mdelay(200); 295*e9954b86SRene Griessl 296*e9954b86SRene Griessl /* RX bulk configuration */ 297*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 298*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 299*e9954b86SRene Griessl 300*e9954b86SRene Griessl dev_priv->rx_urb_size = 128 * 20; 301*e9954b86SRene Griessl 302*e9954b86SRene Griessl /* Water Level configuration */ 303*e9954b86SRene Griessl *tmp = 0x34; 304*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 305*e9954b86SRene Griessl 306*e9954b86SRene Griessl *tmp = 0x52; 307*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); 308*e9954b86SRene Griessl 309*e9954b86SRene Griessl /* Enable checksum offload */ 310*e9954b86SRene Griessl *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 311*e9954b86SRene Griessl AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 312*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 313*e9954b86SRene Griessl 314*e9954b86SRene Griessl *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 315*e9954b86SRene Griessl AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 316*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 317*e9954b86SRene Griessl 318*e9954b86SRene Griessl /* Configure RX control register => start operation */ 319*e9954b86SRene Griessl *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 320*e9954b86SRene Griessl AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 321*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 322*e9954b86SRene Griessl 323*e9954b86SRene Griessl *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 324*e9954b86SRene Griessl AX_MONITOR_MODE_RWMP; 325*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 326*e9954b86SRene Griessl 327*e9954b86SRene Griessl /* Configure default medium type => giga */ 328*e9954b86SRene Griessl *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 329*e9954b86SRene Griessl AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 330*e9954b86SRene Griessl AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; 331*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); 332*e9954b86SRene Griessl 333*e9954b86SRene Griessl u16 adv = 0; 334*e9954b86SRene Griessl adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | 335*e9954b86SRene Griessl ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; 336*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); 337*e9954b86SRene Griessl 338*e9954b86SRene Griessl adv = ADVERTISE_1000FULL; 339*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); 340*e9954b86SRene Griessl 341*e9954b86SRene Griessl return 0; 342*e9954b86SRene Griessl } 343*e9954b86SRene Griessl 344*e9954b86SRene Griessl static int asix_wait_link(struct ueth_data *dev) 345*e9954b86SRene Griessl { 346*e9954b86SRene Griessl int timeout = 0; 347*e9954b86SRene Griessl int link_detected; 348*e9954b86SRene Griessl u8 buf[2]; 349*e9954b86SRene Griessl u16 *tmp16; 350*e9954b86SRene Griessl 351*e9954b86SRene Griessl tmp16 = (u16 *)buf; 352*e9954b86SRene Griessl 353*e9954b86SRene Griessl do { 354*e9954b86SRene Griessl asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 355*e9954b86SRene Griessl MII_BMSR, 2, buf); 356*e9954b86SRene Griessl link_detected = *tmp16 & BMSR_LSTATUS; 357*e9954b86SRene Griessl if (!link_detected) { 358*e9954b86SRene Griessl if (timeout == 0) 359*e9954b86SRene Griessl printf("Waiting for Ethernet connection... "); 360*e9954b86SRene Griessl mdelay(TIMEOUT_RESOLUTION); 361*e9954b86SRene Griessl timeout += TIMEOUT_RESOLUTION; 362*e9954b86SRene Griessl } 363*e9954b86SRene Griessl } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 364*e9954b86SRene Griessl 365*e9954b86SRene Griessl if (link_detected) { 366*e9954b86SRene Griessl if (timeout > 0) 367*e9954b86SRene Griessl printf("done.\n"); 368*e9954b86SRene Griessl return 0; 369*e9954b86SRene Griessl } else { 370*e9954b86SRene Griessl printf("unable to connect.\n"); 371*e9954b86SRene Griessl return -ENETUNREACH; 372*e9954b86SRene Griessl } 373*e9954b86SRene Griessl } 374*e9954b86SRene Griessl 375*e9954b86SRene Griessl /* 376*e9954b86SRene Griessl * Asix callbacks 377*e9954b86SRene Griessl */ 378*e9954b86SRene Griessl static int asix_init(struct eth_device *eth, bd_t *bd) 379*e9954b86SRene Griessl { 380*e9954b86SRene Griessl struct ueth_data *dev = (struct ueth_data *)eth->priv; 381*e9954b86SRene Griessl struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 382*e9954b86SRene Griessl u8 buf[2], tmp[5], link_sts; 383*e9954b86SRene Griessl u16 *tmp16, mode; 384*e9954b86SRene Griessl 385*e9954b86SRene Griessl 386*e9954b86SRene Griessl tmp16 = (u16 *)buf; 387*e9954b86SRene Griessl 388*e9954b86SRene Griessl debug("** %s()\n", __func__); 389*e9954b86SRene Griessl 390*e9954b86SRene Griessl /* Configure RX control register => start operation */ 391*e9954b86SRene Griessl *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 392*e9954b86SRene Griessl AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 393*e9954b86SRene Griessl if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) 394*e9954b86SRene Griessl goto out_err; 395*e9954b86SRene Griessl 396*e9954b86SRene Griessl if (asix_wait_link(dev) != 0) { 397*e9954b86SRene Griessl /*reset device and try again*/ 398*e9954b86SRene Griessl printf("Reset Ethernet Device\n"); 399*e9954b86SRene Griessl asix_basic_reset(dev); 400*e9954b86SRene Griessl if (asix_wait_link(dev) != 0) 401*e9954b86SRene Griessl goto out_err; 402*e9954b86SRene Griessl } 403*e9954b86SRene Griessl 404*e9954b86SRene Griessl /* Configure link */ 405*e9954b86SRene Griessl mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 406*e9954b86SRene Griessl AX_MEDIUM_RXFLOW_CTRLEN; 407*e9954b86SRene Griessl 408*e9954b86SRene Griessl asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 409*e9954b86SRene Griessl 1, 1, &link_sts); 410*e9954b86SRene Griessl 411*e9954b86SRene Griessl asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 412*e9954b86SRene Griessl GMII_PHY_PHYSR, 2, tmp16); 413*e9954b86SRene Griessl 414*e9954b86SRene Griessl if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { 415*e9954b86SRene Griessl return 0; 416*e9954b86SRene Griessl } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 417*e9954b86SRene Griessl mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | 418*e9954b86SRene Griessl AX_MEDIUM_JUMBO_EN; 419*e9954b86SRene Griessl 420*e9954b86SRene Griessl if (link_sts & AX_USB_SS) 421*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 422*e9954b86SRene Griessl else if (link_sts & AX_USB_HS) 423*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 424*e9954b86SRene Griessl else 425*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 426*e9954b86SRene Griessl } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 427*e9954b86SRene Griessl mode |= AX_MEDIUM_PS; 428*e9954b86SRene Griessl 429*e9954b86SRene Griessl if (link_sts & (AX_USB_SS | AX_USB_HS)) 430*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 431*e9954b86SRene Griessl else 432*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 433*e9954b86SRene Griessl } else { 434*e9954b86SRene Griessl memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 435*e9954b86SRene Griessl } 436*e9954b86SRene Griessl 437*e9954b86SRene Griessl /* RX bulk configuration */ 438*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 439*e9954b86SRene Griessl 440*e9954b86SRene Griessl dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); 441*e9954b86SRene Griessl if (*tmp16 & GMII_PHY_PHYSR_FULL) 442*e9954b86SRene Griessl mode |= AX_MEDIUM_FULL_DUPLEX; 443*e9954b86SRene Griessl asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 444*e9954b86SRene Griessl 2, 2, &mode); 445*e9954b86SRene Griessl 446*e9954b86SRene Griessl return 0; 447*e9954b86SRene Griessl out_err: 448*e9954b86SRene Griessl return -1; 449*e9954b86SRene Griessl } 450*e9954b86SRene Griessl 451*e9954b86SRene Griessl static int asix_send(struct eth_device *eth, void *packet, int length) 452*e9954b86SRene Griessl { 453*e9954b86SRene Griessl struct ueth_data *dev = (struct ueth_data *)eth->priv; 454*e9954b86SRene Griessl struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 455*e9954b86SRene Griessl 456*e9954b86SRene Griessl int err; 457*e9954b86SRene Griessl u32 packet_len, tx_hdr2; 458*e9954b86SRene Griessl int actual_len, framesize; 459*e9954b86SRene Griessl ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 460*e9954b86SRene Griessl PKTSIZE + (2 * sizeof(packet_len))); 461*e9954b86SRene Griessl 462*e9954b86SRene Griessl debug("** %s(), len %d\n", __func__, length); 463*e9954b86SRene Griessl 464*e9954b86SRene Griessl packet_len = length; 465*e9954b86SRene Griessl cpu_to_le32s(&packet_len); 466*e9954b86SRene Griessl 467*e9954b86SRene Griessl memcpy(msg, &packet_len, sizeof(packet_len)); 468*e9954b86SRene Griessl framesize = dev_priv->maxpacketsize; 469*e9954b86SRene Griessl tx_hdr2 = 0; 470*e9954b86SRene Griessl if (((length + 8) % framesize) == 0) 471*e9954b86SRene Griessl tx_hdr2 |= 0x80008000; /* Enable padding */ 472*e9954b86SRene Griessl 473*e9954b86SRene Griessl cpu_to_le32s(&tx_hdr2); 474*e9954b86SRene Griessl 475*e9954b86SRene Griessl memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); 476*e9954b86SRene Griessl 477*e9954b86SRene Griessl memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), 478*e9954b86SRene Griessl (void *)packet, length); 479*e9954b86SRene Griessl 480*e9954b86SRene Griessl err = usb_bulk_msg(dev->pusb_dev, 481*e9954b86SRene Griessl usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 482*e9954b86SRene Griessl (void *)msg, 483*e9954b86SRene Griessl length + sizeof(packet_len) + sizeof(tx_hdr2), 484*e9954b86SRene Griessl &actual_len, 485*e9954b86SRene Griessl USB_BULK_SEND_TIMEOUT); 486*e9954b86SRene Griessl debug("Tx: len = %u, actual = %u, err = %d\n", 487*e9954b86SRene Griessl length + sizeof(packet_len), actual_len, err); 488*e9954b86SRene Griessl 489*e9954b86SRene Griessl return err; 490*e9954b86SRene Griessl } 491*e9954b86SRene Griessl 492*e9954b86SRene Griessl static int asix_recv(struct eth_device *eth) 493*e9954b86SRene Griessl { 494*e9954b86SRene Griessl struct ueth_data *dev = (struct ueth_data *)eth->priv; 495*e9954b86SRene Griessl struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 496*e9954b86SRene Griessl 497*e9954b86SRene Griessl u16 frame_pos; 498*e9954b86SRene Griessl int err; 499*e9954b86SRene Griessl int actual_len; 500*e9954b86SRene Griessl 501*e9954b86SRene Griessl int pkt_cnt; 502*e9954b86SRene Griessl u32 rx_hdr; 503*e9954b86SRene Griessl u16 hdr_off; 504*e9954b86SRene Griessl u32 *pkt_hdr; 505*e9954b86SRene Griessl ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); 506*e9954b86SRene Griessl 507*e9954b86SRene Griessl actual_len = -1; 508*e9954b86SRene Griessl 509*e9954b86SRene Griessl debug("** %s()\n", __func__); 510*e9954b86SRene Griessl 511*e9954b86SRene Griessl err = usb_bulk_msg(dev->pusb_dev, 512*e9954b86SRene Griessl usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 513*e9954b86SRene Griessl (void *)recv_buf, 514*e9954b86SRene Griessl dev_priv->rx_urb_size, 515*e9954b86SRene Griessl &actual_len, 516*e9954b86SRene Griessl USB_BULK_RECV_TIMEOUT); 517*e9954b86SRene Griessl debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, 518*e9954b86SRene Griessl actual_len, err); 519*e9954b86SRene Griessl 520*e9954b86SRene Griessl if (err != 0) { 521*e9954b86SRene Griessl debug("Rx: failed to receive\n"); 522*e9954b86SRene Griessl return -ECOMM; 523*e9954b86SRene Griessl } 524*e9954b86SRene Griessl if (actual_len > dev_priv->rx_urb_size) { 525*e9954b86SRene Griessl debug("Rx: received too many bytes %d\n", actual_len); 526*e9954b86SRene Griessl return -EMSGSIZE; 527*e9954b86SRene Griessl } 528*e9954b86SRene Griessl 529*e9954b86SRene Griessl 530*e9954b86SRene Griessl rx_hdr = *(u32 *)(recv_buf + actual_len - 4); 531*e9954b86SRene Griessl le32_to_cpus(&pkt_hdr); 532*e9954b86SRene Griessl 533*e9954b86SRene Griessl pkt_cnt = (u16)rx_hdr; 534*e9954b86SRene Griessl hdr_off = (u16)(rx_hdr >> 16); 535*e9954b86SRene Griessl pkt_hdr = (u32 *)(recv_buf + hdr_off); 536*e9954b86SRene Griessl 537*e9954b86SRene Griessl 538*e9954b86SRene Griessl frame_pos = 0; 539*e9954b86SRene Griessl 540*e9954b86SRene Griessl while (pkt_cnt--) { 541*e9954b86SRene Griessl u16 pkt_len; 542*e9954b86SRene Griessl 543*e9954b86SRene Griessl le32_to_cpus(pkt_hdr); 544*e9954b86SRene Griessl pkt_len = (*pkt_hdr >> 16) & 0x1fff; 545*e9954b86SRene Griessl 546*e9954b86SRene Griessl frame_pos += 2; 547*e9954b86SRene Griessl 548*e9954b86SRene Griessl NetReceive(recv_buf + frame_pos, pkt_len); 549*e9954b86SRene Griessl 550*e9954b86SRene Griessl pkt_hdr++; 551*e9954b86SRene Griessl frame_pos += ((pkt_len + 7) & 0xFFF8)-2; 552*e9954b86SRene Griessl 553*e9954b86SRene Griessl if (pkt_cnt == 0) 554*e9954b86SRene Griessl return 0; 555*e9954b86SRene Griessl } 556*e9954b86SRene Griessl return err; 557*e9954b86SRene Griessl } 558*e9954b86SRene Griessl 559*e9954b86SRene Griessl static void asix_halt(struct eth_device *eth) 560*e9954b86SRene Griessl { 561*e9954b86SRene Griessl debug("** %s()\n", __func__); 562*e9954b86SRene Griessl } 563*e9954b86SRene Griessl 564*e9954b86SRene Griessl /* 565*e9954b86SRene Griessl * Asix probing functions 566*e9954b86SRene Griessl */ 567*e9954b86SRene Griessl void ax88179_eth_before_probe(void) 568*e9954b86SRene Griessl { 569*e9954b86SRene Griessl curr_eth_dev = 0; 570*e9954b86SRene Griessl } 571*e9954b86SRene Griessl 572*e9954b86SRene Griessl struct asix_dongle { 573*e9954b86SRene Griessl unsigned short vendor; 574*e9954b86SRene Griessl unsigned short product; 575*e9954b86SRene Griessl int flags; 576*e9954b86SRene Griessl }; 577*e9954b86SRene Griessl 578*e9954b86SRene Griessl static const struct asix_dongle asix_dongles[] = { 579*e9954b86SRene Griessl { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, 580*e9954b86SRene Griessl { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, 581*e9954b86SRene Griessl { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, 582*e9954b86SRene Griessl { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, 583*e9954b86SRene Griessl { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, 584*e9954b86SRene Griessl { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, 585*e9954b86SRene Griessl { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 586*e9954b86SRene Griessl }; 587*e9954b86SRene Griessl 588*e9954b86SRene Griessl /* Probe to see if a new device is actually an asix device */ 589*e9954b86SRene Griessl int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, 590*e9954b86SRene Griessl struct ueth_data *ss) 591*e9954b86SRene Griessl { 592*e9954b86SRene Griessl struct usb_interface *iface; 593*e9954b86SRene Griessl struct usb_interface_descriptor *iface_desc; 594*e9954b86SRene Griessl struct asix_private *dev_priv; 595*e9954b86SRene Griessl int ep_in_found = 0, ep_out_found = 0; 596*e9954b86SRene Griessl int i; 597*e9954b86SRene Griessl 598*e9954b86SRene Griessl /* let's examine the device now */ 599*e9954b86SRene Griessl iface = &dev->config.if_desc[ifnum]; 600*e9954b86SRene Griessl iface_desc = &dev->config.if_desc[ifnum].desc; 601*e9954b86SRene Griessl 602*e9954b86SRene Griessl for (i = 0; asix_dongles[i].vendor != 0; i++) { 603*e9954b86SRene Griessl if (dev->descriptor.idVendor == asix_dongles[i].vendor && 604*e9954b86SRene Griessl dev->descriptor.idProduct == asix_dongles[i].product) 605*e9954b86SRene Griessl /* Found a supported dongle */ 606*e9954b86SRene Griessl break; 607*e9954b86SRene Griessl } 608*e9954b86SRene Griessl 609*e9954b86SRene Griessl if (asix_dongles[i].vendor == 0) 610*e9954b86SRene Griessl return 0; 611*e9954b86SRene Griessl 612*e9954b86SRene Griessl memset(ss, 0, sizeof(struct ueth_data)); 613*e9954b86SRene Griessl 614*e9954b86SRene Griessl /* At this point, we know we've got a live one */ 615*e9954b86SRene Griessl debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 616*e9954b86SRene Griessl dev->descriptor.idVendor, dev->descriptor.idProduct); 617*e9954b86SRene Griessl 618*e9954b86SRene Griessl /* Initialize the ueth_data structure with some useful info */ 619*e9954b86SRene Griessl ss->ifnum = ifnum; 620*e9954b86SRene Griessl ss->pusb_dev = dev; 621*e9954b86SRene Griessl ss->subclass = iface_desc->bInterfaceSubClass; 622*e9954b86SRene Griessl ss->protocol = iface_desc->bInterfaceProtocol; 623*e9954b86SRene Griessl 624*e9954b86SRene Griessl /* alloc driver private */ 625*e9954b86SRene Griessl ss->dev_priv = calloc(1, sizeof(struct asix_private)); 626*e9954b86SRene Griessl if (!ss->dev_priv) 627*e9954b86SRene Griessl return 0; 628*e9954b86SRene Griessl dev_priv = ss->dev_priv; 629*e9954b86SRene Griessl dev_priv->flags = asix_dongles[i].flags; 630*e9954b86SRene Griessl 631*e9954b86SRene Griessl /* 632*e9954b86SRene Griessl * We are expecting a minimum of 3 endpoints - in, out (bulk), and 633*e9954b86SRene Griessl * int. We will ignore any others. 634*e9954b86SRene Griessl */ 635*e9954b86SRene Griessl for (i = 0; i < iface_desc->bNumEndpoints; i++) { 636*e9954b86SRene Griessl /* is it an interrupt endpoint? */ 637*e9954b86SRene Griessl if ((iface->ep_desc[i].bmAttributes & 638*e9954b86SRene Griessl USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 639*e9954b86SRene Griessl ss->ep_int = iface->ep_desc[i].bEndpointAddress & 640*e9954b86SRene Griessl USB_ENDPOINT_NUMBER_MASK; 641*e9954b86SRene Griessl ss->irqinterval = iface->ep_desc[i].bInterval; 642*e9954b86SRene Griessl continue; 643*e9954b86SRene Griessl } 644*e9954b86SRene Griessl 645*e9954b86SRene Griessl /* is it an BULK endpoint? */ 646*e9954b86SRene Griessl if (!((iface->ep_desc[i].bmAttributes & 647*e9954b86SRene Griessl USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) 648*e9954b86SRene Griessl continue; 649*e9954b86SRene Griessl 650*e9954b86SRene Griessl u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 651*e9954b86SRene Griessl if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 652*e9954b86SRene Griessl ss->ep_in = ep_addr & 653*e9954b86SRene Griessl USB_ENDPOINT_NUMBER_MASK; 654*e9954b86SRene Griessl ep_in_found = 1; 655*e9954b86SRene Griessl } 656*e9954b86SRene Griessl if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { 657*e9954b86SRene Griessl ss->ep_out = ep_addr & 658*e9954b86SRene Griessl USB_ENDPOINT_NUMBER_MASK; 659*e9954b86SRene Griessl dev_priv->maxpacketsize = 660*e9954b86SRene Griessl dev->epmaxpacketout[AX_ENDPOINT_OUT]; 661*e9954b86SRene Griessl ep_out_found = 1; 662*e9954b86SRene Griessl } 663*e9954b86SRene Griessl } 664*e9954b86SRene Griessl debug("Endpoints In %d Out %d Int %d\n", 665*e9954b86SRene Griessl ss->ep_in, ss->ep_out, ss->ep_int); 666*e9954b86SRene Griessl 667*e9954b86SRene Griessl /* Do some basic sanity checks, and bail if we find a problem */ 668*e9954b86SRene Griessl if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 669*e9954b86SRene Griessl !ss->ep_in || !ss->ep_out || !ss->ep_int) { 670*e9954b86SRene Griessl debug("Problems with device\n"); 671*e9954b86SRene Griessl return 0; 672*e9954b86SRene Griessl } 673*e9954b86SRene Griessl dev->privptr = (void *)ss; 674*e9954b86SRene Griessl return 1; 675*e9954b86SRene Griessl } 676*e9954b86SRene Griessl 677*e9954b86SRene Griessl int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 678*e9954b86SRene Griessl struct eth_device *eth) 679*e9954b86SRene Griessl { 680*e9954b86SRene Griessl if (!eth) { 681*e9954b86SRene Griessl debug("%s: missing parameter.\n", __func__); 682*e9954b86SRene Griessl return 0; 683*e9954b86SRene Griessl } 684*e9954b86SRene Griessl sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 685*e9954b86SRene Griessl eth->init = asix_init; 686*e9954b86SRene Griessl eth->send = asix_send; 687*e9954b86SRene Griessl eth->recv = asix_recv; 688*e9954b86SRene Griessl eth->halt = asix_halt; 689*e9954b86SRene Griessl eth->priv = ss; 690*e9954b86SRene Griessl 691*e9954b86SRene Griessl if (asix_basic_reset(ss)) 692*e9954b86SRene Griessl return 0; 693*e9954b86SRene Griessl 694*e9954b86SRene Griessl /* Get the MAC address */ 695*e9954b86SRene Griessl if (asix_read_mac(eth)) 696*e9954b86SRene Griessl return 0; 697*e9954b86SRene Griessl debug("MAC %pM\n", eth->enetaddr); 698*e9954b86SRene Griessl 699*e9954b86SRene Griessl return 1; 700*e9954b86SRene Griessl } 701