xref: /openbmc/u-boot/drivers/usb/eth/asix88179.c (revision 620452e7aed023205d9432e0f3476906018ad688)
1e9954b86SRene Griessl /*
2e9954b86SRene Griessl  * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
3e9954b86SRene Griessl  * based on the U-Boot Asix driver as well as information
4e9954b86SRene Griessl  * from the Linux AX88179_178a driver
5e9954b86SRene Griessl  *
6e9954b86SRene Griessl  * SPDX-License-Identifier:	GPL-2.0+
7e9954b86SRene Griessl  */
8e9954b86SRene Griessl 
9e9954b86SRene Griessl #include <common.h>
10e9954b86SRene Griessl #include <usb.h>
11e9954b86SRene Griessl #include <net.h>
12e9954b86SRene Griessl #include <linux/mii.h>
13e9954b86SRene Griessl #include "usb_ether.h"
14e9954b86SRene Griessl #include <malloc.h>
15cf92e05cSSimon Glass #include <memalign.h>
16e9954b86SRene Griessl #include <errno.h>
17e9954b86SRene Griessl 
18e9954b86SRene Griessl /* ASIX AX88179 based USB 3.0 Ethernet Devices */
19e9954b86SRene Griessl #define AX88179_PHY_ID				0x03
20e9954b86SRene Griessl #define AX_EEPROM_LEN				0x100
21e9954b86SRene Griessl #define AX88179_EEPROM_MAGIC			0x17900b95
22e9954b86SRene Griessl #define AX_MCAST_FLTSIZE			8
23e9954b86SRene Griessl #define AX_MAX_MCAST				64
24e9954b86SRene Griessl #define AX_INT_PPLS_LINK			(1 << 16)
25e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_MASK			0x1c
26e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_UDP			4
27e9954b86SRene Griessl #define AX_RXHDR_L4_TYPE_TCP			16
28e9954b86SRene Griessl #define AX_RXHDR_L3CSUM_ERR			2
29e9954b86SRene Griessl #define AX_RXHDR_L4CSUM_ERR			1
30e9954b86SRene Griessl #define AX_RXHDR_CRC_ERR			(1 << 29)
31e9954b86SRene Griessl #define AX_RXHDR_DROP_ERR			(1 << 31)
32e9954b86SRene Griessl #define AX_ENDPOINT_INT				0x01
33e9954b86SRene Griessl #define AX_ENDPOINT_IN				0x02
34e9954b86SRene Griessl #define AX_ENDPOINT_OUT				0x03
35e9954b86SRene Griessl #define AX_ACCESS_MAC				0x01
36e9954b86SRene Griessl #define AX_ACCESS_PHY				0x02
37e9954b86SRene Griessl #define AX_ACCESS_EEPROM			0x04
38e9954b86SRene Griessl #define AX_ACCESS_EFUS				0x05
39e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_HIGH			0x54
40e9954b86SRene Griessl #define AX_PAUSE_WATERLVL_LOW			0x55
41e9954b86SRene Griessl 
42e9954b86SRene Griessl #define PHYSICAL_LINK_STATUS			0x02
43e9954b86SRene Griessl 	#define	AX_USB_SS		(1 << 2)
44e9954b86SRene Griessl 	#define	AX_USB_HS		(1 << 1)
45e9954b86SRene Griessl 
46e9954b86SRene Griessl #define GENERAL_STATUS				0x03
47e9954b86SRene Griessl 	#define	AX_SECLD		(1 << 2)
48e9954b86SRene Griessl 
49e9954b86SRene Griessl #define AX_SROM_ADDR				0x07
50e9954b86SRene Griessl #define AX_SROM_CMD				0x0a
51e9954b86SRene Griessl 	#define EEP_RD			(1 << 2)
52e9954b86SRene Griessl 	#define EEP_BUSY		(1 << 4)
53e9954b86SRene Griessl 
54e9954b86SRene Griessl #define AX_SROM_DATA_LOW			0x08
55e9954b86SRene Griessl #define AX_SROM_DATA_HIGH			0x09
56e9954b86SRene Griessl 
57e9954b86SRene Griessl #define AX_RX_CTL				0x0b
58e9954b86SRene Griessl 	#define AX_RX_CTL_DROPCRCERR	(1 << 8)
59e9954b86SRene Griessl 	#define AX_RX_CTL_IPE		(1 << 9)
60e9954b86SRene Griessl 	#define AX_RX_CTL_START		(1 << 7)
61e9954b86SRene Griessl 	#define AX_RX_CTL_AP		(1 << 5)
62e9954b86SRene Griessl 	#define AX_RX_CTL_AM		(1 << 4)
63e9954b86SRene Griessl 	#define AX_RX_CTL_AB		(1 << 3)
64e9954b86SRene Griessl 	#define AX_RX_CTL_AMALL		(1 << 1)
65e9954b86SRene Griessl 	#define AX_RX_CTL_PRO		(1 << 0)
66e9954b86SRene Griessl 	#define AX_RX_CTL_STOP		0
67e9954b86SRene Griessl 
68e9954b86SRene Griessl #define AX_NODE_ID				0x10
69e9954b86SRene Griessl #define AX_MULFLTARY				0x16
70e9954b86SRene Griessl 
71e9954b86SRene Griessl #define AX_MEDIUM_STATUS_MODE			0x22
72e9954b86SRene Griessl 	#define AX_MEDIUM_GIGAMODE	(1 << 0)
73e9954b86SRene Griessl 	#define AX_MEDIUM_FULL_DUPLEX	(1 << 1)
74e9954b86SRene Griessl 	#define AX_MEDIUM_EN_125MHZ	(1 << 3)
75e9954b86SRene Griessl 	#define AX_MEDIUM_RXFLOW_CTRLEN	(1 << 4)
76e9954b86SRene Griessl 	#define AX_MEDIUM_TXFLOW_CTRLEN	(1 << 5)
77e9954b86SRene Griessl 	#define AX_MEDIUM_RECEIVE_EN	(1 << 8)
78e9954b86SRene Griessl 	#define AX_MEDIUM_PS		(1 << 9)
79e9954b86SRene Griessl 	#define AX_MEDIUM_JUMBO_EN	0x8040
80e9954b86SRene Griessl 
81e9954b86SRene Griessl #define AX_MONITOR_MOD				0x24
82e9954b86SRene Griessl 	#define AX_MONITOR_MODE_RWLC	(1 << 1)
83e9954b86SRene Griessl 	#define AX_MONITOR_MODE_RWMP	(1 << 2)
84e9954b86SRene Griessl 	#define AX_MONITOR_MODE_PMEPOL	(1 << 5)
85e9954b86SRene Griessl 	#define AX_MONITOR_MODE_PMETYPE	(1 << 6)
86e9954b86SRene Griessl 
87e9954b86SRene Griessl #define AX_GPIO_CTRL				0x25
88e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO3EN	(1 << 7)
89e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO2EN	(1 << 6)
90e9954b86SRene Griessl 	#define AX_GPIO_CTRL_GPIO1EN	(1 << 5)
91e9954b86SRene Griessl 
92e9954b86SRene Griessl #define AX_PHYPWR_RSTCTL			0x26
93e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_BZ	(1 << 4)
94e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_IPRL	(1 << 5)
95e9954b86SRene Griessl 	#define AX_PHYPWR_RSTCTL_AT	(1 << 12)
96e9954b86SRene Griessl 
97e9954b86SRene Griessl #define AX_RX_BULKIN_QCTRL			0x2e
98e9954b86SRene Griessl #define AX_CLK_SELECT				0x33
99e9954b86SRene Griessl 	#define AX_CLK_SELECT_BCS	(1 << 0)
100e9954b86SRene Griessl 	#define AX_CLK_SELECT_ACS	(1 << 1)
101e9954b86SRene Griessl 	#define AX_CLK_SELECT_ULR	(1 << 3)
102e9954b86SRene Griessl 
103e9954b86SRene Griessl #define AX_RXCOE_CTL				0x34
104e9954b86SRene Griessl 	#define AX_RXCOE_IP		(1 << 0)
105e9954b86SRene Griessl 	#define AX_RXCOE_TCP		(1 << 1)
106e9954b86SRene Griessl 	#define AX_RXCOE_UDP		(1 << 2)
107e9954b86SRene Griessl 	#define AX_RXCOE_TCPV6		(1 << 5)
108e9954b86SRene Griessl 	#define AX_RXCOE_UDPV6		(1 << 6)
109e9954b86SRene Griessl 
110e9954b86SRene Griessl #define AX_TXCOE_CTL				0x35
111e9954b86SRene Griessl 	#define AX_TXCOE_IP		(1 << 0)
112e9954b86SRene Griessl 	#define AX_TXCOE_TCP		(1 << 1)
113e9954b86SRene Griessl 	#define AX_TXCOE_UDP		(1 << 2)
114e9954b86SRene Griessl 	#define AX_TXCOE_TCPV6		(1 << 5)
115e9954b86SRene Griessl 	#define AX_TXCOE_UDPV6		(1 << 6)
116e9954b86SRene Griessl 
117e9954b86SRene Griessl #define AX_LEDCTRL				0x73
118e9954b86SRene Griessl 
119e9954b86SRene Griessl #define GMII_PHY_PHYSR				0x11
120e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_SMASK	0xc000
121e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_GIGA	(1 << 15)
122e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_100	(1 << 14)
123e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_FULL	(1 << 13)
124e9954b86SRene Griessl 	#define GMII_PHY_PHYSR_LINK	(1 << 10)
125e9954b86SRene Griessl 
126e9954b86SRene Griessl #define GMII_LED_ACT				0x1a
127e9954b86SRene Griessl 	#define	GMII_LED_ACTIVE_MASK	0xff8f
128e9954b86SRene Griessl 	#define	GMII_LED0_ACTIVE	(1 << 4)
129e9954b86SRene Griessl 	#define	GMII_LED1_ACTIVE	(1 << 5)
130e9954b86SRene Griessl 	#define	GMII_LED2_ACTIVE	(1 << 6)
131e9954b86SRene Griessl 
132e9954b86SRene Griessl #define GMII_LED_LINK				0x1c
133e9954b86SRene Griessl 	#define	GMII_LED_LINK_MASK	0xf888
134e9954b86SRene Griessl 	#define	GMII_LED0_LINK_10	(1 << 0)
135e9954b86SRene Griessl 	#define	GMII_LED0_LINK_100	(1 << 1)
136e9954b86SRene Griessl 	#define	GMII_LED0_LINK_1000	(1 << 2)
137e9954b86SRene Griessl 	#define	GMII_LED1_LINK_10	(1 << 4)
138e9954b86SRene Griessl 	#define	GMII_LED1_LINK_100	(1 << 5)
139e9954b86SRene Griessl 	#define	GMII_LED1_LINK_1000	(1 << 6)
140e9954b86SRene Griessl 	#define	GMII_LED2_LINK_10	(1 << 8)
141e9954b86SRene Griessl 	#define	GMII_LED2_LINK_100	(1 << 9)
142e9954b86SRene Griessl 	#define	GMII_LED2_LINK_1000	(1 << 10)
143e9954b86SRene Griessl 	#define	LED0_ACTIVE		(1 << 0)
144e9954b86SRene Griessl 	#define	LED0_LINK_10		(1 << 1)
145e9954b86SRene Griessl 	#define	LED0_LINK_100		(1 << 2)
146e9954b86SRene Griessl 	#define	LED0_LINK_1000		(1 << 3)
147e9954b86SRene Griessl 	#define	LED0_FD			(1 << 4)
148e9954b86SRene Griessl 	#define	LED0_USB3_MASK		0x001f
149e9954b86SRene Griessl 	#define	LED1_ACTIVE		(1 << 5)
150e9954b86SRene Griessl 	#define	LED1_LINK_10		(1 << 6)
151e9954b86SRene Griessl 	#define	LED1_LINK_100		(1 << 7)
152e9954b86SRene Griessl 	#define	LED1_LINK_1000		(1 << 8)
153e9954b86SRene Griessl 	#define	LED1_FD			(1 << 9)
154e9954b86SRene Griessl 	#define	LED1_USB3_MASK		0x03e0
155e9954b86SRene Griessl 	#define	LED2_ACTIVE		(1 << 10)
156e9954b86SRene Griessl 	#define	LED2_LINK_1000		(1 << 13)
157e9954b86SRene Griessl 	#define	LED2_LINK_100		(1 << 12)
158e9954b86SRene Griessl 	#define	LED2_LINK_10		(1 << 11)
159e9954b86SRene Griessl 	#define	LED2_FD			(1 << 14)
160e9954b86SRene Griessl 	#define	LED_VALID		(1 << 15)
161e9954b86SRene Griessl 	#define	LED2_USB3_MASK		0x7c00
162e9954b86SRene Griessl 
163e9954b86SRene Griessl #define GMII_PHYPAGE				0x1e
164e9954b86SRene Griessl #define GMII_PHY_PAGE_SELECT			0x1f
165e9954b86SRene Griessl 	#define GMII_PHY_PGSEL_EXT	0x0007
166e9954b86SRene Griessl 	#define GMII_PHY_PGSEL_PAGE0	0x0000
167e9954b86SRene Griessl 
168e9954b86SRene Griessl /* local defines */
169e9954b86SRene Griessl #define ASIX_BASE_NAME "axg"
170e9954b86SRene Griessl #define USB_CTRL_SET_TIMEOUT 5000
171e9954b86SRene Griessl #define USB_CTRL_GET_TIMEOUT 5000
172e9954b86SRene Griessl #define USB_BULK_SEND_TIMEOUT 5000
173e9954b86SRene Griessl #define USB_BULK_RECV_TIMEOUT 5000
174e9954b86SRene Griessl 
175e9954b86SRene Griessl #define AX_RX_URB_SIZE 1024 * 0x12
176e9954b86SRene Griessl #define BLK_FRAME_SIZE 0x200
177e9954b86SRene Griessl #define PHY_CONNECT_TIMEOUT 5000
178e9954b86SRene Griessl 
179e9954b86SRene Griessl #define TIMEOUT_RESOLUTION 50	/* ms */
180e9954b86SRene Griessl 
181e9954b86SRene Griessl #define FLAG_NONE			0
182e9954b86SRene Griessl #define FLAG_TYPE_AX88179	(1U << 0)
183e9954b86SRene Griessl #define FLAG_TYPE_AX88178a	(1U << 1)
184e9954b86SRene Griessl #define FLAG_TYPE_DLINK_DUB1312	(1U << 2)
185e9954b86SRene Griessl #define FLAG_TYPE_SITECOM	(1U << 3)
186e9954b86SRene Griessl #define FLAG_TYPE_SAMSUNG	(1U << 4)
187e9954b86SRene Griessl #define FLAG_TYPE_LENOVO	(1U << 5)
188652b2694SAlban Bedel #define FLAG_TYPE_GX3		(1U << 6)
189e9954b86SRene Griessl 
190e9954b86SRene Griessl /* local vars */
191e9954b86SRene Griessl static const struct {
192e9954b86SRene Griessl 	unsigned char ctrl, timer_l, timer_h, size, ifg;
193e9954b86SRene Griessl } AX88179_BULKIN_SIZE[] =	{
194e9954b86SRene Griessl 	{7, 0x4f, 0,	0x02, 0xff},
195e9954b86SRene Griessl 	{7, 0x20, 3,	0x03, 0xff},
196e9954b86SRene Griessl 	{7, 0xae, 7,	0x04, 0xff},
197e9954b86SRene Griessl 	{7, 0xcc, 0x4c, 0x04, 8},
198e9954b86SRene Griessl };
199e9954b86SRene Griessl 
200e9954b86SRene Griessl static int curr_eth_dev; /* index for name of next device detected */
201e9954b86SRene Griessl 
202e9954b86SRene Griessl /* driver private */
203e9954b86SRene Griessl struct asix_private {
204e9954b86SRene Griessl 	int flags;
205e9954b86SRene Griessl 	int rx_urb_size;
206e9954b86SRene Griessl 	int maxpacketsize;
207e9954b86SRene Griessl };
208e9954b86SRene Griessl 
209e9954b86SRene Griessl /*
210e9954b86SRene Griessl  * Asix infrastructure commands
211e9954b86SRene Griessl  */
212e9954b86SRene Griessl static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
213e9954b86SRene Griessl 			     u16 size, void *data)
214e9954b86SRene Griessl {
215e9954b86SRene Griessl 	int len;
216e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
217e9954b86SRene Griessl 
218e9954b86SRene Griessl 	debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
219e9954b86SRene Griessl 	      cmd, value, index, size);
220e9954b86SRene Griessl 
221e9954b86SRene Griessl 	memcpy(buf, data, size);
222e9954b86SRene Griessl 
223e9954b86SRene Griessl 	len = usb_control_msg(
224e9954b86SRene Griessl 		dev->pusb_dev,
225e9954b86SRene Griessl 		usb_sndctrlpipe(dev->pusb_dev, 0),
226e9954b86SRene Griessl 		cmd,
227e9954b86SRene Griessl 		USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
228e9954b86SRene Griessl 		value,
229e9954b86SRene Griessl 		index,
230e9954b86SRene Griessl 		buf,
231e9954b86SRene Griessl 		size,
232e9954b86SRene Griessl 		USB_CTRL_SET_TIMEOUT);
233e9954b86SRene Griessl 
234e9954b86SRene Griessl 	return len == size ? 0 : ECOMM;
235e9954b86SRene Griessl }
236e9954b86SRene Griessl 
237e9954b86SRene Griessl static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
238e9954b86SRene Griessl 			    u16 size, void *data)
239e9954b86SRene Griessl {
240e9954b86SRene Griessl 	int len;
241e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
242e9954b86SRene Griessl 
243e9954b86SRene Griessl 	debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
244e9954b86SRene Griessl 	      cmd, value, index, size);
245e9954b86SRene Griessl 
246e9954b86SRene Griessl 	len = usb_control_msg(
247e9954b86SRene Griessl 		dev->pusb_dev,
248e9954b86SRene Griessl 		usb_rcvctrlpipe(dev->pusb_dev, 0),
249e9954b86SRene Griessl 		cmd,
250e9954b86SRene Griessl 		USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
251e9954b86SRene Griessl 		value,
252e9954b86SRene Griessl 		index,
253e9954b86SRene Griessl 		buf,
254e9954b86SRene Griessl 		size,
255e9954b86SRene Griessl 		USB_CTRL_GET_TIMEOUT);
256e9954b86SRene Griessl 
257e9954b86SRene Griessl 	memcpy(data, buf, size);
258e9954b86SRene Griessl 
259e9954b86SRene Griessl 	return len == size ? 0 : ECOMM;
260e9954b86SRene Griessl }
261e9954b86SRene Griessl 
262*620452e7SAlban Bedel static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
263e9954b86SRene Griessl {
264*620452e7SAlban Bedel 	int ret;
265e9954b86SRene Griessl 
266*620452e7SAlban Bedel 	ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
267*620452e7SAlban Bedel 	if (ret < 0)
268*620452e7SAlban Bedel 		debug("Failed to read MAC address: %02x\n", ret);
269e9954b86SRene Griessl 
270*620452e7SAlban Bedel 	return ret;
271e9954b86SRene Griessl }
272e9954b86SRene Griessl 
273*620452e7SAlban Bedel static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
27411933975SRene Griessl {
27511933975SRene Griessl 	int ret;
27611933975SRene Griessl 
27711933975SRene Griessl 	ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
278*620452e7SAlban Bedel 				 ETH_ALEN, enetaddr);
27911933975SRene Griessl 	if (ret < 0)
28011933975SRene Griessl 		debug("Failed to set MAC address: %02x\n", ret);
28111933975SRene Griessl 
28211933975SRene Griessl 	return ret;
28311933975SRene Griessl }
28411933975SRene Griessl 
285*620452e7SAlban Bedel static int asix_basic_reset(struct ueth_data *dev,
286*620452e7SAlban Bedel 			struct asix_private *dev_priv)
287e9954b86SRene Griessl {
288e9954b86SRene Griessl 	u8 buf[5];
289e9954b86SRene Griessl 	u16 *tmp16;
290e9954b86SRene Griessl 	u8 *tmp;
291e9954b86SRene Griessl 
292e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
293e9954b86SRene Griessl 	tmp = (u8 *)buf;
294e9954b86SRene Griessl 
295e9954b86SRene Griessl 	/* Power up ethernet PHY */
296e9954b86SRene Griessl 	*tmp16 = 0;
297e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
298e9954b86SRene Griessl 
299e9954b86SRene Griessl 	*tmp16 = AX_PHYPWR_RSTCTL_IPRL;
300e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
301e9954b86SRene Griessl 	mdelay(200);
302e9954b86SRene Griessl 
303e9954b86SRene Griessl 	*tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
304e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
305e9954b86SRene Griessl 	mdelay(200);
306e9954b86SRene Griessl 
307e9954b86SRene Griessl 	/* RX bulk configuration */
308e9954b86SRene Griessl 	memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
309e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
310e9954b86SRene Griessl 
311e9954b86SRene Griessl 	dev_priv->rx_urb_size = 128 * 20;
312e9954b86SRene Griessl 
313e9954b86SRene Griessl 	/* Water Level configuration */
314e9954b86SRene Griessl 	*tmp = 0x34;
315e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
316e9954b86SRene Griessl 
317e9954b86SRene Griessl 	*tmp = 0x52;
318e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
319e9954b86SRene Griessl 
320e9954b86SRene Griessl 	/* Enable checksum offload */
321e9954b86SRene Griessl 	*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
322e9954b86SRene Griessl 	       AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
323e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
324e9954b86SRene Griessl 
325e9954b86SRene Griessl 	*tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
326e9954b86SRene Griessl 	       AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
327e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
328e9954b86SRene Griessl 
329e9954b86SRene Griessl 	/* Configure RX control register => start operation */
330e9954b86SRene Griessl 	*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
331e9954b86SRene Griessl 		 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
332e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
333e9954b86SRene Griessl 
334e9954b86SRene Griessl 	*tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
335e9954b86SRene Griessl 	       AX_MONITOR_MODE_RWMP;
336e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
337e9954b86SRene Griessl 
338e9954b86SRene Griessl 	/* Configure default medium type => giga */
339e9954b86SRene Griessl 	*tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
340e9954b86SRene Griessl 		 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
341e9954b86SRene Griessl 		 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
342e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
343e9954b86SRene Griessl 
344e9954b86SRene Griessl 	u16 adv = 0;
345e9954b86SRene Griessl 	adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
346e9954b86SRene Griessl 	      ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
347e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
348e9954b86SRene Griessl 
349e9954b86SRene Griessl 	adv = ADVERTISE_1000FULL;
350e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
351e9954b86SRene Griessl 
352e9954b86SRene Griessl 	return 0;
353e9954b86SRene Griessl }
354e9954b86SRene Griessl 
355e9954b86SRene Griessl static int asix_wait_link(struct ueth_data *dev)
356e9954b86SRene Griessl {
357e9954b86SRene Griessl 	int timeout = 0;
358e9954b86SRene Griessl 	int link_detected;
359e9954b86SRene Griessl 	u8 buf[2];
360e9954b86SRene Griessl 	u16 *tmp16;
361e9954b86SRene Griessl 
362e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
363e9954b86SRene Griessl 
364e9954b86SRene Griessl 	do {
365e9954b86SRene Griessl 		asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
366e9954b86SRene Griessl 			      MII_BMSR, 2, buf);
367e9954b86SRene Griessl 		link_detected = *tmp16 & BMSR_LSTATUS;
368e9954b86SRene Griessl 		if (!link_detected) {
369e9954b86SRene Griessl 			if (timeout == 0)
370e9954b86SRene Griessl 				printf("Waiting for Ethernet connection... ");
371e9954b86SRene Griessl 			mdelay(TIMEOUT_RESOLUTION);
372e9954b86SRene Griessl 			timeout += TIMEOUT_RESOLUTION;
373e9954b86SRene Griessl 		}
374e9954b86SRene Griessl 	} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
375e9954b86SRene Griessl 
376e9954b86SRene Griessl 	if (link_detected) {
377e9954b86SRene Griessl 		if (timeout > 0)
378e9954b86SRene Griessl 			printf("done.\n");
379e9954b86SRene Griessl 		return 0;
380e9954b86SRene Griessl 	} else {
381e9954b86SRene Griessl 		printf("unable to connect.\n");
382e9954b86SRene Griessl 		return -ENETUNREACH;
383e9954b86SRene Griessl 	}
384e9954b86SRene Griessl }
385e9954b86SRene Griessl 
386*620452e7SAlban Bedel static int asix_init_common(struct ueth_data *dev,
387*620452e7SAlban Bedel 			struct asix_private *dev_priv)
388e9954b86SRene Griessl {
389e9954b86SRene Griessl 	u8 buf[2], tmp[5], link_sts;
390e9954b86SRene Griessl 	u16 *tmp16, mode;
391e9954b86SRene Griessl 
392e9954b86SRene Griessl 
393e9954b86SRene Griessl 	tmp16 = (u16 *)buf;
394e9954b86SRene Griessl 
395e9954b86SRene Griessl 	debug("** %s()\n", __func__);
396e9954b86SRene Griessl 
397e9954b86SRene Griessl 	/* Configure RX control register => start operation */
398e9954b86SRene Griessl 	*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
399e9954b86SRene Griessl 		 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
400e9954b86SRene Griessl 	if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
401e9954b86SRene Griessl 		goto out_err;
402e9954b86SRene Griessl 
403e9954b86SRene Griessl 	if (asix_wait_link(dev) != 0) {
404e9954b86SRene Griessl 		/*reset device and try again*/
405e9954b86SRene Griessl 		printf("Reset Ethernet Device\n");
406*620452e7SAlban Bedel 		asix_basic_reset(dev, dev_priv);
407e9954b86SRene Griessl 		if (asix_wait_link(dev) != 0)
408e9954b86SRene Griessl 			goto out_err;
409e9954b86SRene Griessl 	}
410e9954b86SRene Griessl 
411e9954b86SRene Griessl 	/* Configure link */
412e9954b86SRene Griessl 	mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
413e9954b86SRene Griessl 	       AX_MEDIUM_RXFLOW_CTRLEN;
414e9954b86SRene Griessl 
415e9954b86SRene Griessl 	asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
416e9954b86SRene Griessl 		      1, 1, &link_sts);
417e9954b86SRene Griessl 
418e9954b86SRene Griessl 	asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
419e9954b86SRene Griessl 		      GMII_PHY_PHYSR, 2, tmp16);
420e9954b86SRene Griessl 
421e9954b86SRene Griessl 	if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
422e9954b86SRene Griessl 		return 0;
423e9954b86SRene Griessl 	} else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
424e9954b86SRene Griessl 		mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
425e9954b86SRene Griessl 			AX_MEDIUM_JUMBO_EN;
426e9954b86SRene Griessl 
427e9954b86SRene Griessl 		if (link_sts & AX_USB_SS)
428e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
429e9954b86SRene Griessl 		else if (link_sts & AX_USB_HS)
430e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
431e9954b86SRene Griessl 		else
432e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
433e9954b86SRene Griessl 	} else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
434e9954b86SRene Griessl 		mode |= AX_MEDIUM_PS;
435e9954b86SRene Griessl 
436e9954b86SRene Griessl 		if (link_sts & (AX_USB_SS | AX_USB_HS))
437e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
438e9954b86SRene Griessl 		else
439e9954b86SRene Griessl 			memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
440e9954b86SRene Griessl 	} else {
441e9954b86SRene Griessl 		memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
442e9954b86SRene Griessl 	}
443e9954b86SRene Griessl 
444e9954b86SRene Griessl 	/* RX bulk configuration */
445e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
446e9954b86SRene Griessl 
447e9954b86SRene Griessl 	dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
448e9954b86SRene Griessl 	if (*tmp16 & GMII_PHY_PHYSR_FULL)
449e9954b86SRene Griessl 		mode |= AX_MEDIUM_FULL_DUPLEX;
450e9954b86SRene Griessl 	asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
451e9954b86SRene Griessl 		       2, 2, &mode);
452e9954b86SRene Griessl 
453e9954b86SRene Griessl 	return 0;
454e9954b86SRene Griessl out_err:
455e9954b86SRene Griessl 	return -1;
456e9954b86SRene Griessl }
457e9954b86SRene Griessl 
458*620452e7SAlban Bedel static int asix_send_common(struct ueth_data *dev,
459*620452e7SAlban Bedel 			struct asix_private *dev_priv,
460*620452e7SAlban Bedel 			void *packet, int length)
461e9954b86SRene Griessl {
462e9954b86SRene Griessl 	int err;
463e9954b86SRene Griessl 	u32 packet_len, tx_hdr2;
464e9954b86SRene Griessl 	int actual_len, framesize;
465e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
466e9954b86SRene Griessl 				 PKTSIZE + (2 * sizeof(packet_len)));
467e9954b86SRene Griessl 
468e9954b86SRene Griessl 	debug("** %s(), len %d\n", __func__, length);
469e9954b86SRene Griessl 
470e9954b86SRene Griessl 	packet_len = length;
471e9954b86SRene Griessl 	cpu_to_le32s(&packet_len);
472e9954b86SRene Griessl 
473e9954b86SRene Griessl 	memcpy(msg, &packet_len, sizeof(packet_len));
474e9954b86SRene Griessl 	framesize = dev_priv->maxpacketsize;
475e9954b86SRene Griessl 	tx_hdr2 = 0;
476e9954b86SRene Griessl 	if (((length + 8) % framesize) == 0)
477e9954b86SRene Griessl 		tx_hdr2 |= 0x80008000;	/* Enable padding */
478e9954b86SRene Griessl 
479e9954b86SRene Griessl 	cpu_to_le32s(&tx_hdr2);
480e9954b86SRene Griessl 
481e9954b86SRene Griessl 	memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
482e9954b86SRene Griessl 
483e9954b86SRene Griessl 	memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
484e9954b86SRene Griessl 	       (void *)packet, length);
485e9954b86SRene Griessl 
486e9954b86SRene Griessl 	err = usb_bulk_msg(dev->pusb_dev,
487e9954b86SRene Griessl 				usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
488e9954b86SRene Griessl 				(void *)msg,
489e9954b86SRene Griessl 				length + sizeof(packet_len) + sizeof(tx_hdr2),
490e9954b86SRene Griessl 				&actual_len,
491e9954b86SRene Griessl 				USB_BULK_SEND_TIMEOUT);
49264160a54SMateusz Kulikowski 	debug("Tx: len = %zu, actual = %u, err = %d\n",
493e9954b86SRene Griessl 	      length + sizeof(packet_len), actual_len, err);
494e9954b86SRene Griessl 
495e9954b86SRene Griessl 	return err;
496e9954b86SRene Griessl }
497e9954b86SRene Griessl 
498*620452e7SAlban Bedel /*
499*620452e7SAlban Bedel  * Asix callbacks
500*620452e7SAlban Bedel  */
501*620452e7SAlban Bedel static int asix_init(struct eth_device *eth, bd_t *bd)
502*620452e7SAlban Bedel {
503*620452e7SAlban Bedel 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
504*620452e7SAlban Bedel 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
505*620452e7SAlban Bedel 
506*620452e7SAlban Bedel 	return asix_init_common(dev, dev_priv);
507*620452e7SAlban Bedel }
508*620452e7SAlban Bedel 
509*620452e7SAlban Bedel static int asix_write_hwaddr(struct eth_device *eth)
510*620452e7SAlban Bedel {
511*620452e7SAlban Bedel 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
512*620452e7SAlban Bedel 
513*620452e7SAlban Bedel 	return asix_write_mac(dev, eth->enetaddr);
514*620452e7SAlban Bedel }
515*620452e7SAlban Bedel 
516*620452e7SAlban Bedel static int asix_send(struct eth_device *eth, void *packet, int length)
517*620452e7SAlban Bedel {
518*620452e7SAlban Bedel 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
519*620452e7SAlban Bedel 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
520*620452e7SAlban Bedel 
521*620452e7SAlban Bedel 	return asix_send_common(dev, dev_priv, packet, length);
522*620452e7SAlban Bedel }
523*620452e7SAlban Bedel 
524e9954b86SRene Griessl static int asix_recv(struct eth_device *eth)
525e9954b86SRene Griessl {
526e9954b86SRene Griessl 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
527e9954b86SRene Griessl 	struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
528e9954b86SRene Griessl 
529e9954b86SRene Griessl 	u16 frame_pos;
530e9954b86SRene Griessl 	int err;
531e9954b86SRene Griessl 	int actual_len;
532e9954b86SRene Griessl 
533e9954b86SRene Griessl 	int pkt_cnt;
534e9954b86SRene Griessl 	u32 rx_hdr;
535e9954b86SRene Griessl 	u16 hdr_off;
536e9954b86SRene Griessl 	u32 *pkt_hdr;
537e9954b86SRene Griessl 	ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
538e9954b86SRene Griessl 
539e9954b86SRene Griessl 	actual_len = -1;
540e9954b86SRene Griessl 
541e9954b86SRene Griessl 	debug("** %s()\n", __func__);
542e9954b86SRene Griessl 
543e9954b86SRene Griessl 	err = usb_bulk_msg(dev->pusb_dev,
544e9954b86SRene Griessl 				usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
545e9954b86SRene Griessl 				(void *)recv_buf,
546e9954b86SRene Griessl 				dev_priv->rx_urb_size,
547e9954b86SRene Griessl 				&actual_len,
548e9954b86SRene Griessl 				USB_BULK_RECV_TIMEOUT);
549e9954b86SRene Griessl 	debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
550e9954b86SRene Griessl 	      actual_len, err);
551e9954b86SRene Griessl 
552e9954b86SRene Griessl 	if (err != 0) {
553e9954b86SRene Griessl 		debug("Rx: failed to receive\n");
554e9954b86SRene Griessl 		return -ECOMM;
555e9954b86SRene Griessl 	}
556e9954b86SRene Griessl 	if (actual_len > dev_priv->rx_urb_size) {
557e9954b86SRene Griessl 		debug("Rx: received too many bytes %d\n", actual_len);
558e9954b86SRene Griessl 		return -EMSGSIZE;
559e9954b86SRene Griessl 	}
560e9954b86SRene Griessl 
561e9954b86SRene Griessl 
562e9954b86SRene Griessl 	rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
56350f5bb25SAlban Bedel 	le32_to_cpus(&rx_hdr);
564e9954b86SRene Griessl 
565e9954b86SRene Griessl 	pkt_cnt = (u16)rx_hdr;
566e9954b86SRene Griessl 	hdr_off = (u16)(rx_hdr >> 16);
567e9954b86SRene Griessl 	pkt_hdr = (u32 *)(recv_buf + hdr_off);
568e9954b86SRene Griessl 
569e9954b86SRene Griessl 
570e9954b86SRene Griessl 	frame_pos = 0;
571e9954b86SRene Griessl 
572e9954b86SRene Griessl 	while (pkt_cnt--) {
573e9954b86SRene Griessl 		u16 pkt_len;
574e9954b86SRene Griessl 
575e9954b86SRene Griessl 		le32_to_cpus(pkt_hdr);
576e9954b86SRene Griessl 		pkt_len = (*pkt_hdr >> 16) & 0x1fff;
577e9954b86SRene Griessl 
578e9954b86SRene Griessl 		frame_pos += 2;
579e9954b86SRene Griessl 
5801fd92db8SJoe Hershberger 		net_process_received_packet(recv_buf + frame_pos, pkt_len);
581e9954b86SRene Griessl 
582e9954b86SRene Griessl 		pkt_hdr++;
583e9954b86SRene Griessl 		frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
584e9954b86SRene Griessl 
585e9954b86SRene Griessl 		if (pkt_cnt == 0)
586e9954b86SRene Griessl 			return 0;
587e9954b86SRene Griessl 	}
588e9954b86SRene Griessl 	return err;
589e9954b86SRene Griessl }
590e9954b86SRene Griessl 
591e9954b86SRene Griessl static void asix_halt(struct eth_device *eth)
592e9954b86SRene Griessl {
593e9954b86SRene Griessl 	debug("** %s()\n", __func__);
594e9954b86SRene Griessl }
595e9954b86SRene Griessl 
596e9954b86SRene Griessl /*
597e9954b86SRene Griessl  * Asix probing functions
598e9954b86SRene Griessl  */
599e9954b86SRene Griessl void ax88179_eth_before_probe(void)
600e9954b86SRene Griessl {
601e9954b86SRene Griessl 	curr_eth_dev = 0;
602e9954b86SRene Griessl }
603e9954b86SRene Griessl 
604e9954b86SRene Griessl struct asix_dongle {
605e9954b86SRene Griessl 	unsigned short vendor;
606e9954b86SRene Griessl 	unsigned short product;
607e9954b86SRene Griessl 	int flags;
608e9954b86SRene Griessl };
609e9954b86SRene Griessl 
610e9954b86SRene Griessl static const struct asix_dongle asix_dongles[] = {
611e9954b86SRene Griessl 	{ 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
612e9954b86SRene Griessl 	{ 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
613e9954b86SRene Griessl 	{ 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
614e9954b86SRene Griessl 	{ 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
615e9954b86SRene Griessl 	{ 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
616e9954b86SRene Griessl 	{ 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
617652b2694SAlban Bedel 	{ 0x04b4, 0x3610, FLAG_TYPE_GX3 },
618e9954b86SRene Griessl 	{ 0x0000, 0x0000, FLAG_NONE }	/* END - Do not remove */
619e9954b86SRene Griessl };
620e9954b86SRene Griessl 
621e9954b86SRene Griessl /* Probe to see if a new device is actually an asix device */
622e9954b86SRene Griessl int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
623e9954b86SRene Griessl 		      struct ueth_data *ss)
624e9954b86SRene Griessl {
625e9954b86SRene Griessl 	struct usb_interface *iface;
626e9954b86SRene Griessl 	struct usb_interface_descriptor *iface_desc;
627e9954b86SRene Griessl 	struct asix_private *dev_priv;
628e9954b86SRene Griessl 	int ep_in_found = 0, ep_out_found = 0;
629e9954b86SRene Griessl 	int i;
630e9954b86SRene Griessl 
631e9954b86SRene Griessl 	/* let's examine the device now */
632e9954b86SRene Griessl 	iface = &dev->config.if_desc[ifnum];
633e9954b86SRene Griessl 	iface_desc = &dev->config.if_desc[ifnum].desc;
634e9954b86SRene Griessl 
635e9954b86SRene Griessl 	for (i = 0; asix_dongles[i].vendor != 0; i++) {
636e9954b86SRene Griessl 		if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
637e9954b86SRene Griessl 		    dev->descriptor.idProduct == asix_dongles[i].product)
638e9954b86SRene Griessl 			/* Found a supported dongle */
639e9954b86SRene Griessl 			break;
640e9954b86SRene Griessl 	}
641e9954b86SRene Griessl 
642e9954b86SRene Griessl 	if (asix_dongles[i].vendor == 0)
643e9954b86SRene Griessl 		return 0;
644e9954b86SRene Griessl 
645e9954b86SRene Griessl 	memset(ss, 0, sizeof(struct ueth_data));
646e9954b86SRene Griessl 
647e9954b86SRene Griessl 	/* At this point, we know we've got a live one */
648e9954b86SRene Griessl 	debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
649e9954b86SRene Griessl 	      dev->descriptor.idVendor, dev->descriptor.idProduct);
650e9954b86SRene Griessl 
651e9954b86SRene Griessl 	/* Initialize the ueth_data structure with some useful info */
652e9954b86SRene Griessl 	ss->ifnum = ifnum;
653e9954b86SRene Griessl 	ss->pusb_dev = dev;
654e9954b86SRene Griessl 	ss->subclass = iface_desc->bInterfaceSubClass;
655e9954b86SRene Griessl 	ss->protocol = iface_desc->bInterfaceProtocol;
656e9954b86SRene Griessl 
657e9954b86SRene Griessl 	/* alloc driver private */
658e9954b86SRene Griessl 	ss->dev_priv = calloc(1, sizeof(struct asix_private));
659e9954b86SRene Griessl 	if (!ss->dev_priv)
660e9954b86SRene Griessl 		return 0;
661e9954b86SRene Griessl 	dev_priv = ss->dev_priv;
662e9954b86SRene Griessl 	dev_priv->flags = asix_dongles[i].flags;
663e9954b86SRene Griessl 
664e9954b86SRene Griessl 	/*
665e9954b86SRene Griessl 	 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
666e9954b86SRene Griessl 	 * int. We will ignore any others.
667e9954b86SRene Griessl 	 */
668e9954b86SRene Griessl 	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
669e9954b86SRene Griessl 		/* is it an interrupt endpoint? */
670e9954b86SRene Griessl 		if ((iface->ep_desc[i].bmAttributes &
671e9954b86SRene Griessl 		    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
672e9954b86SRene Griessl 			ss->ep_int = iface->ep_desc[i].bEndpointAddress &
673e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
674e9954b86SRene Griessl 			ss->irqinterval = iface->ep_desc[i].bInterval;
675e9954b86SRene Griessl 			continue;
676e9954b86SRene Griessl 		}
677e9954b86SRene Griessl 
678e9954b86SRene Griessl 		/* is it an BULK endpoint? */
679e9954b86SRene Griessl 		if (!((iface->ep_desc[i].bmAttributes &
680e9954b86SRene Griessl 		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
681e9954b86SRene Griessl 			continue;
682e9954b86SRene Griessl 
683e9954b86SRene Griessl 		u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
684e9954b86SRene Griessl 		if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
685e9954b86SRene Griessl 			ss->ep_in = ep_addr &
686e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
687e9954b86SRene Griessl 			ep_in_found = 1;
688e9954b86SRene Griessl 		}
689e9954b86SRene Griessl 		if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
690e9954b86SRene Griessl 			ss->ep_out = ep_addr &
691e9954b86SRene Griessl 				USB_ENDPOINT_NUMBER_MASK;
692e9954b86SRene Griessl 			dev_priv->maxpacketsize =
693e9954b86SRene Griessl 				dev->epmaxpacketout[AX_ENDPOINT_OUT];
694e9954b86SRene Griessl 			ep_out_found = 1;
695e9954b86SRene Griessl 		}
696e9954b86SRene Griessl 	}
697e9954b86SRene Griessl 	debug("Endpoints In %d Out %d Int %d\n",
698e9954b86SRene Griessl 	      ss->ep_in, ss->ep_out, ss->ep_int);
699e9954b86SRene Griessl 
700e9954b86SRene Griessl 	/* Do some basic sanity checks, and bail if we find a problem */
701e9954b86SRene Griessl 	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
702e9954b86SRene Griessl 	    !ss->ep_in || !ss->ep_out || !ss->ep_int) {
703e9954b86SRene Griessl 		debug("Problems with device\n");
704e9954b86SRene Griessl 		return 0;
705e9954b86SRene Griessl 	}
706e9954b86SRene Griessl 	dev->privptr = (void *)ss;
707e9954b86SRene Griessl 	return 1;
708e9954b86SRene Griessl }
709e9954b86SRene Griessl 
710e9954b86SRene Griessl int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
711e9954b86SRene Griessl 				struct eth_device *eth)
712e9954b86SRene Griessl {
713*620452e7SAlban Bedel 	struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
714*620452e7SAlban Bedel 
715e9954b86SRene Griessl 	if (!eth) {
716e9954b86SRene Griessl 		debug("%s: missing parameter.\n", __func__);
717e9954b86SRene Griessl 		return 0;
718e9954b86SRene Griessl 	}
719e9954b86SRene Griessl 	sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
720e9954b86SRene Griessl 	eth->init = asix_init;
721e9954b86SRene Griessl 	eth->send = asix_send;
722e9954b86SRene Griessl 	eth->recv = asix_recv;
723e9954b86SRene Griessl 	eth->halt = asix_halt;
724*620452e7SAlban Bedel 	eth->write_hwaddr = asix_write_hwaddr;
725e9954b86SRene Griessl 	eth->priv = ss;
726e9954b86SRene Griessl 
727*620452e7SAlban Bedel 	if (asix_basic_reset(ss, dev_priv))
728e9954b86SRene Griessl 		return 0;
729e9954b86SRene Griessl 
730e9954b86SRene Griessl 	/* Get the MAC address */
731*620452e7SAlban Bedel 	if (asix_read_mac(ss, eth->enetaddr))
732e9954b86SRene Griessl 		return 0;
733e9954b86SRene Griessl 	debug("MAC %pM\n", eth->enetaddr);
734e9954b86SRene Griessl 
735e9954b86SRene Griessl 	return 1;
736e9954b86SRene Griessl }
737