1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <linux/version.h> 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/interrupt.h> 25 #include <linux/ioport.h> 26 #include <linux/io.h> 27 #include <linux/list.h> 28 #include <linux/delay.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/of.h> 31 #include <linux/acpi.h> 32 33 #include <linux/usb/ch9.h> 34 #include <linux/usb/gadget.h> 35 #include <linux/usb/of.h> 36 #include <linux/usb/otg.h> 37 38 #include "platform_data.h" 39 #include "core.h" 40 #include "gadget.h" 41 #include "io.h" 42 43 #include "debug.h" 44 45 /* -------------------------------------------------------------------------- */ 46 47 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 48 { 49 u32 reg; 50 51 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 52 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 53 reg |= DWC3_GCTL_PRTCAPDIR(mode); 54 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 55 } 56 57 /** 58 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 59 * @dwc: pointer to our context structure 60 */ 61 static int dwc3_core_soft_reset(struct dwc3 *dwc) 62 { 63 u32 reg; 64 int ret; 65 66 /* Before Resetting PHY, put Core in Reset */ 67 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 68 reg |= DWC3_GCTL_CORESOFTRESET; 69 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 70 71 /* Assert USB3 PHY reset */ 72 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 73 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 74 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 75 76 /* Assert USB2 PHY reset */ 77 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 78 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 79 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 80 81 usb_phy_init(dwc->usb2_phy); 82 usb_phy_init(dwc->usb3_phy); 83 ret = phy_init(dwc->usb2_generic_phy); 84 if (ret < 0) 85 return ret; 86 87 ret = phy_init(dwc->usb3_generic_phy); 88 if (ret < 0) { 89 phy_exit(dwc->usb2_generic_phy); 90 return ret; 91 } 92 mdelay(100); 93 94 /* Clear USB3 PHY reset */ 95 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 96 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 97 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 98 99 /* Clear USB2 PHY reset */ 100 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 101 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 102 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 103 104 mdelay(100); 105 106 /* After PHYs are stable we can take Core out of reset state */ 107 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 108 reg &= ~DWC3_GCTL_CORESOFTRESET; 109 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 110 111 return 0; 112 } 113 114 /** 115 * dwc3_free_one_event_buffer - Frees one event buffer 116 * @dwc: Pointer to our controller context structure 117 * @evt: Pointer to event buffer to be freed 118 */ 119 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 120 struct dwc3_event_buffer *evt) 121 { 122 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); 123 } 124 125 /** 126 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 127 * @dwc: Pointer to our controller context structure 128 * @length: size of the event buffer 129 * 130 * Returns a pointer to the allocated event buffer structure on success 131 * otherwise ERR_PTR(errno). 132 */ 133 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 134 unsigned length) 135 { 136 struct dwc3_event_buffer *evt; 137 138 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 139 if (!evt) 140 return ERR_PTR(-ENOMEM); 141 142 evt->dwc = dwc; 143 evt->length = length; 144 evt->buf = dma_alloc_coherent(dwc->dev, length, 145 &evt->dma, GFP_KERNEL); 146 if (!evt->buf) 147 return ERR_PTR(-ENOMEM); 148 149 return evt; 150 } 151 152 /** 153 * dwc3_free_event_buffers - frees all allocated event buffers 154 * @dwc: Pointer to our controller context structure 155 */ 156 static void dwc3_free_event_buffers(struct dwc3 *dwc) 157 { 158 struct dwc3_event_buffer *evt; 159 int i; 160 161 for (i = 0; i < dwc->num_event_buffers; i++) { 162 evt = dwc->ev_buffs[i]; 163 if (evt) 164 dwc3_free_one_event_buffer(dwc, evt); 165 } 166 } 167 168 /** 169 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 170 * @dwc: pointer to our controller context structure 171 * @length: size of event buffer 172 * 173 * Returns 0 on success otherwise negative errno. In the error case, dwc 174 * may contain some buffers allocated but not all which were requested. 175 */ 176 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 177 { 178 int num; 179 int i; 180 181 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 182 dwc->num_event_buffers = num; 183 184 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, 185 GFP_KERNEL); 186 if (!dwc->ev_buffs) 187 return -ENOMEM; 188 189 for (i = 0; i < num; i++) { 190 struct dwc3_event_buffer *evt; 191 192 evt = dwc3_alloc_one_event_buffer(dwc, length); 193 if (IS_ERR(evt)) { 194 dev_err(dwc->dev, "can't allocate event buffer\n"); 195 return PTR_ERR(evt); 196 } 197 dwc->ev_buffs[i] = evt; 198 } 199 200 return 0; 201 } 202 203 /** 204 * dwc3_event_buffers_setup - setup our allocated event buffers 205 * @dwc: pointer to our controller context structure 206 * 207 * Returns 0 on success otherwise negative errno. 208 */ 209 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 210 { 211 struct dwc3_event_buffer *evt; 212 int n; 213 214 for (n = 0; n < dwc->num_event_buffers; n++) { 215 evt = dwc->ev_buffs[n]; 216 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 217 evt->buf, (unsigned long long) evt->dma, 218 evt->length); 219 220 evt->lpos = 0; 221 222 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 223 lower_32_bits(evt->dma)); 224 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 225 upper_32_bits(evt->dma)); 226 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 227 DWC3_GEVNTSIZ_SIZE(evt->length)); 228 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 229 } 230 231 return 0; 232 } 233 234 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 235 { 236 struct dwc3_event_buffer *evt; 237 int n; 238 239 for (n = 0; n < dwc->num_event_buffers; n++) { 240 evt = dwc->ev_buffs[n]; 241 242 evt->lpos = 0; 243 244 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 245 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 246 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 247 | DWC3_GEVNTSIZ_SIZE(0)); 248 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 249 } 250 } 251 252 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 253 { 254 if (!dwc->has_hibernation) 255 return 0; 256 257 if (!dwc->nr_scratch) 258 return 0; 259 260 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 261 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 262 if (!dwc->scratchbuf) 263 return -ENOMEM; 264 265 return 0; 266 } 267 268 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 269 { 270 dma_addr_t scratch_addr; 271 u32 param; 272 int ret; 273 274 if (!dwc->has_hibernation) 275 return 0; 276 277 if (!dwc->nr_scratch) 278 return 0; 279 280 /* should never fall here */ 281 if (!WARN_ON(dwc->scratchbuf)) 282 return 0; 283 284 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, 285 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 286 DMA_BIDIRECTIONAL); 287 if (dma_mapping_error(dwc->dev, scratch_addr)) { 288 dev_err(dwc->dev, "failed to map scratch buffer\n"); 289 ret = -EFAULT; 290 goto err0; 291 } 292 293 dwc->scratch_addr = scratch_addr; 294 295 param = lower_32_bits(scratch_addr); 296 297 ret = dwc3_send_gadget_generic_command(dwc, 298 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 299 if (ret < 0) 300 goto err1; 301 302 param = upper_32_bits(scratch_addr); 303 304 ret = dwc3_send_gadget_generic_command(dwc, 305 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 306 if (ret < 0) 307 goto err1; 308 309 return 0; 310 311 err1: 312 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 313 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 314 315 err0: 316 return ret; 317 } 318 319 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 320 { 321 if (!dwc->has_hibernation) 322 return; 323 324 if (!dwc->nr_scratch) 325 return; 326 327 /* should never fall here */ 328 if (!WARN_ON(dwc->scratchbuf)) 329 return; 330 331 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 332 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 333 kfree(dwc->scratchbuf); 334 } 335 336 static void dwc3_core_num_eps(struct dwc3 *dwc) 337 { 338 struct dwc3_hwparams *parms = &dwc->hwparams; 339 340 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 341 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 342 343 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 344 dwc->num_in_eps, dwc->num_out_eps); 345 } 346 347 static void dwc3_cache_hwparams(struct dwc3 *dwc) 348 { 349 struct dwc3_hwparams *parms = &dwc->hwparams; 350 351 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 352 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 353 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 354 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 355 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 356 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 357 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 358 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 359 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 360 } 361 362 /** 363 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 364 * @dwc: Pointer to our controller context structure 365 */ 366 static void dwc3_phy_setup(struct dwc3 *dwc) 367 { 368 u32 reg; 369 370 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 371 372 /* 373 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 374 * to '0' during coreConsultant configuration. So default value 375 * will be '0' when the core is reset. Application needs to set it 376 * to '1' after the core initialization is completed. 377 */ 378 if (dwc->revision > DWC3_REVISION_194A) 379 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 380 381 if (dwc->u2ss_inp3_quirk) 382 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 383 384 if (dwc->req_p1p2p3_quirk) 385 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 386 387 if (dwc->del_p1p2p3_quirk) 388 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 389 390 if (dwc->del_phy_power_chg_quirk) 391 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 392 393 if (dwc->lfps_filter_quirk) 394 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 395 396 if (dwc->rx_detect_poll_quirk) 397 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 398 399 if (dwc->tx_de_emphasis_quirk) 400 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 401 402 if (dwc->dis_u3_susphy_quirk) 403 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 404 405 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 406 407 mdelay(100); 408 409 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 410 411 /* 412 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 413 * '0' during coreConsultant configuration. So default value will 414 * be '0' when the core is reset. Application needs to set it to 415 * '1' after the core initialization is completed. 416 */ 417 if (dwc->revision > DWC3_REVISION_194A) 418 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 419 420 if (dwc->dis_u2_susphy_quirk) 421 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 422 423 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 424 425 mdelay(100); 426 } 427 428 /** 429 * dwc3_core_init - Low-level initialization of DWC3 Core 430 * @dwc: Pointer to our controller context structure 431 * 432 * Returns 0 on success otherwise negative errno. 433 */ 434 static int dwc3_core_init(struct dwc3 *dwc) 435 { 436 unsigned long timeout; 437 u32 hwparams4 = dwc->hwparams.hwparams4; 438 u32 reg; 439 int ret; 440 441 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 442 /* This should read as U3 followed by revision number */ 443 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 444 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 445 ret = -ENODEV; 446 goto err0; 447 } 448 dwc->revision = reg; 449 450 /* 451 * Write Linux Version Code to our GUID register so it's easy to figure 452 * out which kernel version a bug was found. 453 */ 454 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 455 456 /* Handle USB2.0-only core configuration */ 457 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 458 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 459 if (dwc->maximum_speed == USB_SPEED_SUPER) 460 dwc->maximum_speed = USB_SPEED_HIGH; 461 } 462 463 /* issue device SoftReset too */ 464 timeout = jiffies + msecs_to_jiffies(500); 465 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 466 do { 467 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 468 if (!(reg & DWC3_DCTL_CSFTRST)) 469 break; 470 471 if (time_after(jiffies, timeout)) { 472 dev_err(dwc->dev, "Reset Timed Out\n"); 473 ret = -ETIMEDOUT; 474 goto err0; 475 } 476 477 cpu_relax(); 478 } while (true); 479 480 ret = dwc3_core_soft_reset(dwc); 481 if (ret) 482 goto err0; 483 484 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 485 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 486 487 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 488 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 489 /** 490 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 491 * issue which would cause xHCI compliance tests to fail. 492 * 493 * Because of that we cannot enable clock gating on such 494 * configurations. 495 * 496 * Refers to: 497 * 498 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 499 * SOF/ITP Mode Used 500 */ 501 if ((dwc->dr_mode == USB_DR_MODE_HOST || 502 dwc->dr_mode == USB_DR_MODE_OTG) && 503 (dwc->revision >= DWC3_REVISION_210A && 504 dwc->revision <= DWC3_REVISION_250A)) 505 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 506 else 507 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 508 break; 509 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 510 /* enable hibernation here */ 511 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 512 513 /* 514 * REVISIT Enabling this bit so that host-mode hibernation 515 * will work. Device-mode hibernation is not yet implemented. 516 */ 517 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 518 break; 519 default: 520 dev_dbg(dwc->dev, "No power optimization available\n"); 521 } 522 523 /* check if current dwc3 is on simulation board */ 524 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 525 dev_dbg(dwc->dev, "it is on FPGA board\n"); 526 dwc->is_fpga = true; 527 } 528 529 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 530 "disable_scramble cannot be used on non-FPGA builds\n"); 531 532 if (dwc->disable_scramble_quirk && dwc->is_fpga) 533 reg |= DWC3_GCTL_DISSCRAMBLE; 534 else 535 reg &= ~DWC3_GCTL_DISSCRAMBLE; 536 537 if (dwc->u2exit_lfps_quirk) 538 reg |= DWC3_GCTL_U2EXIT_LFPS; 539 540 /* 541 * WORKAROUND: DWC3 revisions <1.90a have a bug 542 * where the device can fail to connect at SuperSpeed 543 * and falls back to high-speed mode which causes 544 * the device to enter a Connect/Disconnect loop 545 */ 546 if (dwc->revision < DWC3_REVISION_190A) 547 reg |= DWC3_GCTL_U2RSTECN; 548 549 dwc3_core_num_eps(dwc); 550 551 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 552 553 dwc3_phy_setup(dwc); 554 555 ret = dwc3_alloc_scratch_buffers(dwc); 556 if (ret) 557 goto err1; 558 559 ret = dwc3_setup_scratch_buffers(dwc); 560 if (ret) 561 goto err2; 562 563 return 0; 564 565 err2: 566 dwc3_free_scratch_buffers(dwc); 567 568 err1: 569 usb_phy_shutdown(dwc->usb2_phy); 570 usb_phy_shutdown(dwc->usb3_phy); 571 phy_exit(dwc->usb2_generic_phy); 572 phy_exit(dwc->usb3_generic_phy); 573 574 err0: 575 return ret; 576 } 577 578 static void dwc3_core_exit(struct dwc3 *dwc) 579 { 580 dwc3_free_scratch_buffers(dwc); 581 usb_phy_shutdown(dwc->usb2_phy); 582 usb_phy_shutdown(dwc->usb3_phy); 583 phy_exit(dwc->usb2_generic_phy); 584 phy_exit(dwc->usb3_generic_phy); 585 } 586 587 static int dwc3_core_get_phy(struct dwc3 *dwc) 588 { 589 struct device *dev = dwc->dev; 590 struct device_node *node = dev->of_node; 591 int ret; 592 593 if (node) { 594 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 595 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 596 } else { 597 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 598 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 599 } 600 601 if (IS_ERR(dwc->usb2_phy)) { 602 ret = PTR_ERR(dwc->usb2_phy); 603 if (ret == -ENXIO || ret == -ENODEV) { 604 dwc->usb2_phy = NULL; 605 } else if (ret == -EPROBE_DEFER) { 606 return ret; 607 } else { 608 dev_err(dev, "no usb2 phy configured\n"); 609 return ret; 610 } 611 } 612 613 if (IS_ERR(dwc->usb3_phy)) { 614 ret = PTR_ERR(dwc->usb3_phy); 615 if (ret == -ENXIO || ret == -ENODEV) { 616 dwc->usb3_phy = NULL; 617 } else if (ret == -EPROBE_DEFER) { 618 return ret; 619 } else { 620 dev_err(dev, "no usb3 phy configured\n"); 621 return ret; 622 } 623 } 624 625 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 626 if (IS_ERR(dwc->usb2_generic_phy)) { 627 ret = PTR_ERR(dwc->usb2_generic_phy); 628 if (ret == -ENOSYS || ret == -ENODEV) { 629 dwc->usb2_generic_phy = NULL; 630 } else if (ret == -EPROBE_DEFER) { 631 return ret; 632 } else { 633 dev_err(dev, "no usb2 phy configured\n"); 634 return ret; 635 } 636 } 637 638 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 639 if (IS_ERR(dwc->usb3_generic_phy)) { 640 ret = PTR_ERR(dwc->usb3_generic_phy); 641 if (ret == -ENOSYS || ret == -ENODEV) { 642 dwc->usb3_generic_phy = NULL; 643 } else if (ret == -EPROBE_DEFER) { 644 return ret; 645 } else { 646 dev_err(dev, "no usb3 phy configured\n"); 647 return ret; 648 } 649 } 650 651 return 0; 652 } 653 654 static int dwc3_core_init_mode(struct dwc3 *dwc) 655 { 656 struct device *dev = dwc->dev; 657 int ret; 658 659 switch (dwc->dr_mode) { 660 case USB_DR_MODE_PERIPHERAL: 661 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 662 ret = dwc3_gadget_init(dwc); 663 if (ret) { 664 dev_err(dev, "failed to initialize gadget\n"); 665 return ret; 666 } 667 break; 668 case USB_DR_MODE_HOST: 669 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 670 ret = dwc3_host_init(dwc); 671 if (ret) { 672 dev_err(dev, "failed to initialize host\n"); 673 return ret; 674 } 675 break; 676 case USB_DR_MODE_OTG: 677 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 678 ret = dwc3_host_init(dwc); 679 if (ret) { 680 dev_err(dev, "failed to initialize host\n"); 681 return ret; 682 } 683 684 ret = dwc3_gadget_init(dwc); 685 if (ret) { 686 dev_err(dev, "failed to initialize gadget\n"); 687 return ret; 688 } 689 break; 690 default: 691 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 692 return -EINVAL; 693 } 694 695 return 0; 696 } 697 698 static void dwc3_core_exit_mode(struct dwc3 *dwc) 699 { 700 switch (dwc->dr_mode) { 701 case USB_DR_MODE_PERIPHERAL: 702 dwc3_gadget_exit(dwc); 703 break; 704 case USB_DR_MODE_HOST: 705 dwc3_host_exit(dwc); 706 break; 707 case USB_DR_MODE_OTG: 708 dwc3_host_exit(dwc); 709 dwc3_gadget_exit(dwc); 710 break; 711 default: 712 /* do nothing */ 713 break; 714 } 715 } 716 717 #define DWC3_ALIGN_MASK (16 - 1) 718 719 static int dwc3_probe(struct platform_device *pdev) 720 { 721 struct device *dev = &pdev->dev; 722 struct dwc3_platform_data *pdata = dev_get_platdata(dev); 723 struct device_node *node = dev->of_node; 724 struct resource *res; 725 struct dwc3 *dwc; 726 u8 lpm_nyet_threshold; 727 u8 tx_de_emphasis; 728 u8 hird_threshold; 729 730 int ret; 731 732 void __iomem *regs; 733 void *mem; 734 735 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 736 if (!mem) 737 return -ENOMEM; 738 739 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 740 dwc->mem = mem; 741 dwc->dev = dev; 742 743 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 744 if (!res) { 745 dev_err(dev, "missing IRQ\n"); 746 return -ENODEV; 747 } 748 dwc->xhci_resources[1].start = res->start; 749 dwc->xhci_resources[1].end = res->end; 750 dwc->xhci_resources[1].flags = res->flags; 751 dwc->xhci_resources[1].name = res->name; 752 753 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 754 if (!res) { 755 dev_err(dev, "missing memory resource\n"); 756 return -ENODEV; 757 } 758 759 dwc->xhci_resources[0].start = res->start; 760 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 761 DWC3_XHCI_REGS_END; 762 dwc->xhci_resources[0].flags = res->flags; 763 dwc->xhci_resources[0].name = res->name; 764 765 res->start += DWC3_GLOBALS_REGS_START; 766 767 /* 768 * Request memory region but exclude xHCI regs, 769 * since it will be requested by the xhci-plat driver. 770 */ 771 regs = devm_ioremap_resource(dev, res); 772 if (IS_ERR(regs)) 773 return PTR_ERR(regs); 774 775 dwc->regs = regs; 776 dwc->regs_size = resource_size(res); 777 /* 778 * restore res->start back to its original value so that, 779 * in case the probe is deferred, we don't end up getting error in 780 * request the memory region the next time probe is called. 781 */ 782 res->start -= DWC3_GLOBALS_REGS_START; 783 784 /* default to highest possible threshold */ 785 lpm_nyet_threshold = 0xff; 786 787 /* default to -3.5dB de-emphasis */ 788 tx_de_emphasis = 1; 789 790 /* 791 * default to assert utmi_sleep_n and use maximum allowed HIRD 792 * threshold value of 0b1100 793 */ 794 hird_threshold = 12; 795 796 if (node) { 797 dwc->maximum_speed = of_usb_get_maximum_speed(node); 798 dwc->has_lpm_erratum = of_property_read_bool(node, 799 "snps,has-lpm-erratum"); 800 of_property_read_u8(node, "snps,lpm-nyet-threshold", 801 &lpm_nyet_threshold); 802 dwc->is_utmi_l1_suspend = of_property_read_bool(node, 803 "snps,is-utmi-l1-suspend"); 804 of_property_read_u8(node, "snps,hird-threshold", 805 &hird_threshold); 806 807 dwc->needs_fifo_resize = of_property_read_bool(node, 808 "tx-fifo-resize"); 809 dwc->dr_mode = of_usb_get_dr_mode(node); 810 811 dwc->disable_scramble_quirk = of_property_read_bool(node, 812 "snps,disable_scramble_quirk"); 813 dwc->u2exit_lfps_quirk = of_property_read_bool(node, 814 "snps,u2exit_lfps_quirk"); 815 dwc->u2ss_inp3_quirk = of_property_read_bool(node, 816 "snps,u2ss_inp3_quirk"); 817 dwc->req_p1p2p3_quirk = of_property_read_bool(node, 818 "snps,req_p1p2p3_quirk"); 819 dwc->del_p1p2p3_quirk = of_property_read_bool(node, 820 "snps,del_p1p2p3_quirk"); 821 dwc->del_phy_power_chg_quirk = of_property_read_bool(node, 822 "snps,del_phy_power_chg_quirk"); 823 dwc->lfps_filter_quirk = of_property_read_bool(node, 824 "snps,lfps_filter_quirk"); 825 dwc->rx_detect_poll_quirk = of_property_read_bool(node, 826 "snps,rx_detect_poll_quirk"); 827 dwc->dis_u3_susphy_quirk = of_property_read_bool(node, 828 "snps,dis_u3_susphy_quirk"); 829 dwc->dis_u2_susphy_quirk = of_property_read_bool(node, 830 "snps,dis_u2_susphy_quirk"); 831 832 dwc->tx_de_emphasis_quirk = of_property_read_bool(node, 833 "snps,tx_de_emphasis_quirk"); 834 of_property_read_u8(node, "snps,tx_de_emphasis", 835 &tx_de_emphasis); 836 } else if (pdata) { 837 dwc->maximum_speed = pdata->maximum_speed; 838 dwc->has_lpm_erratum = pdata->has_lpm_erratum; 839 if (pdata->lpm_nyet_threshold) 840 lpm_nyet_threshold = pdata->lpm_nyet_threshold; 841 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; 842 if (pdata->hird_threshold) 843 hird_threshold = pdata->hird_threshold; 844 845 dwc->needs_fifo_resize = pdata->tx_fifo_resize; 846 dwc->dr_mode = pdata->dr_mode; 847 848 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; 849 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; 850 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; 851 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; 852 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; 853 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; 854 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; 855 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; 856 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; 857 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; 858 859 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; 860 if (pdata->tx_de_emphasis) 861 tx_de_emphasis = pdata->tx_de_emphasis; 862 } 863 864 /* default to superspeed if no maximum_speed passed */ 865 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 866 dwc->maximum_speed = USB_SPEED_SUPER; 867 868 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 869 dwc->tx_de_emphasis = tx_de_emphasis; 870 871 dwc->hird_threshold = hird_threshold 872 | (dwc->is_utmi_l1_suspend << 4); 873 874 ret = dwc3_core_get_phy(dwc); 875 if (ret) 876 return ret; 877 878 spin_lock_init(&dwc->lock); 879 platform_set_drvdata(pdev, dwc); 880 881 if (!dev->dma_mask) { 882 dev->dma_mask = dev->parent->dma_mask; 883 dev->dma_parms = dev->parent->dma_parms; 884 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); 885 } 886 887 pm_runtime_enable(dev); 888 pm_runtime_get_sync(dev); 889 pm_runtime_forbid(dev); 890 891 dwc3_cache_hwparams(dwc); 892 893 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 894 if (ret) { 895 dev_err(dwc->dev, "failed to allocate event buffers\n"); 896 ret = -ENOMEM; 897 goto err0; 898 } 899 900 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 901 dwc->dr_mode = USB_DR_MODE_HOST; 902 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 903 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 904 905 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 906 dwc->dr_mode = USB_DR_MODE_OTG; 907 908 ret = dwc3_core_init(dwc); 909 if (ret) { 910 dev_err(dev, "failed to initialize core\n"); 911 goto err0; 912 } 913 914 usb_phy_set_suspend(dwc->usb2_phy, 0); 915 usb_phy_set_suspend(dwc->usb3_phy, 0); 916 ret = phy_power_on(dwc->usb2_generic_phy); 917 if (ret < 0) 918 goto err1; 919 920 ret = phy_power_on(dwc->usb3_generic_phy); 921 if (ret < 0) 922 goto err_usb2phy_power; 923 924 ret = dwc3_event_buffers_setup(dwc); 925 if (ret) { 926 dev_err(dwc->dev, "failed to setup event buffers\n"); 927 goto err_usb3phy_power; 928 } 929 930 ret = dwc3_core_init_mode(dwc); 931 if (ret) 932 goto err2; 933 934 ret = dwc3_debugfs_init(dwc); 935 if (ret) { 936 dev_err(dev, "failed to initialize debugfs\n"); 937 goto err3; 938 } 939 940 pm_runtime_allow(dev); 941 942 return 0; 943 944 err3: 945 dwc3_core_exit_mode(dwc); 946 947 err2: 948 dwc3_event_buffers_cleanup(dwc); 949 950 err_usb3phy_power: 951 phy_power_off(dwc->usb3_generic_phy); 952 953 err_usb2phy_power: 954 phy_power_off(dwc->usb2_generic_phy); 955 956 err1: 957 usb_phy_set_suspend(dwc->usb2_phy, 1); 958 usb_phy_set_suspend(dwc->usb3_phy, 1); 959 dwc3_core_exit(dwc); 960 961 err0: 962 dwc3_free_event_buffers(dwc); 963 964 return ret; 965 } 966 967 static int dwc3_remove(struct platform_device *pdev) 968 { 969 struct dwc3 *dwc = platform_get_drvdata(pdev); 970 971 dwc3_debugfs_exit(dwc); 972 dwc3_core_exit_mode(dwc); 973 dwc3_event_buffers_cleanup(dwc); 974 dwc3_free_event_buffers(dwc); 975 976 usb_phy_set_suspend(dwc->usb2_phy, 1); 977 usb_phy_set_suspend(dwc->usb3_phy, 1); 978 phy_power_off(dwc->usb2_generic_phy); 979 phy_power_off(dwc->usb3_generic_phy); 980 981 dwc3_core_exit(dwc); 982 983 pm_runtime_put_sync(&pdev->dev); 984 pm_runtime_disable(&pdev->dev); 985 986 return 0; 987 } 988 989 #ifdef CONFIG_PM_SLEEP 990 static int dwc3_suspend(struct device *dev) 991 { 992 struct dwc3 *dwc = dev_get_drvdata(dev); 993 unsigned long flags; 994 995 spin_lock_irqsave(&dwc->lock, flags); 996 997 switch (dwc->dr_mode) { 998 case USB_DR_MODE_PERIPHERAL: 999 case USB_DR_MODE_OTG: 1000 dwc3_gadget_suspend(dwc); 1001 /* FALLTHROUGH */ 1002 case USB_DR_MODE_HOST: 1003 default: 1004 dwc3_event_buffers_cleanup(dwc); 1005 break; 1006 } 1007 1008 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); 1009 spin_unlock_irqrestore(&dwc->lock, flags); 1010 1011 usb_phy_shutdown(dwc->usb3_phy); 1012 usb_phy_shutdown(dwc->usb2_phy); 1013 phy_exit(dwc->usb2_generic_phy); 1014 phy_exit(dwc->usb3_generic_phy); 1015 1016 return 0; 1017 } 1018 1019 static int dwc3_resume(struct device *dev) 1020 { 1021 struct dwc3 *dwc = dev_get_drvdata(dev); 1022 unsigned long flags; 1023 int ret; 1024 1025 usb_phy_init(dwc->usb3_phy); 1026 usb_phy_init(dwc->usb2_phy); 1027 ret = phy_init(dwc->usb2_generic_phy); 1028 if (ret < 0) 1029 return ret; 1030 1031 ret = phy_init(dwc->usb3_generic_phy); 1032 if (ret < 0) 1033 goto err_usb2phy_init; 1034 1035 spin_lock_irqsave(&dwc->lock, flags); 1036 1037 dwc3_event_buffers_setup(dwc); 1038 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); 1039 1040 switch (dwc->dr_mode) { 1041 case USB_DR_MODE_PERIPHERAL: 1042 case USB_DR_MODE_OTG: 1043 dwc3_gadget_resume(dwc); 1044 /* FALLTHROUGH */ 1045 case USB_DR_MODE_HOST: 1046 default: 1047 /* do nothing */ 1048 break; 1049 } 1050 1051 spin_unlock_irqrestore(&dwc->lock, flags); 1052 1053 pm_runtime_disable(dev); 1054 pm_runtime_set_active(dev); 1055 pm_runtime_enable(dev); 1056 1057 return 0; 1058 1059 err_usb2phy_init: 1060 phy_exit(dwc->usb2_generic_phy); 1061 1062 return ret; 1063 } 1064 1065 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1066 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1067 }; 1068 1069 #define DWC3_PM_OPS &(dwc3_dev_pm_ops) 1070 #else 1071 #define DWC3_PM_OPS NULL 1072 #endif 1073 1074 #ifdef CONFIG_OF 1075 static const struct of_device_id of_dwc3_match[] = { 1076 { 1077 .compatible = "snps,dwc3" 1078 }, 1079 { 1080 .compatible = "synopsys,dwc3" 1081 }, 1082 { }, 1083 }; 1084 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1085 #endif 1086 1087 #ifdef CONFIG_ACPI 1088 1089 #define ACPI_ID_INTEL_BSW "808622B7" 1090 1091 static const struct acpi_device_id dwc3_acpi_match[] = { 1092 { ACPI_ID_INTEL_BSW, 0 }, 1093 { }, 1094 }; 1095 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1096 #endif 1097 1098 static struct platform_driver dwc3_driver = { 1099 .probe = dwc3_probe, 1100 .remove = dwc3_remove, 1101 .driver = { 1102 .name = "dwc3", 1103 .of_match_table = of_match_ptr(of_dwc3_match), 1104 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1105 .pm = DWC3_PM_OPS, 1106 }, 1107 }; 1108 1109 module_platform_driver(dwc3_driver); 1110 1111 MODULE_ALIAS("platform:dwc3"); 1112 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1113 MODULE_LICENSE("GPL v2"); 1114 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1115