1*b75fdc11SChristophe Ricard /* 2*b75fdc11SChristophe Ricard * STMicroelectronics TPM ST33ZP24 SPI UBOOT driver 3*b75fdc11SChristophe Ricard * 4*b75fdc11SChristophe Ricard * Copyright (C) 2016 STMicroelectronics 5*b75fdc11SChristophe Ricard * 6*b75fdc11SChristophe Ricard * Description: Device driver for ST33ZP24 SPI TPM TCG. 7*b75fdc11SChristophe Ricard * 8*b75fdc11SChristophe Ricard * This device driver implements the TPM interface as defined in 9*b75fdc11SChristophe Ricard * the TCG TPM Interface Spec version 1.21, revision 1.0 and the 10*b75fdc11SChristophe Ricard * STMicroelectronics Protocol Stack Specification version 1.2.0. 11*b75fdc11SChristophe Ricard * 12*b75fdc11SChristophe Ricard * SPDX-License-Identifier: GPL-2.0+ 13*b75fdc11SChristophe Ricard */ 14*b75fdc11SChristophe Ricard 15*b75fdc11SChristophe Ricard #include <common.h> 16*b75fdc11SChristophe Ricard #include <dm.h> 17*b75fdc11SChristophe Ricard #include <fdtdec.h> 18*b75fdc11SChristophe Ricard #include <spi.h> 19*b75fdc11SChristophe Ricard #include <tpm.h> 20*b75fdc11SChristophe Ricard #include <errno.h> 21*b75fdc11SChristophe Ricard #include <linux/types.h> 22*b75fdc11SChristophe Ricard #include <asm/unaligned.h> 23*b75fdc11SChristophe Ricard #include <linux/compat.h> 24*b75fdc11SChristophe Ricard 25*b75fdc11SChristophe Ricard #include "tpm_tis.h" 26*b75fdc11SChristophe Ricard #include "tpm_internal.h" 27*b75fdc11SChristophe Ricard 28*b75fdc11SChristophe Ricard #define TPM_ACCESS 0x0 29*b75fdc11SChristophe Ricard #define TPM_STS 0x18 30*b75fdc11SChristophe Ricard #define TPM_DATA_FIFO 0x24 31*b75fdc11SChristophe Ricard 32*b75fdc11SChristophe Ricard #define LOCALITY0 0 33*b75fdc11SChristophe Ricard 34*b75fdc11SChristophe Ricard #define TPM_DATA_FIFO 0x24 35*b75fdc11SChristophe Ricard #define TPM_INTF_CAPABILITY 0x14 36*b75fdc11SChristophe Ricard 37*b75fdc11SChristophe Ricard #define TPM_DUMMY_BYTE 0x00 38*b75fdc11SChristophe Ricard #define TPM_WRITE_DIRECTION 0x80 39*b75fdc11SChristophe Ricard 40*b75fdc11SChristophe Ricard #define MAX_SPI_LATENCY 15 41*b75fdc11SChristophe Ricard #define LOCALITY0 0 42*b75fdc11SChristophe Ricard 43*b75fdc11SChristophe Ricard #define ST33ZP24_OK 0x5A 44*b75fdc11SChristophe Ricard #define ST33ZP24_UNDEFINED_ERR 0x80 45*b75fdc11SChristophe Ricard #define ST33ZP24_BADLOCALITY 0x81 46*b75fdc11SChristophe Ricard #define ST33ZP24_TISREGISTER_UKNOWN 0x82 47*b75fdc11SChristophe Ricard #define ST33ZP24_LOCALITY_NOT_ACTIVATED 0x83 48*b75fdc11SChristophe Ricard #define ST33ZP24_HASH_END_BEFORE_HASH_START 0x84 49*b75fdc11SChristophe Ricard #define ST33ZP24_BAD_COMMAND_ORDER 0x85 50*b75fdc11SChristophe Ricard #define ST33ZP24_INCORECT_RECEIVED_LENGTH 0x86 51*b75fdc11SChristophe Ricard #define ST33ZP24_TPM_FIFO_OVERFLOW 0x89 52*b75fdc11SChristophe Ricard #define ST33ZP24_UNEXPECTED_READ_FIFO 0x8A 53*b75fdc11SChristophe Ricard #define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B 54*b75fdc11SChristophe Ricard #define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END 0x90 55*b75fdc11SChristophe Ricard #define ST33ZP24_DUMMY_BYTES 0x00 56*b75fdc11SChristophe Ricard 57*b75fdc11SChristophe Ricard /* 58*b75fdc11SChristophe Ricard * TPM command can be up to 2048 byte, A TPM response can be up to 59*b75fdc11SChristophe Ricard * 1024 byte. 60*b75fdc11SChristophe Ricard * Between command and response, there are latency byte (up to 15 61*b75fdc11SChristophe Ricard * usually on st33zp24 2 are enough). 62*b75fdc11SChristophe Ricard * 63*b75fdc11SChristophe Ricard * Overall when sending a command and expecting an answer we need if 64*b75fdc11SChristophe Ricard * worst case: 65*b75fdc11SChristophe Ricard * 2048 (for the TPM command) + 1024 (for the TPM answer). We need 66*b75fdc11SChristophe Ricard * some latency byte before the answer is available (max 15). 67*b75fdc11SChristophe Ricard * We have 2048 + 1024 + 15. 68*b75fdc11SChristophe Ricard */ 69*b75fdc11SChristophe Ricard #define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\ 70*b75fdc11SChristophe Ricard MAX_SPI_LATENCY) 71*b75fdc11SChristophe Ricard 72*b75fdc11SChristophe Ricard struct st33zp24_spi_phy { 73*b75fdc11SChristophe Ricard int latency; 74*b75fdc11SChristophe Ricard 75*b75fdc11SChristophe Ricard u8 tx_buf[ST33ZP24_SPI_BUFFER_SIZE]; 76*b75fdc11SChristophe Ricard u8 rx_buf[ST33ZP24_SPI_BUFFER_SIZE]; 77*b75fdc11SChristophe Ricard }; 78*b75fdc11SChristophe Ricard 79*b75fdc11SChristophe Ricard static int st33zp24_spi_status_to_errno(u8 code) 80*b75fdc11SChristophe Ricard { 81*b75fdc11SChristophe Ricard switch (code) { 82*b75fdc11SChristophe Ricard case ST33ZP24_OK: 83*b75fdc11SChristophe Ricard return 0; 84*b75fdc11SChristophe Ricard case ST33ZP24_UNDEFINED_ERR: 85*b75fdc11SChristophe Ricard case ST33ZP24_BADLOCALITY: 86*b75fdc11SChristophe Ricard case ST33ZP24_TISREGISTER_UKNOWN: 87*b75fdc11SChristophe Ricard case ST33ZP24_LOCALITY_NOT_ACTIVATED: 88*b75fdc11SChristophe Ricard case ST33ZP24_HASH_END_BEFORE_HASH_START: 89*b75fdc11SChristophe Ricard case ST33ZP24_BAD_COMMAND_ORDER: 90*b75fdc11SChristophe Ricard case ST33ZP24_UNEXPECTED_READ_FIFO: 91*b75fdc11SChristophe Ricard case ST33ZP24_UNEXPECTED_WRITE_FIFO: 92*b75fdc11SChristophe Ricard case ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END: 93*b75fdc11SChristophe Ricard return -EPROTO; 94*b75fdc11SChristophe Ricard case ST33ZP24_INCORECT_RECEIVED_LENGTH: 95*b75fdc11SChristophe Ricard case ST33ZP24_TPM_FIFO_OVERFLOW: 96*b75fdc11SChristophe Ricard return -EMSGSIZE; 97*b75fdc11SChristophe Ricard case ST33ZP24_DUMMY_BYTES: 98*b75fdc11SChristophe Ricard return -ENOSYS; 99*b75fdc11SChristophe Ricard } 100*b75fdc11SChristophe Ricard return code; 101*b75fdc11SChristophe Ricard } 102*b75fdc11SChristophe Ricard 103*b75fdc11SChristophe Ricard /* 104*b75fdc11SChristophe Ricard * st33zp24_spi_send 105*b75fdc11SChristophe Ricard * Send byte to TPM register according to the ST33ZP24 SPI protocol. 106*b75fdc11SChristophe Ricard * @param: tpm, the chip description 107*b75fdc11SChristophe Ricard * @param: tpm_register, the tpm tis register where the data should be written 108*b75fdc11SChristophe Ricard * @param: tpm_data, the tpm_data to write inside the tpm_register 109*b75fdc11SChristophe Ricard * @param: tpm_size, The length of the data 110*b75fdc11SChristophe Ricard * @return: should be zero if success else a negative error code. 111*b75fdc11SChristophe Ricard */ 112*b75fdc11SChristophe Ricard static int st33zp24_spi_write(struct udevice *dev, u8 tpm_register, 113*b75fdc11SChristophe Ricard const u8 *tpm_data, size_t tpm_size) 114*b75fdc11SChristophe Ricard { 115*b75fdc11SChristophe Ricard int total_length = 0, ret; 116*b75fdc11SChristophe Ricard struct spi_slave *slave = dev_get_parent_priv(dev); 117*b75fdc11SChristophe Ricard struct st33zp24_spi_phy *phy = dev_get_platdata(dev); 118*b75fdc11SChristophe Ricard 119*b75fdc11SChristophe Ricard u8 *tx_buf = (u8 *)phy->tx_buf; 120*b75fdc11SChristophe Ricard u8 *rx_buf = phy->rx_buf; 121*b75fdc11SChristophe Ricard 122*b75fdc11SChristophe Ricard tx_buf[total_length++] = TPM_WRITE_DIRECTION | LOCALITY0; 123*b75fdc11SChristophe Ricard tx_buf[total_length++] = tpm_register; 124*b75fdc11SChristophe Ricard 125*b75fdc11SChristophe Ricard if (tpm_size > 0 && tpm_register == TPM_DATA_FIFO) { 126*b75fdc11SChristophe Ricard tx_buf[total_length++] = tpm_size >> 8; 127*b75fdc11SChristophe Ricard tx_buf[total_length++] = tpm_size; 128*b75fdc11SChristophe Ricard } 129*b75fdc11SChristophe Ricard memcpy(tx_buf + total_length, tpm_data, tpm_size); 130*b75fdc11SChristophe Ricard total_length += tpm_size; 131*b75fdc11SChristophe Ricard 132*b75fdc11SChristophe Ricard memset(tx_buf + total_length, TPM_DUMMY_BYTE, phy->latency); 133*b75fdc11SChristophe Ricard 134*b75fdc11SChristophe Ricard total_length += phy->latency; 135*b75fdc11SChristophe Ricard 136*b75fdc11SChristophe Ricard ret = spi_claim_bus(slave); 137*b75fdc11SChristophe Ricard if (ret < 0) 138*b75fdc11SChristophe Ricard return ret; 139*b75fdc11SChristophe Ricard 140*b75fdc11SChristophe Ricard ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, 141*b75fdc11SChristophe Ricard SPI_XFER_BEGIN | SPI_XFER_END); 142*b75fdc11SChristophe Ricard if (ret < 0) 143*b75fdc11SChristophe Ricard return ret; 144*b75fdc11SChristophe Ricard 145*b75fdc11SChristophe Ricard spi_release_bus(slave); 146*b75fdc11SChristophe Ricard 147*b75fdc11SChristophe Ricard if (ret == 0) 148*b75fdc11SChristophe Ricard ret = rx_buf[total_length - 1]; 149*b75fdc11SChristophe Ricard 150*b75fdc11SChristophe Ricard return st33zp24_spi_status_to_errno(ret); 151*b75fdc11SChristophe Ricard } 152*b75fdc11SChristophe Ricard 153*b75fdc11SChristophe Ricard /* 154*b75fdc11SChristophe Ricard * spi_st33zp24_spi_read8_reg 155*b75fdc11SChristophe Ricard * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. 156*b75fdc11SChristophe Ricard * @param: tpm, the chip description 157*b75fdc11SChristophe Ricard * @param: tpm_loc, the locality to read register from 158*b75fdc11SChristophe Ricard * @param: tpm_register, the tpm tis register where the data should be read 159*b75fdc11SChristophe Ricard * @param: tpm_data, the TPM response 160*b75fdc11SChristophe Ricard * @param: tpm_size, tpm TPM response size to read. 161*b75fdc11SChristophe Ricard * @return: should be zero if success else a negative error code. 162*b75fdc11SChristophe Ricard */ 163*b75fdc11SChristophe Ricard static u8 st33zp24_spi_read8_reg(struct udevice *dev, u8 tpm_register, 164*b75fdc11SChristophe Ricard u8 *tpm_data, size_t tpm_size) 165*b75fdc11SChristophe Ricard { 166*b75fdc11SChristophe Ricard int total_length = 0, ret; 167*b75fdc11SChristophe Ricard struct spi_slave *slave = dev_get_parent_priv(dev); 168*b75fdc11SChristophe Ricard struct st33zp24_spi_phy *phy = dev_get_platdata(dev); 169*b75fdc11SChristophe Ricard 170*b75fdc11SChristophe Ricard u8 *tx_buf = (u8 *)phy->tx_buf; 171*b75fdc11SChristophe Ricard u8 *rx_buf = phy->rx_buf; 172*b75fdc11SChristophe Ricard 173*b75fdc11SChristophe Ricard /* Pre-Header */ 174*b75fdc11SChristophe Ricard tx_buf[total_length++] = LOCALITY0; 175*b75fdc11SChristophe Ricard tx_buf[total_length++] = tpm_register; 176*b75fdc11SChristophe Ricard 177*b75fdc11SChristophe Ricard memset(&tx_buf[total_length], TPM_DUMMY_BYTE, 178*b75fdc11SChristophe Ricard phy->latency + tpm_size); 179*b75fdc11SChristophe Ricard total_length += phy->latency + tpm_size; 180*b75fdc11SChristophe Ricard 181*b75fdc11SChristophe Ricard ret = spi_claim_bus(slave); 182*b75fdc11SChristophe Ricard if (ret < 0) 183*b75fdc11SChristophe Ricard return 0; 184*b75fdc11SChristophe Ricard 185*b75fdc11SChristophe Ricard ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, 186*b75fdc11SChristophe Ricard SPI_XFER_BEGIN | SPI_XFER_END); 187*b75fdc11SChristophe Ricard if (ret < 0) 188*b75fdc11SChristophe Ricard return 0; 189*b75fdc11SChristophe Ricard 190*b75fdc11SChristophe Ricard spi_release_bus(slave); 191*b75fdc11SChristophe Ricard 192*b75fdc11SChristophe Ricard if (tpm_size > 0 && ret == 0) { 193*b75fdc11SChristophe Ricard ret = rx_buf[total_length - tpm_size - 1]; 194*b75fdc11SChristophe Ricard memcpy(tpm_data, rx_buf + total_length - tpm_size, tpm_size); 195*b75fdc11SChristophe Ricard } 196*b75fdc11SChristophe Ricard return ret; 197*b75fdc11SChristophe Ricard } 198*b75fdc11SChristophe Ricard 199*b75fdc11SChristophe Ricard /* 200*b75fdc11SChristophe Ricard * st33zp24_spi_recv 201*b75fdc11SChristophe Ricard * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. 202*b75fdc11SChristophe Ricard * @param: phy_id, the phy description 203*b75fdc11SChristophe Ricard * @param: tpm_register, the tpm tis register where the data should be read 204*b75fdc11SChristophe Ricard * @param: tpm_data, the TPM response 205*b75fdc11SChristophe Ricard * @param: tpm_size, tpm TPM response size to read. 206*b75fdc11SChristophe Ricard * @return: number of byte read successfully: should be one if success. 207*b75fdc11SChristophe Ricard */ 208*b75fdc11SChristophe Ricard static int st33zp24_spi_read(struct udevice *dev, u8 tpm_register, 209*b75fdc11SChristophe Ricard u8 *tpm_data, size_t tpm_size) 210*b75fdc11SChristophe Ricard { 211*b75fdc11SChristophe Ricard int ret; 212*b75fdc11SChristophe Ricard 213*b75fdc11SChristophe Ricard ret = st33zp24_spi_read8_reg(dev, tpm_register, tpm_data, tpm_size); 214*b75fdc11SChristophe Ricard if (!st33zp24_spi_status_to_errno(ret)) 215*b75fdc11SChristophe Ricard return tpm_size; 216*b75fdc11SChristophe Ricard 217*b75fdc11SChristophe Ricard return ret; 218*b75fdc11SChristophe Ricard } 219*b75fdc11SChristophe Ricard 220*b75fdc11SChristophe Ricard static int st33zp24_spi_evaluate_latency(struct udevice *dev) 221*b75fdc11SChristophe Ricard { 222*b75fdc11SChristophe Ricard int latency = 1, status = 0; 223*b75fdc11SChristophe Ricard u8 data = 0; 224*b75fdc11SChristophe Ricard struct st33zp24_spi_phy *phy = dev_get_platdata(dev); 225*b75fdc11SChristophe Ricard 226*b75fdc11SChristophe Ricard while (!status && latency < MAX_SPI_LATENCY) { 227*b75fdc11SChristophe Ricard phy->latency = latency; 228*b75fdc11SChristophe Ricard status = st33zp24_spi_read8_reg(dev, TPM_INTF_CAPABILITY, 229*b75fdc11SChristophe Ricard &data, 1); 230*b75fdc11SChristophe Ricard latency++; 231*b75fdc11SChristophe Ricard } 232*b75fdc11SChristophe Ricard if (status < 0) 233*b75fdc11SChristophe Ricard return status; 234*b75fdc11SChristophe Ricard if (latency == MAX_SPI_LATENCY) 235*b75fdc11SChristophe Ricard return -ENODEV; 236*b75fdc11SChristophe Ricard 237*b75fdc11SChristophe Ricard return latency - 1; 238*b75fdc11SChristophe Ricard } 239*b75fdc11SChristophe Ricard 240*b75fdc11SChristophe Ricard /* 241*b75fdc11SChristophe Ricard * st33zp24_spi_release_locality release the active locality 242*b75fdc11SChristophe Ricard * @param: chip, the tpm chip description. 243*b75fdc11SChristophe Ricard */ 244*b75fdc11SChristophe Ricard static void st33zp24_spi_release_locality(struct udevice *dev) 245*b75fdc11SChristophe Ricard { 246*b75fdc11SChristophe Ricard u8 data = TPM_ACCESS_ACTIVE_LOCALITY; 247*b75fdc11SChristophe Ricard 248*b75fdc11SChristophe Ricard st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); 249*b75fdc11SChristophe Ricard } 250*b75fdc11SChristophe Ricard 251*b75fdc11SChristophe Ricard /* 252*b75fdc11SChristophe Ricard * st33zp24_spi_check_locality if the locality is active 253*b75fdc11SChristophe Ricard * @param: chip, the tpm chip description 254*b75fdc11SChristophe Ricard * @return: the active locality or -EACCES. 255*b75fdc11SChristophe Ricard */ 256*b75fdc11SChristophe Ricard static int st33zp24_spi_check_locality(struct udevice *dev) 257*b75fdc11SChristophe Ricard { 258*b75fdc11SChristophe Ricard u8 data; 259*b75fdc11SChristophe Ricard u8 status; 260*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 261*b75fdc11SChristophe Ricard 262*b75fdc11SChristophe Ricard status = st33zp24_spi_read(dev, TPM_ACCESS, &data, 1); 263*b75fdc11SChristophe Ricard if (status && (data & 264*b75fdc11SChristophe Ricard (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == 265*b75fdc11SChristophe Ricard (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) 266*b75fdc11SChristophe Ricard return chip->locality; 267*b75fdc11SChristophe Ricard 268*b75fdc11SChristophe Ricard return -EACCES; 269*b75fdc11SChristophe Ricard } 270*b75fdc11SChristophe Ricard 271*b75fdc11SChristophe Ricard /* 272*b75fdc11SChristophe Ricard * st33zp24_spi_request_locality request the TPM locality 273*b75fdc11SChristophe Ricard * @param: chip, the chip description 274*b75fdc11SChristophe Ricard * @return: the active locality or negative value. 275*b75fdc11SChristophe Ricard */ 276*b75fdc11SChristophe Ricard static int st33zp24_spi_request_locality(struct udevice *dev) 277*b75fdc11SChristophe Ricard { 278*b75fdc11SChristophe Ricard unsigned long start, stop; 279*b75fdc11SChristophe Ricard long ret; 280*b75fdc11SChristophe Ricard u8 data; 281*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 282*b75fdc11SChristophe Ricard 283*b75fdc11SChristophe Ricard if (st33zp24_spi_check_locality(dev) == chip->locality) 284*b75fdc11SChristophe Ricard return chip->locality; 285*b75fdc11SChristophe Ricard 286*b75fdc11SChristophe Ricard data = TPM_ACCESS_REQUEST_USE; 287*b75fdc11SChristophe Ricard ret = st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); 288*b75fdc11SChristophe Ricard if (ret < 0) 289*b75fdc11SChristophe Ricard return ret; 290*b75fdc11SChristophe Ricard 291*b75fdc11SChristophe Ricard /* wait for locality activated */ 292*b75fdc11SChristophe Ricard start = get_timer(0); 293*b75fdc11SChristophe Ricard stop = chip->timeout_a; 294*b75fdc11SChristophe Ricard do { 295*b75fdc11SChristophe Ricard if (st33zp24_spi_check_locality(dev) >= 0) 296*b75fdc11SChristophe Ricard return chip->locality; 297*b75fdc11SChristophe Ricard udelay(TPM_TIMEOUT_MS * 1000); 298*b75fdc11SChristophe Ricard } while (get_timer(start) < stop); 299*b75fdc11SChristophe Ricard 300*b75fdc11SChristophe Ricard return -EACCES; 301*b75fdc11SChristophe Ricard } 302*b75fdc11SChristophe Ricard 303*b75fdc11SChristophe Ricard /* 304*b75fdc11SChristophe Ricard * st33zp24_spi_status return the TPM_STS register 305*b75fdc11SChristophe Ricard * @param: chip, the tpm chip description 306*b75fdc11SChristophe Ricard * @return: the TPM_STS register value. 307*b75fdc11SChristophe Ricard */ 308*b75fdc11SChristophe Ricard static u8 st33zp24_spi_status(struct udevice *dev) 309*b75fdc11SChristophe Ricard { 310*b75fdc11SChristophe Ricard u8 data; 311*b75fdc11SChristophe Ricard 312*b75fdc11SChristophe Ricard st33zp24_spi_read(dev, TPM_STS, &data, 1); 313*b75fdc11SChristophe Ricard return data; 314*b75fdc11SChristophe Ricard } 315*b75fdc11SChristophe Ricard 316*b75fdc11SChristophe Ricard /* 317*b75fdc11SChristophe Ricard * st33zp24_spi_get_burstcount return the burstcount address 0x19 0x1A 318*b75fdc11SChristophe Ricard * @param: chip, the chip description 319*b75fdc11SChristophe Ricard * return: the burstcount or -TPM_DRIVER_ERR in case of error. 320*b75fdc11SChristophe Ricard */ 321*b75fdc11SChristophe Ricard static int st33zp24_spi_get_burstcount(struct udevice *dev) 322*b75fdc11SChristophe Ricard { 323*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 324*b75fdc11SChristophe Ricard unsigned long start, stop; 325*b75fdc11SChristophe Ricard int burstcnt, status; 326*b75fdc11SChristophe Ricard u8 tpm_reg, temp; 327*b75fdc11SChristophe Ricard 328*b75fdc11SChristophe Ricard /* wait for burstcount */ 329*b75fdc11SChristophe Ricard start = get_timer(0); 330*b75fdc11SChristophe Ricard stop = chip->timeout_d; 331*b75fdc11SChristophe Ricard do { 332*b75fdc11SChristophe Ricard tpm_reg = TPM_STS + 1; 333*b75fdc11SChristophe Ricard status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); 334*b75fdc11SChristophe Ricard if (status < 0) 335*b75fdc11SChristophe Ricard return -EBUSY; 336*b75fdc11SChristophe Ricard 337*b75fdc11SChristophe Ricard tpm_reg = TPM_STS + 2; 338*b75fdc11SChristophe Ricard burstcnt = temp; 339*b75fdc11SChristophe Ricard status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); 340*b75fdc11SChristophe Ricard if (status < 0) 341*b75fdc11SChristophe Ricard return -EBUSY; 342*b75fdc11SChristophe Ricard 343*b75fdc11SChristophe Ricard burstcnt |= temp << 8; 344*b75fdc11SChristophe Ricard if (burstcnt) 345*b75fdc11SChristophe Ricard return burstcnt; 346*b75fdc11SChristophe Ricard udelay(TIS_SHORT_TIMEOUT_MS * 1000); 347*b75fdc11SChristophe Ricard } while (get_timer(start) < stop); 348*b75fdc11SChristophe Ricard 349*b75fdc11SChristophe Ricard return -EBUSY; 350*b75fdc11SChristophe Ricard } 351*b75fdc11SChristophe Ricard 352*b75fdc11SChristophe Ricard /* 353*b75fdc11SChristophe Ricard * st33zp24_spi_cancel, cancel the current command execution or 354*b75fdc11SChristophe Ricard * set STS to COMMAND READY. 355*b75fdc11SChristophe Ricard * @param: chip, tpm_chip description. 356*b75fdc11SChristophe Ricard */ 357*b75fdc11SChristophe Ricard static void st33zp24_spi_cancel(struct udevice *dev) 358*b75fdc11SChristophe Ricard { 359*b75fdc11SChristophe Ricard u8 data; 360*b75fdc11SChristophe Ricard 361*b75fdc11SChristophe Ricard data = TPM_STS_COMMAND_READY; 362*b75fdc11SChristophe Ricard st33zp24_spi_write(dev, TPM_STS, &data, 1); 363*b75fdc11SChristophe Ricard } 364*b75fdc11SChristophe Ricard 365*b75fdc11SChristophe Ricard /* 366*b75fdc11SChristophe Ricard * st33zp24_spi_wait_for_stat wait for a TPM_STS value 367*b75fdc11SChristophe Ricard * @param: chip, the tpm chip description 368*b75fdc11SChristophe Ricard * @param: mask, the value mask to wait 369*b75fdc11SChristophe Ricard * @param: timeout, the timeout 370*b75fdc11SChristophe Ricard * @param: status, 371*b75fdc11SChristophe Ricard * @return: the tpm status, 0 if success, -ETIME if timeout is reached. 372*b75fdc11SChristophe Ricard */ 373*b75fdc11SChristophe Ricard static int st33zp24_spi_wait_for_stat(struct udevice *dev, u8 mask, 374*b75fdc11SChristophe Ricard unsigned long timeout, int *status) 375*b75fdc11SChristophe Ricard { 376*b75fdc11SChristophe Ricard unsigned long start, stop; 377*b75fdc11SChristophe Ricard 378*b75fdc11SChristophe Ricard /* Check current status */ 379*b75fdc11SChristophe Ricard *status = st33zp24_spi_status(dev); 380*b75fdc11SChristophe Ricard if ((*status & mask) == mask) 381*b75fdc11SChristophe Ricard return 0; 382*b75fdc11SChristophe Ricard 383*b75fdc11SChristophe Ricard start = get_timer(0); 384*b75fdc11SChristophe Ricard stop = timeout; 385*b75fdc11SChristophe Ricard do { 386*b75fdc11SChristophe Ricard udelay(TPM_TIMEOUT_MS * 1000); 387*b75fdc11SChristophe Ricard *status = st33zp24_spi_status(dev); 388*b75fdc11SChristophe Ricard if ((*status & mask) == mask) 389*b75fdc11SChristophe Ricard return 0; 390*b75fdc11SChristophe Ricard } while (get_timer(start) < stop); 391*b75fdc11SChristophe Ricard 392*b75fdc11SChristophe Ricard return -ETIME; 393*b75fdc11SChristophe Ricard } 394*b75fdc11SChristophe Ricard 395*b75fdc11SChristophe Ricard /* 396*b75fdc11SChristophe Ricard * st33zp24_spi_recv_data receive data 397*b75fdc11SChristophe Ricard * @param: chip, the tpm chip description 398*b75fdc11SChristophe Ricard * @param: buf, the buffer where the data are received 399*b75fdc11SChristophe Ricard * @param: count, the number of data to receive 400*b75fdc11SChristophe Ricard * @return: the number of bytes read from TPM FIFO. 401*b75fdc11SChristophe Ricard */ 402*b75fdc11SChristophe Ricard static int st33zp24_spi_recv_data(struct udevice *dev, u8 *buf, size_t count) 403*b75fdc11SChristophe Ricard { 404*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 405*b75fdc11SChristophe Ricard int size = 0, burstcnt, len, ret, status; 406*b75fdc11SChristophe Ricard 407*b75fdc11SChristophe Ricard while (size < count && 408*b75fdc11SChristophe Ricard st33zp24_spi_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, 409*b75fdc11SChristophe Ricard chip->timeout_c, &status) == 0) { 410*b75fdc11SChristophe Ricard burstcnt = st33zp24_spi_get_burstcount(dev); 411*b75fdc11SChristophe Ricard if (burstcnt < 0) 412*b75fdc11SChristophe Ricard return burstcnt; 413*b75fdc11SChristophe Ricard len = min_t(int, burstcnt, count - size); 414*b75fdc11SChristophe Ricard ret = st33zp24_spi_read(dev, TPM_DATA_FIFO, buf + size, len); 415*b75fdc11SChristophe Ricard if (ret < 0) 416*b75fdc11SChristophe Ricard return ret; 417*b75fdc11SChristophe Ricard 418*b75fdc11SChristophe Ricard size += len; 419*b75fdc11SChristophe Ricard } 420*b75fdc11SChristophe Ricard return size; 421*b75fdc11SChristophe Ricard } 422*b75fdc11SChristophe Ricard 423*b75fdc11SChristophe Ricard /* 424*b75fdc11SChristophe Ricard * st33zp24_spi_recv received TPM response through TPM phy. 425*b75fdc11SChristophe Ricard * @param: chip, tpm_chip description. 426*b75fdc11SChristophe Ricard * @param: buf, the buffer to store data. 427*b75fdc11SChristophe Ricard * @param: count, the number of bytes that can received (sizeof buf). 428*b75fdc11SChristophe Ricard * @return: Returns zero in case of success else -EIO. 429*b75fdc11SChristophe Ricard */ 430*b75fdc11SChristophe Ricard static int st33zp24_spi_recv(struct udevice *dev, u8 *buf, size_t count) 431*b75fdc11SChristophe Ricard { 432*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 433*b75fdc11SChristophe Ricard int size, expected; 434*b75fdc11SChristophe Ricard 435*b75fdc11SChristophe Ricard if (!chip) 436*b75fdc11SChristophe Ricard return -ENODEV; 437*b75fdc11SChristophe Ricard 438*b75fdc11SChristophe Ricard if (count < TPM_HEADER_SIZE) { 439*b75fdc11SChristophe Ricard size = -EIO; 440*b75fdc11SChristophe Ricard goto out; 441*b75fdc11SChristophe Ricard } 442*b75fdc11SChristophe Ricard 443*b75fdc11SChristophe Ricard size = st33zp24_spi_recv_data(dev, buf, TPM_HEADER_SIZE); 444*b75fdc11SChristophe Ricard if (size < TPM_HEADER_SIZE) { 445*b75fdc11SChristophe Ricard debug("TPM error, unable to read header\n"); 446*b75fdc11SChristophe Ricard goto out; 447*b75fdc11SChristophe Ricard } 448*b75fdc11SChristophe Ricard 449*b75fdc11SChristophe Ricard expected = get_unaligned_be32(buf + 2); 450*b75fdc11SChristophe Ricard if (expected > count) { 451*b75fdc11SChristophe Ricard size = -EIO; 452*b75fdc11SChristophe Ricard goto out; 453*b75fdc11SChristophe Ricard } 454*b75fdc11SChristophe Ricard 455*b75fdc11SChristophe Ricard size += st33zp24_spi_recv_data(dev, &buf[TPM_HEADER_SIZE], 456*b75fdc11SChristophe Ricard expected - TPM_HEADER_SIZE); 457*b75fdc11SChristophe Ricard if (size < expected) { 458*b75fdc11SChristophe Ricard debug("TPM error, unable to read remaining bytes of result\n"); 459*b75fdc11SChristophe Ricard size = -EIO; 460*b75fdc11SChristophe Ricard goto out; 461*b75fdc11SChristophe Ricard } 462*b75fdc11SChristophe Ricard 463*b75fdc11SChristophe Ricard out: 464*b75fdc11SChristophe Ricard st33zp24_spi_cancel(dev); 465*b75fdc11SChristophe Ricard st33zp24_spi_release_locality(dev); 466*b75fdc11SChristophe Ricard 467*b75fdc11SChristophe Ricard return size; 468*b75fdc11SChristophe Ricard } 469*b75fdc11SChristophe Ricard 470*b75fdc11SChristophe Ricard /* 471*b75fdc11SChristophe Ricard * st33zp24_spi_send send TPM commands through TPM phy. 472*b75fdc11SChristophe Ricard * @param: chip, tpm_chip description. 473*b75fdc11SChristophe Ricard * @param: buf, the buffer to send. 474*b75fdc11SChristophe Ricard * @param: len, the number of bytes to send. 475*b75fdc11SChristophe Ricard * @return: Returns zero in case of success else the negative error code. 476*b75fdc11SChristophe Ricard */ 477*b75fdc11SChristophe Ricard static int st33zp24_spi_send(struct udevice *dev, const u8 *buf, size_t len) 478*b75fdc11SChristophe Ricard { 479*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 480*b75fdc11SChristophe Ricard u32 i, size; 481*b75fdc11SChristophe Ricard int burstcnt, ret, status; 482*b75fdc11SChristophe Ricard u8 data, tpm_stat; 483*b75fdc11SChristophe Ricard 484*b75fdc11SChristophe Ricard if (!chip) 485*b75fdc11SChristophe Ricard return -ENODEV; 486*b75fdc11SChristophe Ricard if (len < TPM_HEADER_SIZE) 487*b75fdc11SChristophe Ricard return -EIO; 488*b75fdc11SChristophe Ricard 489*b75fdc11SChristophe Ricard ret = st33zp24_spi_request_locality(dev); 490*b75fdc11SChristophe Ricard if (ret < 0) 491*b75fdc11SChristophe Ricard return ret; 492*b75fdc11SChristophe Ricard 493*b75fdc11SChristophe Ricard tpm_stat = st33zp24_spi_status(dev); 494*b75fdc11SChristophe Ricard if ((tpm_stat & TPM_STS_COMMAND_READY) == 0) { 495*b75fdc11SChristophe Ricard st33zp24_spi_cancel(dev); 496*b75fdc11SChristophe Ricard if (st33zp24_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY, 497*b75fdc11SChristophe Ricard chip->timeout_b, &status) < 0) { 498*b75fdc11SChristophe Ricard ret = -ETIME; 499*b75fdc11SChristophe Ricard goto out_err; 500*b75fdc11SChristophe Ricard } 501*b75fdc11SChristophe Ricard } 502*b75fdc11SChristophe Ricard 503*b75fdc11SChristophe Ricard for (i = 0; i < len - 1;) { 504*b75fdc11SChristophe Ricard burstcnt = st33zp24_spi_get_burstcount(dev); 505*b75fdc11SChristophe Ricard if (burstcnt < 0) 506*b75fdc11SChristophe Ricard return burstcnt; 507*b75fdc11SChristophe Ricard 508*b75fdc11SChristophe Ricard size = min_t(int, len - i - 1, burstcnt); 509*b75fdc11SChristophe Ricard ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + i, size); 510*b75fdc11SChristophe Ricard if (ret < 0) 511*b75fdc11SChristophe Ricard goto out_err; 512*b75fdc11SChristophe Ricard 513*b75fdc11SChristophe Ricard i += size; 514*b75fdc11SChristophe Ricard } 515*b75fdc11SChristophe Ricard 516*b75fdc11SChristophe Ricard tpm_stat = st33zp24_spi_status(dev); 517*b75fdc11SChristophe Ricard if ((tpm_stat & TPM_STS_DATA_EXPECT) == 0) { 518*b75fdc11SChristophe Ricard ret = -EIO; 519*b75fdc11SChristophe Ricard goto out_err; 520*b75fdc11SChristophe Ricard } 521*b75fdc11SChristophe Ricard 522*b75fdc11SChristophe Ricard ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + len - 1, 1); 523*b75fdc11SChristophe Ricard if (ret < 0) 524*b75fdc11SChristophe Ricard goto out_err; 525*b75fdc11SChristophe Ricard 526*b75fdc11SChristophe Ricard tpm_stat = st33zp24_spi_status(dev); 527*b75fdc11SChristophe Ricard if ((tpm_stat & TPM_STS_DATA_EXPECT) != 0) { 528*b75fdc11SChristophe Ricard ret = -EIO; 529*b75fdc11SChristophe Ricard goto out_err; 530*b75fdc11SChristophe Ricard } 531*b75fdc11SChristophe Ricard 532*b75fdc11SChristophe Ricard data = TPM_STS_GO; 533*b75fdc11SChristophe Ricard ret = st33zp24_spi_write(dev, TPM_STS, &data, 1); 534*b75fdc11SChristophe Ricard if (ret < 0) 535*b75fdc11SChristophe Ricard goto out_err; 536*b75fdc11SChristophe Ricard 537*b75fdc11SChristophe Ricard return len; 538*b75fdc11SChristophe Ricard 539*b75fdc11SChristophe Ricard out_err: 540*b75fdc11SChristophe Ricard st33zp24_spi_cancel(dev); 541*b75fdc11SChristophe Ricard st33zp24_spi_release_locality(dev); 542*b75fdc11SChristophe Ricard 543*b75fdc11SChristophe Ricard return ret; 544*b75fdc11SChristophe Ricard } 545*b75fdc11SChristophe Ricard 546*b75fdc11SChristophe Ricard static int st33zp24_spi_cleanup(struct udevice *dev) 547*b75fdc11SChristophe Ricard { 548*b75fdc11SChristophe Ricard st33zp24_spi_cancel(dev); 549*b75fdc11SChristophe Ricard /* 550*b75fdc11SChristophe Ricard * The TPM needs some time to clean up here, 551*b75fdc11SChristophe Ricard * so we sleep rather than keeping the bus busy 552*b75fdc11SChristophe Ricard */ 553*b75fdc11SChristophe Ricard mdelay(2); 554*b75fdc11SChristophe Ricard st33zp24_spi_release_locality(dev); 555*b75fdc11SChristophe Ricard 556*b75fdc11SChristophe Ricard return 0; 557*b75fdc11SChristophe Ricard } 558*b75fdc11SChristophe Ricard 559*b75fdc11SChristophe Ricard static int st33zp24_spi_init(struct udevice *dev) 560*b75fdc11SChristophe Ricard { 561*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 562*b75fdc11SChristophe Ricard struct st33zp24_spi_phy *phy = dev_get_platdata(dev); 563*b75fdc11SChristophe Ricard 564*b75fdc11SChristophe Ricard chip->is_open = 1; 565*b75fdc11SChristophe Ricard 566*b75fdc11SChristophe Ricard /* Default timeouts - these could move to the device tree */ 567*b75fdc11SChristophe Ricard chip->timeout_a = TIS_SHORT_TIMEOUT_MS; 568*b75fdc11SChristophe Ricard chip->timeout_b = TIS_LONG_TIMEOUT_MS; 569*b75fdc11SChristophe Ricard chip->timeout_c = TIS_SHORT_TIMEOUT_MS; 570*b75fdc11SChristophe Ricard chip->timeout_d = TIS_SHORT_TIMEOUT_MS; 571*b75fdc11SChristophe Ricard 572*b75fdc11SChristophe Ricard chip->locality = LOCALITY0; 573*b75fdc11SChristophe Ricard 574*b75fdc11SChristophe Ricard phy->latency = st33zp24_spi_evaluate_latency(dev); 575*b75fdc11SChristophe Ricard if (phy->latency <= 0) 576*b75fdc11SChristophe Ricard return -ENODEV; 577*b75fdc11SChristophe Ricard 578*b75fdc11SChristophe Ricard /* 579*b75fdc11SChristophe Ricard * A timeout query to TPM can be placed here. 580*b75fdc11SChristophe Ricard * Standard timeout values are used so far 581*b75fdc11SChristophe Ricard */ 582*b75fdc11SChristophe Ricard 583*b75fdc11SChristophe Ricard return 0; 584*b75fdc11SChristophe Ricard } 585*b75fdc11SChristophe Ricard 586*b75fdc11SChristophe Ricard static int st33zp24_spi_open(struct udevice *dev) 587*b75fdc11SChristophe Ricard { 588*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 589*b75fdc11SChristophe Ricard int rc; 590*b75fdc11SChristophe Ricard 591*b75fdc11SChristophe Ricard debug("%s: start\n", __func__); 592*b75fdc11SChristophe Ricard if (chip->is_open) 593*b75fdc11SChristophe Ricard return -EBUSY; 594*b75fdc11SChristophe Ricard 595*b75fdc11SChristophe Ricard rc = st33zp24_spi_init(dev); 596*b75fdc11SChristophe Ricard if (rc < 0) 597*b75fdc11SChristophe Ricard chip->is_open = 0; 598*b75fdc11SChristophe Ricard 599*b75fdc11SChristophe Ricard return rc; 600*b75fdc11SChristophe Ricard } 601*b75fdc11SChristophe Ricard 602*b75fdc11SChristophe Ricard static int st33zp24_spi_close(struct udevice *dev) 603*b75fdc11SChristophe Ricard { 604*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 605*b75fdc11SChristophe Ricard 606*b75fdc11SChristophe Ricard if (chip->is_open) { 607*b75fdc11SChristophe Ricard st33zp24_spi_release_locality(dev); 608*b75fdc11SChristophe Ricard chip->is_open = 0; 609*b75fdc11SChristophe Ricard chip->vend_dev = 0; 610*b75fdc11SChristophe Ricard } 611*b75fdc11SChristophe Ricard 612*b75fdc11SChristophe Ricard return 0; 613*b75fdc11SChristophe Ricard } 614*b75fdc11SChristophe Ricard 615*b75fdc11SChristophe Ricard static int st33zp24_spi_get_desc(struct udevice *dev, char *buf, int size) 616*b75fdc11SChristophe Ricard { 617*b75fdc11SChristophe Ricard struct tpm_chip *chip = dev_get_priv(dev); 618*b75fdc11SChristophe Ricard 619*b75fdc11SChristophe Ricard if (size < 50) 620*b75fdc11SChristophe Ricard return -ENOSPC; 621*b75fdc11SChristophe Ricard 622*b75fdc11SChristophe Ricard return snprintf(buf, size, "1.2 TPM (%s, chip type %s device-id 0x%x)", 623*b75fdc11SChristophe Ricard chip->is_open ? "open" : "closed", 624*b75fdc11SChristophe Ricard dev->name, 625*b75fdc11SChristophe Ricard chip->vend_dev >> 16); 626*b75fdc11SChristophe Ricard } 627*b75fdc11SChristophe Ricard 628*b75fdc11SChristophe Ricard const struct tpm_ops st33zp24_spi_tpm_ops = { 629*b75fdc11SChristophe Ricard .open = st33zp24_spi_open, 630*b75fdc11SChristophe Ricard .close = st33zp24_spi_close, 631*b75fdc11SChristophe Ricard .recv = st33zp24_spi_recv, 632*b75fdc11SChristophe Ricard .send = st33zp24_spi_send, 633*b75fdc11SChristophe Ricard .cleanup = st33zp24_spi_cleanup, 634*b75fdc11SChristophe Ricard .get_desc = st33zp24_spi_get_desc, 635*b75fdc11SChristophe Ricard }; 636*b75fdc11SChristophe Ricard 637*b75fdc11SChristophe Ricard static int st33zp24_spi_probe(struct udevice *dev) 638*b75fdc11SChristophe Ricard { 639*b75fdc11SChristophe Ricard struct tpm_chip_priv *uc_priv = dev_get_uclass_priv(dev); 640*b75fdc11SChristophe Ricard 641*b75fdc11SChristophe Ricard uc_priv->duration_ms[TPM_SHORT] = TIS_SHORT_TIMEOUT_MS; 642*b75fdc11SChristophe Ricard uc_priv->duration_ms[TPM_MEDIUM] = TIS_LONG_TIMEOUT_MS; 643*b75fdc11SChristophe Ricard uc_priv->duration_ms[TPM_LONG] = TIS_LONG_TIMEOUT_MS; 644*b75fdc11SChristophe Ricard uc_priv->retry_time_ms = TPM_TIMEOUT_MS; 645*b75fdc11SChristophe Ricard 646*b75fdc11SChristophe Ricard debug("ST33ZP24 SPI TPM from STMicroelectronics found\n"); 647*b75fdc11SChristophe Ricard 648*b75fdc11SChristophe Ricard return 0; 649*b75fdc11SChristophe Ricard } 650*b75fdc11SChristophe Ricard 651*b75fdc11SChristophe Ricard static int st33zp24_spi_remove(struct udevice *dev) 652*b75fdc11SChristophe Ricard { 653*b75fdc11SChristophe Ricard st33zp24_spi_release_locality(dev); 654*b75fdc11SChristophe Ricard 655*b75fdc11SChristophe Ricard return 0; 656*b75fdc11SChristophe Ricard } 657*b75fdc11SChristophe Ricard 658*b75fdc11SChristophe Ricard static const struct udevice_id st33zp24_spi_ids[] = { 659*b75fdc11SChristophe Ricard { .compatible = "st,st33zp24-spi" }, 660*b75fdc11SChristophe Ricard { } 661*b75fdc11SChristophe Ricard }; 662*b75fdc11SChristophe Ricard 663*b75fdc11SChristophe Ricard U_BOOT_DRIVER(st33zp24_spi_spi) = { 664*b75fdc11SChristophe Ricard .name = "st33zp24-spi", 665*b75fdc11SChristophe Ricard .id = UCLASS_TPM, 666*b75fdc11SChristophe Ricard .of_match = of_match_ptr(st33zp24_spi_ids), 667*b75fdc11SChristophe Ricard .probe = st33zp24_spi_probe, 668*b75fdc11SChristophe Ricard .remove = st33zp24_spi_remove, 669*b75fdc11SChristophe Ricard .ops = &st33zp24_spi_tpm_ops, 670*b75fdc11SChristophe Ricard .priv_auto_alloc_size = sizeof(struct tpm_chip), 671*b75fdc11SChristophe Ricard .platdata_auto_alloc_size = sizeof(struct st33zp24_spi_phy), 672*b75fdc11SChristophe Ricard }; 673