1 /* 2 * SH QSPI (Quad SPI) driver 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <asm/io.h> 14 15 /* SH QSPI register bit masks <REG>_<BIT> */ 16 #define SPCR_MSTR 0x08 17 #define SPCR_SPE 0x40 18 #define SPSR_SPRFF 0x80 19 #define SPSR_SPTEF 0x20 20 #define SPPCR_IO3FV 0x04 21 #define SPPCR_IO2FV 0x02 22 #define SPPCR_IO1FV 0x01 23 #define SPBDCR_RXBC0 (1 << 0) 24 #define SPCMD_SCKDEN (1 << 15) 25 #define SPCMD_SLNDEN (1 << 14) 26 #define SPCMD_SPNDEN (1 << 13) 27 #define SPCMD_SSLKP (1 << 7) 28 #define SPCMD_BRDV0 (1 << 2) 29 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ 30 SPCMD_SPNDEN | SPCMD_SSLKP | \ 31 SPCMD_BRDV0 32 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ 33 SPCMD_BRDV0 34 #define SPBFCR_TXRST (1 << 7) 35 #define SPBFCR_RXRST (1 << 6) 36 37 /* SH QSPI register set */ 38 struct sh_qspi_regs { 39 unsigned char spcr; 40 unsigned char sslp; 41 unsigned char sppcr; 42 unsigned char spsr; 43 unsigned long spdr; 44 unsigned char spscr; 45 unsigned char spssr; 46 unsigned char spbr; 47 unsigned char spdcr; 48 unsigned char spckd; 49 unsigned char sslnd; 50 unsigned char spnd; 51 unsigned char dummy0; 52 unsigned short spcmd0; 53 unsigned short spcmd1; 54 unsigned short spcmd2; 55 unsigned short spcmd3; 56 unsigned char spbfcr; 57 unsigned char dummy1; 58 unsigned short spbdcr; 59 unsigned long spbmul0; 60 unsigned long spbmul1; 61 unsigned long spbmul2; 62 unsigned long spbmul3; 63 }; 64 65 struct sh_qspi_slave { 66 struct spi_slave slave; 67 struct sh_qspi_regs *regs; 68 }; 69 70 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) 71 { 72 return container_of(slave, struct sh_qspi_slave, slave); 73 } 74 75 static void sh_qspi_init(struct sh_qspi_slave *ss) 76 { 77 /* QSPI initialize */ 78 /* Set master mode only */ 79 writeb(SPCR_MSTR, &ss->regs->spcr); 80 81 /* Set SSL signal level */ 82 writeb(0x00, &ss->regs->sslp); 83 84 /* Set MOSI signal value when transfer is in idle state */ 85 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); 86 87 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ 88 writeb(0x01, &ss->regs->spbr); 89 90 /* Disable Dummy Data Transmission */ 91 writeb(0x00, &ss->regs->spdcr); 92 93 /* Set clock delay value */ 94 writeb(0x00, &ss->regs->spckd); 95 96 /* Set SSL negation delay value */ 97 writeb(0x00, &ss->regs->sslnd); 98 99 /* Set next-access delay value */ 100 writeb(0x00, &ss->regs->spnd); 101 102 /* Set equence command */ 103 writew(SPCMD_INIT2, &ss->regs->spcmd0); 104 105 /* Reset transfer and receive Buffer */ 106 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 107 108 /* Clear transfer and receive Buffer control bit */ 109 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 110 111 /* Set equence control method. Use equence0 only */ 112 writeb(0x00, &ss->regs->spscr); 113 114 /* Enable SPI function */ 115 setbits_8(&ss->regs->spcr, SPCR_SPE); 116 } 117 118 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 119 { 120 return 1; 121 } 122 123 void spi_cs_activate(struct spi_slave *slave) 124 { 125 struct sh_qspi_slave *ss = to_sh_qspi(slave); 126 127 /* Set master mode only */ 128 writeb(SPCR_MSTR, &ss->regs->spcr); 129 130 /* Set command */ 131 writew(SPCMD_INIT1, &ss->regs->spcmd0); 132 133 /* Reset transfer and receive Buffer */ 134 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 135 136 /* Clear transfer and receive Buffer control bit */ 137 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); 138 139 /* Set equence control method. Use equence0 only */ 140 writeb(0x00, &ss->regs->spscr); 141 142 /* Enable SPI function */ 143 setbits_8(&ss->regs->spcr, SPCR_SPE); 144 } 145 146 void spi_cs_deactivate(struct spi_slave *slave) 147 { 148 struct sh_qspi_slave *ss = to_sh_qspi(slave); 149 150 /* Disable SPI Function */ 151 clrbits_8(&ss->regs->spcr, SPCR_SPE); 152 } 153 154 void spi_init(void) 155 { 156 /* nothing to do */ 157 } 158 159 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 160 unsigned int max_hz, unsigned int mode) 161 { 162 struct sh_qspi_slave *ss; 163 164 if (!spi_cs_is_valid(bus, cs)) 165 return NULL; 166 167 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); 168 if (!ss) { 169 printf("SPI_error: Fail to allocate sh_qspi_slave\n"); 170 return NULL; 171 } 172 173 ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE; 174 175 /* Init SH QSPI */ 176 sh_qspi_init(ss); 177 178 return &ss->slave; 179 } 180 181 void spi_free_slave(struct spi_slave *slave) 182 { 183 struct sh_qspi_slave *spi = to_sh_qspi(slave); 184 185 free(spi); 186 } 187 188 int spi_claim_bus(struct spi_slave *slave) 189 { 190 return 0; 191 } 192 193 void spi_release_bus(struct spi_slave *slave) 194 { 195 } 196 197 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 198 void *din, unsigned long flags) 199 { 200 struct sh_qspi_slave *ss = to_sh_qspi(slave); 201 unsigned long nbyte; 202 int ret = 0; 203 unsigned char dtdata = 0, drdata; 204 unsigned char *tdata = &dtdata, *rdata = &drdata; 205 unsigned long *spbmul0 = &ss->regs->spbmul0; 206 207 if (dout == NULL && din == NULL) { 208 if (flags & SPI_XFER_END) 209 spi_cs_deactivate(slave); 210 return 0; 211 } 212 213 if (bitlen % 8) { 214 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); 215 return 1; 216 } 217 218 nbyte = bitlen / 8; 219 220 if (flags & SPI_XFER_BEGIN) { 221 spi_cs_activate(slave); 222 223 /* Set 1048576 byte */ 224 writel(0x100000, spbmul0); 225 } 226 227 if (flags & SPI_XFER_END) 228 writel(nbyte, spbmul0); 229 230 if (dout != NULL) 231 tdata = (unsigned char *)dout; 232 233 if (din != NULL) 234 rdata = din; 235 236 while (nbyte > 0) { 237 while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { 238 if (ctrlc()) { 239 puts("abort\n"); 240 return 1; 241 } 242 udelay(10); 243 } 244 245 writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); 246 247 while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { 248 if (ctrlc()) { 249 puts("abort\n"); 250 return 1; 251 } 252 udelay(1); 253 } 254 255 while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { 256 if (ctrlc()) { 257 puts("abort\n"); 258 return 1; 259 } 260 udelay(10); 261 } 262 263 *rdata = readb((unsigned char *)(&ss->regs->spdr)); 264 265 if (dout != NULL) 266 tdata++; 267 if (din != NULL) 268 rdata++; 269 270 nbyte--; 271 } 272 273 if (flags & SPI_XFER_END) 274 spi_cs_deactivate(slave); 275 276 return ret; 277 } 278