1 /* 2 * Freescale i.MX28 SPI driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * NOTE: This driver only supports the SPI-controller chipselects, 23 * GPIO driven chipselects are not supported. 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <spi.h> 29 #include <asm/errno.h> 30 #include <asm/io.h> 31 #include <asm/arch/clock.h> 32 #include <asm/arch/imx-regs.h> 33 #include <asm/arch/sys_proto.h> 34 #include <asm/arch/dma.h> 35 36 #define MXS_SPI_MAX_TIMEOUT 1000000 37 #define MXS_SPI_PORT_OFFSET 0x2000 38 #define MXS_SSP_CHIPSELECT_MASK 0x00300000 39 #define MXS_SSP_CHIPSELECT_SHIFT 20 40 41 #define MXSSSP_SMALL_TRANSFER 512 42 43 /* 44 * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI 45 * host. Use with utmost caution! 46 * 47 * Enabling this is not yet recommended since this 48 * still doesn't support transfers to/from unaligned 49 * addresses. Therefore this driver will not work 50 * for example with saving environment. This is 51 * caused by DMA alignment constraints on MXS. 52 */ 53 54 struct mxs_spi_slave { 55 struct spi_slave slave; 56 uint32_t max_khz; 57 uint32_t mode; 58 struct mxs_ssp_regs *regs; 59 }; 60 61 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) 62 { 63 return container_of(slave, struct mxs_spi_slave, slave); 64 } 65 66 void spi_init(void) 67 { 68 } 69 70 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 71 { 72 /* MXS SPI: 4 ports and 3 chip selects maximum */ 73 if (!mxs_ssp_bus_id_valid(bus) || cs > 2) 74 return 0; 75 else 76 return 1; 77 } 78 79 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 80 unsigned int max_hz, unsigned int mode) 81 { 82 struct mxs_spi_slave *mxs_slave; 83 struct mxs_ssp_regs *ssp_regs; 84 int reg; 85 86 if (!spi_cs_is_valid(bus, cs)) { 87 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); 88 return NULL; 89 } 90 91 mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1); 92 if (!mxs_slave) 93 return NULL; 94 95 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) 96 goto err_init; 97 98 mxs_slave->slave.bus = bus; 99 mxs_slave->slave.cs = cs; 100 mxs_slave->max_khz = max_hz / 1000; 101 mxs_slave->mode = mode; 102 mxs_slave->regs = mxs_ssp_regs_by_bus(bus); 103 ssp_regs = mxs_slave->regs; 104 105 reg = readl(&ssp_regs->hw_ssp_ctrl0); 106 reg &= ~(MXS_SSP_CHIPSELECT_MASK); 107 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; 108 109 writel(reg, &ssp_regs->hw_ssp_ctrl0); 110 return &mxs_slave->slave; 111 112 err_init: 113 free(mxs_slave); 114 return NULL; 115 } 116 117 void spi_free_slave(struct spi_slave *slave) 118 { 119 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 120 free(mxs_slave); 121 } 122 123 int spi_claim_bus(struct spi_slave *slave) 124 { 125 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 126 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 127 uint32_t reg = 0; 128 129 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 130 131 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); 132 133 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; 134 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; 135 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; 136 writel(reg, &ssp_regs->hw_ssp_ctrl1); 137 138 writel(0, &ssp_regs->hw_ssp_cmd0); 139 140 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz); 141 142 return 0; 143 } 144 145 void spi_release_bus(struct spi_slave *slave) 146 { 147 } 148 149 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) 150 { 151 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); 152 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); 153 } 154 155 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) 156 { 157 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); 158 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); 159 } 160 161 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, 162 char *data, int length, int write, unsigned long flags) 163 { 164 struct mxs_ssp_regs *ssp_regs = slave->regs; 165 166 if (flags & SPI_XFER_BEGIN) 167 mxs_spi_start_xfer(ssp_regs); 168 169 while (length--) { 170 /* We transfer 1 byte */ 171 #if defined(CONFIG_MX23) 172 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); 173 writel(1, &ssp_regs->hw_ssp_ctrl0_set); 174 #elif defined(CONFIG_MX28) 175 writel(1, &ssp_regs->hw_ssp_xfer_size); 176 #endif 177 178 if ((flags & SPI_XFER_END) && !length) 179 mxs_spi_end_xfer(ssp_regs); 180 181 if (write) 182 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr); 183 else 184 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set); 185 186 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set); 187 188 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, 189 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 190 printf("MXS SPI: Timeout waiting for start\n"); 191 return -ETIMEDOUT; 192 } 193 194 if (write) 195 writel(*data++, &ssp_regs->hw_ssp_data); 196 197 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); 198 199 if (!write) { 200 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, 201 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { 202 printf("MXS SPI: Timeout waiting for data\n"); 203 return -ETIMEDOUT; 204 } 205 206 *data = readl(&ssp_regs->hw_ssp_data); 207 data++; 208 } 209 210 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, 211 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { 212 printf("MXS SPI: Timeout waiting for finish\n"); 213 return -ETIMEDOUT; 214 } 215 } 216 217 return 0; 218 } 219 220 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, 221 char *data, int length, int write, unsigned long flags) 222 { 223 const int xfer_max_sz = 0xff00; 224 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; 225 struct mxs_ssp_regs *ssp_regs = slave->regs; 226 struct mxs_dma_desc *dp; 227 uint32_t ctrl0; 228 uint32_t cache_data_count; 229 const uint32_t dstart = (uint32_t)data; 230 int dmach; 231 int tl; 232 int ret = 0; 233 234 #if defined(CONFIG_MX23) 235 const int mxs_spi_pio_words = 1; 236 #elif defined(CONFIG_MX28) 237 const int mxs_spi_pio_words = 4; 238 #endif 239 240 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); 241 242 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count); 243 244 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0); 245 ctrl0 |= SSP_CTRL0_DATA_XFER; 246 247 if (flags & SPI_XFER_BEGIN) 248 ctrl0 |= SSP_CTRL0_LOCK_CS; 249 if (!write) 250 ctrl0 |= SSP_CTRL0_READ; 251 252 if (length % ARCH_DMA_MINALIGN) 253 cache_data_count = roundup(length, ARCH_DMA_MINALIGN); 254 else 255 cache_data_count = length; 256 257 /* Flush data to DRAM so DMA can pick them up */ 258 if (write) 259 flush_dcache_range(dstart, dstart + cache_data_count); 260 261 /* Invalidate the area, so no writeback into the RAM races with DMA */ 262 invalidate_dcache_range(dstart, dstart + cache_data_count); 263 264 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; 265 266 dp = desc; 267 while (length) { 268 dp->address = (dma_addr_t)dp; 269 dp->cmd.address = (dma_addr_t)data; 270 271 /* 272 * This is correct, even though it does indeed look insane. 273 * I hereby have to, wholeheartedly, thank Freescale Inc., 274 * for always inventing insane hardware and keeping me busy 275 * and employed ;-) 276 */ 277 if (write) 278 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 279 else 280 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 281 282 /* 283 * The DMA controller can transfer large chunks (64kB) at 284 * time by setting the transfer length to 0. Setting tl to 285 * 0x10000 will overflow below and make .data contain 0. 286 * Otherwise, 0xff00 is the transfer maximum. 287 */ 288 if (length >= 0x10000) 289 tl = 0x10000; 290 else 291 tl = min(length, xfer_max_sz); 292 293 dp->cmd.data |= 294 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | 295 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 296 MXS_DMA_DESC_HALT_ON_TERMINATE | 297 MXS_DMA_DESC_TERMINATE_FLUSH; 298 299 data += tl; 300 length -= tl; 301 302 if (!length) { 303 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; 304 305 if (flags & SPI_XFER_END) { 306 ctrl0 &= ~SSP_CTRL0_LOCK_CS; 307 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 308 } 309 } 310 311 /* 312 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in 313 * case of MX28, write only CTRL0 in case of MX23 due 314 * to the difference in register layout. It is utterly 315 * essential that the XFER_SIZE register is written on 316 * a per-descriptor basis with the same size as is the 317 * descriptor! 318 */ 319 dp->cmd.pio_words[0] = ctrl0; 320 #ifdef CONFIG_MX28 321 dp->cmd.pio_words[1] = 0; 322 dp->cmd.pio_words[2] = 0; 323 dp->cmd.pio_words[3] = tl; 324 #endif 325 326 mxs_dma_desc_append(dmach, dp); 327 328 dp++; 329 } 330 331 if (mxs_dma_go(dmach)) 332 ret = -EINVAL; 333 334 /* The data arrived into DRAM, invalidate cache over them */ 335 if (!write) 336 invalidate_dcache_range(dstart, dstart + cache_data_count); 337 338 return ret; 339 } 340 341 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 342 const void *dout, void *din, unsigned long flags) 343 { 344 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); 345 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; 346 int len = bitlen / 8; 347 char dummy; 348 int write = 0; 349 char *data = NULL; 350 351 #ifdef CONFIG_MXS_SPI_DMA_ENABLE 352 int dma = 1; 353 #else 354 int dma = 0; 355 #endif 356 357 if (bitlen == 0) { 358 if (flags & SPI_XFER_END) { 359 din = (void *)&dummy; 360 len = 1; 361 } else 362 return 0; 363 } 364 365 /* Half-duplex only */ 366 if (din && dout) 367 return -EINVAL; 368 /* No data */ 369 if (!din && !dout) 370 return 0; 371 372 if (dout) { 373 data = (char *)dout; 374 write = 1; 375 } else if (din) { 376 data = (char *)din; 377 write = 0; 378 } 379 380 /* 381 * Check for alignment, if the buffer is aligned, do DMA transfer, 382 * PIO otherwise. This is a temporary workaround until proper bounce 383 * buffer is in place. 384 */ 385 if (dma) { 386 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1)) 387 dma = 0; 388 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1)) 389 dma = 0; 390 } 391 392 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { 393 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 394 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); 395 } else { 396 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 397 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); 398 } 399 } 400