1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <mxc_gpio.h> 27 28 #ifdef CONFIG_MX27 29 /* i.MX27 has a completely wrong register layout and register definitions in the 30 * datasheet, the correct one is in the Freescale's Linux driver */ 31 32 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ 33 "See linux mxc_spi driver from Freescale for details." 34 35 #elif defined(CONFIG_MX31) 36 37 #include <asm/arch/mx31.h> 38 39 #define MXC_CSPIRXDATA 0x00 40 #define MXC_CSPITXDATA 0x04 41 #define MXC_CSPICTRL 0x08 42 #define MXC_CSPIINT 0x0C 43 #define MXC_CSPIDMA 0x10 44 #define MXC_CSPISTAT 0x14 45 #define MXC_CSPIPERIOD 0x18 46 #define MXC_CSPITEST 0x1C 47 #define MXC_CSPIRESET 0x00 48 49 #define MXC_CSPICTRL_EN (1 << 0) 50 #define MXC_CSPICTRL_MODE (1 << 1) 51 #define MXC_CSPICTRL_XCH (1 << 2) 52 #define MXC_CSPICTRL_SMC (1 << 3) 53 #define MXC_CSPICTRL_POL (1 << 4) 54 #define MXC_CSPICTRL_PHA (1 << 5) 55 #define MXC_CSPICTRL_SSCTL (1 << 6) 56 #define MXC_CSPICTRL_SSPOL (1 << 7) 57 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 58 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 59 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 60 #define MXC_CSPICTRL_TC (1 << 8) 61 #define MXC_CSPICTRL_RXOVF (1 << 6) 62 #define MXC_CSPICTRL_MAXBITS 0x1f 63 64 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 65 #define MAX_SPI_BYTES 4 66 67 static unsigned long spi_bases[] = { 68 0x43fa4000, 69 0x50010000, 70 0x53f84000, 71 }; 72 73 #elif defined(CONFIG_MX51) 74 #include <asm/arch/imx-regs.h> 75 #include <asm/arch/clock.h> 76 77 #define MXC_CSPIRXDATA 0x00 78 #define MXC_CSPITXDATA 0x04 79 #define MXC_CSPICTRL 0x08 80 #define MXC_CSPICON 0x0C 81 #define MXC_CSPIINT 0x10 82 #define MXC_CSPIDMA 0x14 83 #define MXC_CSPISTAT 0x18 84 #define MXC_CSPIPERIOD 0x1C 85 #define MXC_CSPIRESET 0x00 86 #define MXC_CSPICTRL_EN (1 << 0) 87 #define MXC_CSPICTRL_MODE (1 << 1) 88 #define MXC_CSPICTRL_XCH (1 << 2) 89 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 90 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 91 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 92 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 93 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 94 #define MXC_CSPICTRL_MAXBITS 0xfff 95 #define MXC_CSPICTRL_TC (1 << 7) 96 #define MXC_CSPICTRL_RXOVF (1 << 6) 97 98 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 99 #define MAX_SPI_BYTES 32 100 101 /* Bit position inside CTRL register to be associated with SS */ 102 #define MXC_CSPICTRL_CHAN 18 103 104 /* Bit position inside CON register to be associated with SS */ 105 #define MXC_CSPICON_POL 4 106 #define MXC_CSPICON_PHA 0 107 #define MXC_CSPICON_SSPOL 12 108 109 static unsigned long spi_bases[] = { 110 CSPI1_BASE_ADDR, 111 CSPI2_BASE_ADDR, 112 CSPI3_BASE_ADDR, 113 }; 114 #else 115 #error "Unsupported architecture" 116 #endif 117 118 #define OUT MXC_GPIO_DIRECTION_OUT 119 120 struct mxc_spi_slave { 121 struct spi_slave slave; 122 unsigned long base; 123 u32 ctrl_reg; 124 #if defined(CONFIG_MX51) 125 u32 cfg_reg; 126 #endif 127 int gpio; 128 int ss_pol; 129 }; 130 131 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 132 { 133 return container_of(slave, struct mxc_spi_slave, slave); 134 } 135 136 static inline u32 reg_read(unsigned long addr) 137 { 138 return *(volatile unsigned long*)addr; 139 } 140 141 static inline void reg_write(unsigned long addr, u32 val) 142 { 143 *(volatile unsigned long*)addr = val; 144 } 145 146 void spi_cs_activate(struct spi_slave *slave) 147 { 148 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 149 if (mxcs->gpio > 0) 150 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); 151 } 152 153 void spi_cs_deactivate(struct spi_slave *slave) 154 { 155 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 156 if (mxcs->gpio > 0) 157 mxc_gpio_set(mxcs->gpio, 158 !(mxcs->ss_pol)); 159 } 160 161 #ifdef CONFIG_MX51 162 static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, 163 unsigned int max_hz, unsigned int mode) 164 { 165 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 166 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 167 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 168 169 if (max_hz == 0) { 170 printf("Error: desired clock is 0\n"); 171 return -1; 172 } 173 174 reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); 175 176 /* Reset spi */ 177 reg_write(mxcs->base + MXC_CSPICTRL, 0); 178 reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); 179 180 /* 181 * The following computation is taken directly from Freescale's code. 182 */ 183 if (clk_src > max_hz) { 184 pre_div = clk_src / max_hz; 185 if (pre_div > 16) { 186 post_div = pre_div / 16; 187 pre_div = 15; 188 } 189 if (post_div != 0) { 190 for (i = 0; i < 16; i++) { 191 if ((1 << i) >= post_div) 192 break; 193 } 194 if (i == 16) { 195 printf("Error: no divider for the freq: %d\n", 196 max_hz); 197 return -1; 198 } 199 post_div = i; 200 } 201 } 202 203 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 204 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 205 MXC_CSPICTRL_SELCHAN(cs); 206 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 207 MXC_CSPICTRL_PREDIV(pre_div); 208 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 209 MXC_CSPICTRL_POSTDIV(post_div); 210 211 /* always set to master mode */ 212 reg_ctrl |= 1 << (cs + 4); 213 214 /* We need to disable SPI before changing registers */ 215 reg_ctrl &= ~MXC_CSPICTRL_EN; 216 217 if (mode & SPI_CS_HIGH) 218 ss_pol = 1; 219 220 if (mode & SPI_CPOL) 221 sclkpol = 1; 222 223 if (mode & SPI_CPHA) 224 sclkpha = 1; 225 226 reg_config = reg_read(mxcs->base + MXC_CSPICON); 227 228 /* 229 * Configuration register setup 230 * The MX51 has support different setup for each SS 231 */ 232 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 233 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 234 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 235 (sclkpol << (cs + MXC_CSPICON_POL)); 236 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 237 (sclkpha << (cs + MXC_CSPICON_PHA)); 238 239 debug("reg_ctrl = 0x%x\n", reg_ctrl); 240 reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); 241 debug("reg_config = 0x%x\n", reg_config); 242 reg_write(mxcs->base + MXC_CSPICON, reg_config); 243 244 /* save config register and control register */ 245 mxcs->ctrl_reg = reg_ctrl; 246 mxcs->cfg_reg = reg_config; 247 248 /* clear interrupt reg */ 249 reg_write(mxcs->base + MXC_CSPIINT, 0); 250 reg_write(mxcs->base + MXC_CSPISTAT, 251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 252 253 return 0; 254 } 255 #endif 256 257 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 258 const u8 *dout, u8 *din, unsigned long flags) 259 { 260 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 261 int nbytes = (bitlen + 7) / 8; 262 u32 data, cnt, i; 263 264 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 265 __func__, bitlen, (u32)dout, (u32)din); 266 267 mxcs->ctrl_reg = (mxcs->ctrl_reg & 268 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 269 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 270 271 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 272 #ifdef CONFIG_MX51 273 reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); 274 #endif 275 276 /* Clear interrupt register */ 277 reg_write(mxcs->base + MXC_CSPISTAT, 278 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 279 280 /* 281 * The SPI controller works only with words, 282 * check if less than a word is sent. 283 * Access to the FIFO is only 32 bit 284 */ 285 if (bitlen % 32) { 286 data = 0; 287 cnt = (bitlen % 32) / 8; 288 if (dout) { 289 for (i = 0; i < cnt; i++) { 290 data = (data << 8) | (*dout++ & 0xFF); 291 } 292 } 293 debug("Sending SPI 0x%x\n", data); 294 295 reg_write(mxcs->base + MXC_CSPITXDATA, data); 296 nbytes -= cnt; 297 } 298 299 data = 0; 300 301 while (nbytes > 0) { 302 data = 0; 303 if (dout) { 304 /* Buffer is not 32-bit aligned */ 305 if ((unsigned long)dout & 0x03) { 306 data = 0; 307 for (i = 0; i < 4; i++, data <<= 8) { 308 data = (data << 8) | (*dout++ & 0xFF); 309 } 310 } else { 311 data = *(u32 *)dout; 312 data = cpu_to_be32(data); 313 } 314 dout += 4; 315 } 316 debug("Sending SPI 0x%x\n", data); 317 reg_write(mxcs->base + MXC_CSPITXDATA, data); 318 nbytes -= 4; 319 } 320 321 /* FIFO is written, now starts the transfer setting the XCH bit */ 322 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | 323 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 324 325 /* Wait until the TC (Transfer completed) bit is set */ 326 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) 327 ; 328 329 /* Transfer completed, clear any pending request */ 330 reg_write(mxcs->base + MXC_CSPISTAT, 331 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 332 333 nbytes = (bitlen + 7) / 8; 334 335 cnt = nbytes % 32; 336 337 if (bitlen % 32) { 338 data = reg_read(mxcs->base + MXC_CSPIRXDATA); 339 cnt = (bitlen % 32) / 8; 340 debug("SPI Rx unaligned: 0x%x\n", data); 341 if (din) { 342 for (i = 0; i < cnt; i++, data >>= 8) { 343 *din++ = data & 0xFF; 344 } 345 } 346 nbytes -= cnt; 347 } 348 349 while (nbytes > 0) { 350 u32 tmp; 351 tmp = reg_read(mxcs->base + MXC_CSPIRXDATA); 352 data = cpu_to_be32(tmp); 353 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 354 cnt = min(nbytes, sizeof(data)); 355 if (din) { 356 memcpy(din, &data, cnt); 357 din += cnt; 358 } 359 nbytes -= cnt; 360 } 361 362 return 0; 363 364 } 365 366 367 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 368 void *din, unsigned long flags) 369 { 370 int n_bytes = (bitlen + 7) / 8; 371 int n_bits; 372 int ret; 373 u32 blk_size; 374 u8 *p_outbuf = (u8 *)dout; 375 u8 *p_inbuf = (u8 *)din; 376 377 if (!slave) 378 return -1; 379 380 if (flags & SPI_XFER_BEGIN) 381 spi_cs_activate(slave); 382 383 while (n_bytes > 0) { 384 385 if (n_bytes < MAX_SPI_BYTES) 386 blk_size = n_bytes; 387 else 388 blk_size = MAX_SPI_BYTES; 389 390 n_bits = blk_size * 8; 391 392 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 393 394 if (ret) 395 return ret; 396 if (dout) 397 p_outbuf += blk_size; 398 if (din) 399 p_inbuf += blk_size; 400 n_bytes -= blk_size; 401 } 402 403 if (flags & SPI_XFER_END) { 404 spi_cs_deactivate(slave); 405 } 406 407 return 0; 408 } 409 410 void spi_init(void) 411 { 412 } 413 414 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 415 { 416 int ret; 417 418 /* 419 * Some SPI devices require active chip-select over multiple 420 * transactions, we achieve this using a GPIO. Still, the SPI 421 * controller has to be configured to use one of its own chipselects. 422 * To use this feature you have to call spi_setup_slave() with 423 * cs = internal_cs | (gpio << 8), and you have to use some unused 424 * on this SPI controller cs between 0 and 3. 425 */ 426 if (cs > 3) { 427 mxcs->gpio = cs >> 8; 428 cs &= 3; 429 ret = mxc_gpio_direction(mxcs->gpio, OUT); 430 if (ret) { 431 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 432 return -EINVAL; 433 } 434 } else { 435 mxcs->gpio = -1; 436 } 437 438 return cs; 439 } 440 441 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 442 unsigned int max_hz, unsigned int mode) 443 { 444 unsigned int ctrl_reg; 445 struct mxc_spi_slave *mxcs; 446 int ret; 447 448 if (bus >= ARRAY_SIZE(spi_bases)) 449 return NULL; 450 451 mxcs = malloc(sizeof(struct mxc_spi_slave)); 452 if (!mxcs) { 453 puts("mxc_spi: SPI Slave not allocated !\n"); 454 return NULL; 455 } 456 457 ret = decode_cs(mxcs, cs); 458 if (ret < 0) { 459 free(mxcs); 460 return NULL; 461 } 462 463 cs = ret; 464 465 mxcs->slave.bus = bus; 466 mxcs->slave.cs = cs; 467 mxcs->base = spi_bases[bus]; 468 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 469 470 #ifdef CONFIG_MX51 471 /* Can be used for i.MX31 too ? */ 472 ctrl_reg = 0; 473 ret = spi_cfg(mxcs, cs, max_hz, mode); 474 if (ret) { 475 printf("mxc_spi: cannot setup SPI controller\n"); 476 free(mxcs); 477 return NULL; 478 } 479 #else 480 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 481 MXC_CSPICTRL_BITCOUNT(31) | 482 MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ 483 MXC_CSPICTRL_EN | 484 MXC_CSPICTRL_MODE; 485 486 if (mode & SPI_CPHA) 487 ctrl_reg |= MXC_CSPICTRL_PHA; 488 if (mode & SPI_CPOL) 489 ctrl_reg |= MXC_CSPICTRL_POL; 490 if (mode & SPI_CS_HIGH) 491 ctrl_reg |= MXC_CSPICTRL_SSPOL; 492 mxcs->ctrl_reg = ctrl_reg; 493 #endif 494 return &mxcs->slave; 495 } 496 497 void spi_free_slave(struct spi_slave *slave) 498 { 499 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 500 501 free(mxcs); 502 } 503 504 int spi_claim_bus(struct spi_slave *slave) 505 { 506 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 507 508 reg_write(mxcs->base + MXC_CSPIRESET, 1); 509 udelay(1); 510 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); 511 reg_write(mxcs->base + MXC_CSPIPERIOD, 512 MXC_CSPIPERIOD_32KHZ); 513 reg_write(mxcs->base + MXC_CSPIINT, 0); 514 515 return 0; 516 } 517 518 void spi_release_bus(struct spi_slave *slave) 519 { 520 /* TODO: Shut the controller down */ 521 } 522