1 /* 2 * Copyright (C) 2007 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <spi.h> 11 #include <malloc.h> 12 #include <wait_bit.h> 13 14 #include <asm/io.h> 15 16 #include <asm/arch/clk.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DM_SPI 19 #include <asm/arch/at91_spi.h> 20 #endif 21 #ifdef CONFIG_DM_GPIO 22 #include <asm/gpio.h> 23 #endif 24 25 #include "atmel_spi.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define MAX_CS_COUNT 4 30 31 struct atmel_spi_platdata { 32 struct at91_spi *regs; 33 }; 34 35 struct atmel_spi_priv { 36 unsigned int freq; /* Default frequency */ 37 unsigned int mode; 38 ulong bus_clk_rate; 39 #ifdef CONFIG_DM_GPIO 40 struct gpio_desc cs_gpios[MAX_CS_COUNT]; 41 #endif 42 }; 43 44 static int atmel_spi_claim_bus(struct udevice *dev) 45 { 46 struct udevice *bus = dev_get_parent(dev); 47 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 48 struct atmel_spi_priv *priv = dev_get_priv(bus); 49 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 50 struct at91_spi *reg_base = bus_plat->regs; 51 u32 cs = slave_plat->cs; 52 u32 freq = priv->freq; 53 u32 scbr, csrx, mode; 54 55 scbr = (priv->bus_clk_rate + freq - 1) / freq; 56 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) 57 return -EINVAL; 58 59 if (scbr < 1) 60 scbr = 1; 61 62 csrx = ATMEL_SPI_CSRx_SCBR(scbr); 63 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); 64 65 if (!(priv->mode & SPI_CPHA)) 66 csrx |= ATMEL_SPI_CSRx_NCPHA; 67 if (priv->mode & SPI_CPOL) 68 csrx |= ATMEL_SPI_CSRx_CPOL; 69 70 writel(csrx, ®_base->csr[cs]); 71 72 mode = ATMEL_SPI_MR_MSTR | 73 ATMEL_SPI_MR_MODFDIS | 74 ATMEL_SPI_MR_WDRBT | 75 ATMEL_SPI_MR_PCS(~(1 << cs)); 76 77 writel(mode, ®_base->mr); 78 79 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr); 80 81 return 0; 82 } 83 84 static int atmel_spi_release_bus(struct udevice *dev) 85 { 86 struct udevice *bus = dev_get_parent(dev); 87 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 88 89 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr); 90 91 return 0; 92 } 93 94 static void atmel_spi_cs_activate(struct udevice *dev) 95 { 96 #ifdef CONFIG_DM_GPIO 97 struct udevice *bus = dev_get_parent(dev); 98 struct atmel_spi_priv *priv = dev_get_priv(bus); 99 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 100 u32 cs = slave_plat->cs; 101 102 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 103 return; 104 105 dm_gpio_set_value(&priv->cs_gpios[cs], 0); 106 #endif 107 } 108 109 static void atmel_spi_cs_deactivate(struct udevice *dev) 110 { 111 #ifdef CONFIG_DM_GPIO 112 struct udevice *bus = dev_get_parent(dev); 113 struct atmel_spi_priv *priv = dev_get_priv(bus); 114 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 115 u32 cs = slave_plat->cs; 116 117 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 118 return; 119 120 dm_gpio_set_value(&priv->cs_gpios[cs], 1); 121 #endif 122 } 123 124 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen, 125 const void *dout, void *din, unsigned long flags) 126 { 127 struct udevice *bus = dev_get_parent(dev); 128 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 129 struct at91_spi *reg_base = bus_plat->regs; 130 131 u32 len_tx, len_rx, len; 132 u32 status; 133 const u8 *txp = dout; 134 u8 *rxp = din; 135 u8 value; 136 137 if (bitlen == 0) 138 goto out; 139 140 /* 141 * The controller can do non-multiple-of-8 bit 142 * transfers, but this driver currently doesn't support it. 143 * 144 * It's also not clear how such transfers are supposed to be 145 * represented as a stream of bytes...this is a limitation of 146 * the current SPI interface. 147 */ 148 if (bitlen % 8) { 149 /* Errors always terminate an ongoing transfer */ 150 flags |= SPI_XFER_END; 151 goto out; 152 } 153 154 len = bitlen / 8; 155 156 /* 157 * The controller can do automatic CS control, but it is 158 * somewhat quirky, and it doesn't really buy us much anyway 159 * in the context of U-Boot. 160 */ 161 if (flags & SPI_XFER_BEGIN) { 162 atmel_spi_cs_activate(dev); 163 164 /* 165 * sometimes the RDR is not empty when we get here, 166 * in theory that should not happen, but it DOES happen. 167 * Read it here to be on the safe side. 168 * That also clears the OVRES flag. Required if the 169 * following loop exits due to OVRES! 170 */ 171 readl(®_base->rdr); 172 } 173 174 for (len_tx = 0, len_rx = 0; len_rx < len; ) { 175 status = readl(®_base->sr); 176 177 if (status & ATMEL_SPI_SR_OVRES) 178 return -1; 179 180 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) { 181 if (txp) 182 value = *txp++; 183 else 184 value = 0; 185 writel(value, ®_base->tdr); 186 len_tx++; 187 } 188 189 if (status & ATMEL_SPI_SR_RDRF) { 190 value = readl(®_base->rdr); 191 if (rxp) 192 *rxp++ = value; 193 len_rx++; 194 } 195 } 196 197 out: 198 if (flags & SPI_XFER_END) { 199 /* 200 * Wait until the transfer is completely done before 201 * we deactivate CS. 202 */ 203 wait_for_bit_le32(®_base->sr, 204 ATMEL_SPI_SR_TXEMPTY, true, 1000, false); 205 206 atmel_spi_cs_deactivate(dev); 207 } 208 209 return 0; 210 } 211 212 static int atmel_spi_set_speed(struct udevice *bus, uint speed) 213 { 214 struct atmel_spi_priv *priv = dev_get_priv(bus); 215 216 priv->freq = speed; 217 218 return 0; 219 } 220 221 static int atmel_spi_set_mode(struct udevice *bus, uint mode) 222 { 223 struct atmel_spi_priv *priv = dev_get_priv(bus); 224 225 priv->mode = mode; 226 227 return 0; 228 } 229 230 static const struct dm_spi_ops atmel_spi_ops = { 231 .claim_bus = atmel_spi_claim_bus, 232 .release_bus = atmel_spi_release_bus, 233 .xfer = atmel_spi_xfer, 234 .set_speed = atmel_spi_set_speed, 235 .set_mode = atmel_spi_set_mode, 236 /* 237 * cs_info is not needed, since we require all chip selects to be 238 * in the device tree explicitly 239 */ 240 }; 241 242 static int atmel_spi_enable_clk(struct udevice *bus) 243 { 244 struct atmel_spi_priv *priv = dev_get_priv(bus); 245 struct clk clk; 246 ulong clk_rate; 247 int ret; 248 249 ret = clk_get_by_index(bus, 0, &clk); 250 if (ret) 251 return -EINVAL; 252 253 ret = clk_enable(&clk); 254 if (ret) 255 return ret; 256 257 clk_rate = clk_get_rate(&clk); 258 if (!clk_rate) 259 return -EINVAL; 260 261 priv->bus_clk_rate = clk_rate; 262 263 clk_free(&clk); 264 265 return 0; 266 } 267 268 static int atmel_spi_probe(struct udevice *bus) 269 { 270 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 271 int ret; 272 273 ret = atmel_spi_enable_clk(bus); 274 if (ret) 275 return ret; 276 277 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus); 278 279 #ifdef CONFIG_DM_GPIO 280 struct atmel_spi_priv *priv = dev_get_priv(bus); 281 int i; 282 283 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios, 284 ARRAY_SIZE(priv->cs_gpios), 0); 285 if (ret < 0) { 286 pr_err("Can't get %s gpios! Error: %d", bus->name, ret); 287 return ret; 288 } 289 290 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) { 291 if (!dm_gpio_is_valid(&priv->cs_gpios[i])) 292 continue; 293 294 dm_gpio_set_dir_flags(&priv->cs_gpios[i], 295 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 296 } 297 #endif 298 299 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr); 300 301 return 0; 302 } 303 304 static const struct udevice_id atmel_spi_ids[] = { 305 { .compatible = "atmel,at91rm9200-spi" }, 306 { } 307 }; 308 309 U_BOOT_DRIVER(atmel_spi) = { 310 .name = "atmel_spi", 311 .id = UCLASS_SPI, 312 .of_match = atmel_spi_ids, 313 .ops = &atmel_spi_ops, 314 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata), 315 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), 316 .probe = atmel_spi_probe, 317 }; 318