1*cf885929SSimon Glass // SPDX-License-Identifier: GPL-2.0+
2*cf885929SSimon Glass /*
3*cf885929SSimon Glass * Copyright 2019 Google LLC
4*cf885929SSimon Glass */
5*cf885929SSimon Glass
6*cf885929SSimon Glass #define LOG_CATEGORY UCLASS_SOUND
7*cf885929SSimon Glass
8*cf885929SSimon Glass #include <common.h>
9*cf885929SSimon Glass #include <audio_codec.h>
10*cf885929SSimon Glass #include <dm.h>
11*cf885929SSimon Glass #include <i2c.h>
12*cf885929SSimon Glass #include "rt5677.h"
13*cf885929SSimon Glass
14*cf885929SSimon Glass struct rt5677_priv {
15*cf885929SSimon Glass struct udevice *dev;
16*cf885929SSimon Glass };
17*cf885929SSimon Glass
18*cf885929SSimon Glass /* RT5677 has 256 8-bit register addresses, and 16-bit register data */
19*cf885929SSimon Glass struct rt5677_init_reg {
20*cf885929SSimon Glass u8 reg;
21*cf885929SSimon Glass u16 val;
22*cf885929SSimon Glass };
23*cf885929SSimon Glass
24*cf885929SSimon Glass static struct rt5677_init_reg init_list[] = {
25*cf885929SSimon Glass {RT5677_LOUT1, 0x0800},
26*cf885929SSimon Glass {RT5677_SIDETONE_CTRL, 0x0000},
27*cf885929SSimon Glass {RT5677_STO1_ADC_DIG_VOL, 0x3F3F},
28*cf885929SSimon Glass {RT5677_DAC1_DIG_VOL, 0x9090},
29*cf885929SSimon Glass {RT5677_STO2_ADC_MIXER, 0xA441},
30*cf885929SSimon Glass {RT5677_STO1_ADC_MIXER, 0x5480},
31*cf885929SSimon Glass {RT5677_STO1_DAC_MIXER, 0x8A8A},
32*cf885929SSimon Glass {RT5677_PWR_DIG1, 0x9800}, /* Power up I2S1 */
33*cf885929SSimon Glass {RT5677_PWR_ANLG1, 0xE9D5},
34*cf885929SSimon Glass {RT5677_PWR_ANLG2, 0x2CC0},
35*cf885929SSimon Glass {RT5677_PWR_DSP2, 0x0C00},
36*cf885929SSimon Glass {RT5677_I2S2_SDP, 0x0000},
37*cf885929SSimon Glass {RT5677_CLK_TREE_CTRL1, 0x1111},
38*cf885929SSimon Glass {RT5677_PLL1_CTRL1, 0x0000},
39*cf885929SSimon Glass {RT5677_PLL1_CTRL2, 0x0000},
40*cf885929SSimon Glass {RT5677_DIG_MISC, 0x0029},
41*cf885929SSimon Glass {RT5677_GEN_CTRL1, 0x00FF},
42*cf885929SSimon Glass {RT5677_GPIO_CTRL2, 0x0020},
43*cf885929SSimon Glass {RT5677_PWR_DIG2, 0x9024}, /* Power on ADC Stereo Filters */
44*cf885929SSimon Glass {RT5677_PDM_OUT_CTRL, 0x0088}, /* Unmute PDM, set stereo1 DAC */
45*cf885929SSimon Glass {RT5677_PDM_DATA_CTRL1, 0x0001}, /* Sysclk to PDM filter divider 2 */
46*cf885929SSimon Glass };
47*cf885929SSimon Glass
48*cf885929SSimon Glass /**
49*cf885929SSimon Glass * rt5677_i2c_read() - Read a 16-bit register
50*cf885929SSimon Glass *
51*cf885929SSimon Glass * @priv: Private driver data
52*cf885929SSimon Glass * @reg: Register number to read
53*cf885929SSimon Glass * @returns data read or -ve on error
54*cf885929SSimon Glass */
rt5677_i2c_read(struct rt5677_priv * priv,uint reg)55*cf885929SSimon Glass static int rt5677_i2c_read(struct rt5677_priv *priv, uint reg)
56*cf885929SSimon Glass {
57*cf885929SSimon Glass u8 buf[2];
58*cf885929SSimon Glass int ret;
59*cf885929SSimon Glass
60*cf885929SSimon Glass ret = dm_i2c_read(priv->dev, reg, buf, sizeof(u16));
61*cf885929SSimon Glass if (ret)
62*cf885929SSimon Glass return ret;
63*cf885929SSimon Glass return buf[0] << 8 | buf[1];
64*cf885929SSimon Glass }
65*cf885929SSimon Glass
66*cf885929SSimon Glass /**
67*cf885929SSimon Glass * rt5677_i2c_write() - Write a 16-bit register
68*cf885929SSimon Glass *
69*cf885929SSimon Glass * @priv: Private driver data
70*cf885929SSimon Glass * @reg: Register number to read
71*cf885929SSimon Glass * @data: Data to write
72*cf885929SSimon Glass * @returns 0 if OK, -ve on error
73*cf885929SSimon Glass */
rt5677_i2c_write(struct rt5677_priv * priv,uint reg,uint data)74*cf885929SSimon Glass static int rt5677_i2c_write(struct rt5677_priv *priv, uint reg, uint data)
75*cf885929SSimon Glass {
76*cf885929SSimon Glass u8 buf[2];
77*cf885929SSimon Glass
78*cf885929SSimon Glass buf[0] = (data >> 8) & 0xff;
79*cf885929SSimon Glass buf[1] = data & 0xff;
80*cf885929SSimon Glass
81*cf885929SSimon Glass return dm_i2c_write(priv->dev, reg, buf, sizeof(u16));
82*cf885929SSimon Glass }
83*cf885929SSimon Glass
84*cf885929SSimon Glass /**
85*cf885929SSimon Glass * rt5677_bic_or() - Set and clear bits of a codec register
86*cf885929SSimon Glass *
87*cf885929SSimon Glass * @priv: Private driver data
88*cf885929SSimon Glass * @reg: Register number to update
89*cf885929SSimon Glass * @bic: Mask of bits to clear
90*cf885929SSimon Glass * @set: Mask of bits to set
91*cf885929SSimon Glass * @returns 0 if OK, -ve on error
92*cf885929SSimon Glass *
93*cf885929SSimon Glass */
rt5677_bic_or(struct rt5677_priv * priv,uint reg,uint bic,uint set)94*cf885929SSimon Glass static int rt5677_bic_or(struct rt5677_priv *priv, uint reg, uint bic,
95*cf885929SSimon Glass uint set)
96*cf885929SSimon Glass {
97*cf885929SSimon Glass uint old, new_value;
98*cf885929SSimon Glass int ret;
99*cf885929SSimon Glass
100*cf885929SSimon Glass old = rt5677_i2c_read(priv, reg);
101*cf885929SSimon Glass if (old < 0)
102*cf885929SSimon Glass return old;
103*cf885929SSimon Glass
104*cf885929SSimon Glass new_value = (old & ~bic) | (set & bic);
105*cf885929SSimon Glass
106*cf885929SSimon Glass if (old != new_value) {
107*cf885929SSimon Glass ret = rt5677_i2c_write(priv, reg, new_value);
108*cf885929SSimon Glass if (ret)
109*cf885929SSimon Glass return ret;
110*cf885929SSimon Glass }
111*cf885929SSimon Glass
112*cf885929SSimon Glass return 0;
113*cf885929SSimon Glass }
114*cf885929SSimon Glass
115*cf885929SSimon Glass /**
116*cf885929SSimon Glass * rt5677_reg_init() - Initialise codec regs w/static/base values
117*cf885929SSimon Glass *
118*cf885929SSimon Glass * @priv: Private driver data
119*cf885929SSimon Glass * @returns 0 if OK, -ve on error
120*cf885929SSimon Glass */
rt5677_reg_init(struct rt5677_priv * priv)121*cf885929SSimon Glass static int rt5677_reg_init(struct rt5677_priv *priv)
122*cf885929SSimon Glass {
123*cf885929SSimon Glass int ret;
124*cf885929SSimon Glass int i;
125*cf885929SSimon Glass
126*cf885929SSimon Glass for (i = 0; i < ARRAY_SIZE(init_list); i++) {
127*cf885929SSimon Glass ret = rt5677_i2c_write(priv, init_list[i].reg, init_list[i].val);
128*cf885929SSimon Glass if (ret)
129*cf885929SSimon Glass return ret;
130*cf885929SSimon Glass }
131*cf885929SSimon Glass
132*cf885929SSimon Glass return 0;
133*cf885929SSimon Glass }
134*cf885929SSimon Glass
135*cf885929SSimon Glass #ifdef DEBUG
debug_dump_5677_regs(struct rt5677_priv * priv,int swap)136*cf885929SSimon Glass static void debug_dump_5677_regs(struct rt5677_priv *priv, int swap)
137*cf885929SSimon Glass {
138*cf885929SSimon Glass uint i, reg_word;
139*cf885929SSimon Glass
140*cf885929SSimon Glass /* Show all 16-bit codec regs */
141*cf885929SSimon Glass for (i = 0; i < RT5677_REG_CNT; i++) {
142*cf885929SSimon Glass if (i % 8 == 0)
143*cf885929SSimon Glass log_debug("\nMX%02x: ", i);
144*cf885929SSimon Glass
145*cf885929SSimon Glass rt5677_i2c_read(priv, (u8)i, ®_word);
146*cf885929SSimon Glass if (swap)
147*cf885929SSimon Glass log_debug("%04x ", swap_bytes16(reg_word));
148*cf885929SSimon Glass else
149*cf885929SSimon Glass log_debug("%04x ", reg_word);
150*cf885929SSimon Glass }
151*cf885929SSimon Glass log_debug("\n");
152*cf885929SSimon Glass
153*cf885929SSimon Glass /* Show all 16-bit 'private' codec regs */
154*cf885929SSimon Glass for (i = 0; i < RT5677_PR_REG_CNT; i++) {
155*cf885929SSimon Glass if (i % 8 == 0)
156*cf885929SSimon Glass log_debug("\nPR%02x: ", i);
157*cf885929SSimon Glass
158*cf885929SSimon Glass rt5677_i2c_write(priv, RT5677_PRIV_INDEX, i);
159*cf885929SSimon Glass rt5677_i2c_read(priv, RT5677_PRIV_DATA, ®_word);
160*cf885929SSimon Glass if (swap)
161*cf885929SSimon Glass log_debug("%04x ", swap_bytes16(reg_word));
162*cf885929SSimon Glass else
163*cf885929SSimon Glass log_debug("%04x ", reg_word);
164*cf885929SSimon Glass }
165*cf885929SSimon Glass log_debug("\n");
166*cf885929SSimon Glass }
167*cf885929SSimon Glass #endif /* DEBUG */
168*cf885929SSimon Glass
rt5677_hw_params(struct rt5677_priv * priv,uint bits_per_sample)169*cf885929SSimon Glass static int rt5677_hw_params(struct rt5677_priv *priv, uint bits_per_sample)
170*cf885929SSimon Glass {
171*cf885929SSimon Glass int ret;
172*cf885929SSimon Glass
173*cf885929SSimon Glass switch (bits_per_sample) {
174*cf885929SSimon Glass case 16:
175*cf885929SSimon Glass ret = rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_DL_MASK,
176*cf885929SSimon Glass 0);
177*cf885929SSimon Glass if (ret) {
178*cf885929SSimon Glass log_debug("Error updating I2S1 Interface Ctrl reg\n");
179*cf885929SSimon Glass return 1;
180*cf885929SSimon Glass }
181*cf885929SSimon Glass break;
182*cf885929SSimon Glass default:
183*cf885929SSimon Glass log_err("Illegal bits per sample %d\n", bits_per_sample);
184*cf885929SSimon Glass return -EINVAL;
185*cf885929SSimon Glass }
186*cf885929SSimon Glass
187*cf885929SSimon Glass return 0;
188*cf885929SSimon Glass }
189*cf885929SSimon Glass
190*cf885929SSimon Glass /**
191*cf885929SSimon Glass * rt5677_set_fmt() - set rt5677 I2S format
192*cf885929SSimon Glass *
193*cf885929SSimon Glass * @priv: Private driver data
194*cf885929SSimon Glass * @returns 0 if OK, -ve on error
195*cf885929SSimon Glass */
rt5677_set_fmt(struct rt5677_priv * priv)196*cf885929SSimon Glass static int rt5677_set_fmt(struct rt5677_priv *priv)
197*cf885929SSimon Glass {
198*cf885929SSimon Glass int ret = 0;
199*cf885929SSimon Glass
200*cf885929SSimon Glass /*
201*cf885929SSimon Glass * Set format here: Assumes I2S, NB_NF, CBS_CFS
202*cf885929SSimon Glass *
203*cf885929SSimon Glass * CBS_CFS (Codec Bit Slave/Codec Frame Slave)
204*cf885929SSimon Glass */
205*cf885929SSimon Glass ret = rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_MS_MASK,
206*cf885929SSimon Glass RT5677_I2S_MS_S);
207*cf885929SSimon Glass
208*cf885929SSimon Glass /* NB_NF (Normal Bit/Normal Frame) */
209*cf885929SSimon Glass ret |= rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_BP_MASK,
210*cf885929SSimon Glass RT5677_I2S_BP_NOR);
211*cf885929SSimon Glass
212*cf885929SSimon Glass /* I2S mode */
213*cf885929SSimon Glass ret |= rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_DF_MASK,
214*cf885929SSimon Glass RT5677_I2S_DF_I2S);
215*cf885929SSimon Glass
216*cf885929SSimon Glass /* A44: I2S2 (going to speaker amp) is master */
217*cf885929SSimon Glass ret |= rt5677_bic_or(priv, RT5677_I2S2_SDP, RT5677_I2S_MS_MASK,
218*cf885929SSimon Glass RT5677_I2S_MS_M);
219*cf885929SSimon Glass
220*cf885929SSimon Glass if (ret) {
221*cf885929SSimon Glass log_err("Error updating I2S1 Interface Ctrl reg\n");
222*cf885929SSimon Glass return ret;
223*cf885929SSimon Glass }
224*cf885929SSimon Glass
225*cf885929SSimon Glass return 0;
226*cf885929SSimon Glass }
227*cf885929SSimon Glass
228*cf885929SSimon Glass /**
229*cf885929SSimon Glass * rt5677_reset() - reset the audio codec
230*cf885929SSimon Glass *
231*cf885929SSimon Glass * @priv: Private driver data
232*cf885929SSimon Glass * @returns 0 if OK, -ve on error
233*cf885929SSimon Glass */
rt5677_reset(struct rt5677_priv * priv)234*cf885929SSimon Glass static int rt5677_reset(struct rt5677_priv *priv)
235*cf885929SSimon Glass {
236*cf885929SSimon Glass int ret;
237*cf885929SSimon Glass
238*cf885929SSimon Glass /* Reset the codec registers to their defaults */
239*cf885929SSimon Glass ret = rt5677_i2c_write(priv, RT5677_RESET, RT5677_SW_RESET);
240*cf885929SSimon Glass if (ret) {
241*cf885929SSimon Glass log_err("Error resetting codec\n");
242*cf885929SSimon Glass return ret;
243*cf885929SSimon Glass }
244*cf885929SSimon Glass
245*cf885929SSimon Glass return 0;
246*cf885929SSimon Glass }
247*cf885929SSimon Glass
248*cf885929SSimon Glass /**
249*cf885929SSimon Glass * Initialise rt5677 codec device
250*cf885929SSimon Glass *
251*cf885929SSimon Glass * @priv: Private driver data
252*cf885929SSimon Glass * @returns 0 if OK, -ve on error
253*cf885929SSimon Glass */
rt5677_device_init(struct rt5677_priv * priv)254*cf885929SSimon Glass int rt5677_device_init(struct rt5677_priv *priv)
255*cf885929SSimon Glass {
256*cf885929SSimon Glass int ret;
257*cf885929SSimon Glass
258*cf885929SSimon Glass /* Read status reg */
259*cf885929SSimon Glass ret = rt5677_i2c_read(priv, RT5677_RESET);
260*cf885929SSimon Glass if (ret < 0)
261*cf885929SSimon Glass return ret;
262*cf885929SSimon Glass log_debug("reg 00h, Software Reset & Status = 0x%04x\n", ret);
263*cf885929SSimon Glass
264*cf885929SSimon Glass /* Reset the codec/regs */
265*cf885929SSimon Glass ret = rt5677_reset(priv);
266*cf885929SSimon Glass if (ret)
267*cf885929SSimon Glass return ret;
268*cf885929SSimon Glass
269*cf885929SSimon Glass ret = rt5677_i2c_read(priv, RT5677_VENDOR_ID1);
270*cf885929SSimon Glass if (ret < 0) {
271*cf885929SSimon Glass log_err("Error reading vendor ID\n");
272*cf885929SSimon Glass return 1;
273*cf885929SSimon Glass }
274*cf885929SSimon Glass log_debug("Hardware ID: %0xX\n", ret);
275*cf885929SSimon Glass
276*cf885929SSimon Glass ret = rt5677_i2c_read(priv, RT5677_VENDOR_ID2);
277*cf885929SSimon Glass if (ret < 0) {
278*cf885929SSimon Glass log_err("Error reading vendor rev\n");
279*cf885929SSimon Glass return 1;
280*cf885929SSimon Glass }
281*cf885929SSimon Glass log_debug("Hardware revision: %04x\n", ret);
282*cf885929SSimon Glass
283*cf885929SSimon Glass return 0;
284*cf885929SSimon Glass }
285*cf885929SSimon Glass
rt5677_set_params(struct udevice * dev,int interface,int rate,int mclk_freq,int bits_per_sample,uint channels)286*cf885929SSimon Glass static int rt5677_set_params(struct udevice *dev, int interface, int rate,
287*cf885929SSimon Glass int mclk_freq, int bits_per_sample,
288*cf885929SSimon Glass uint channels)
289*cf885929SSimon Glass {
290*cf885929SSimon Glass struct rt5677_priv *priv = dev_get_priv(dev);
291*cf885929SSimon Glass int ret;
292*cf885929SSimon Glass
293*cf885929SSimon Glass /* Initialise codec regs w/static/base values, same as Linux driver */
294*cf885929SSimon Glass ret = rt5677_reg_init(priv);
295*cf885929SSimon Glass if (ret)
296*cf885929SSimon Glass return ret;
297*cf885929SSimon Glass
298*cf885929SSimon Glass ret = rt5677_hw_params(priv, bits_per_sample);
299*cf885929SSimon Glass if (ret)
300*cf885929SSimon Glass return ret;
301*cf885929SSimon Glass
302*cf885929SSimon Glass ret = rt5677_set_fmt(priv);
303*cf885929SSimon Glass if (ret)
304*cf885929SSimon Glass return ret;
305*cf885929SSimon Glass
306*cf885929SSimon Glass return 0;
307*cf885929SSimon Glass }
308*cf885929SSimon Glass
rt5677_probe(struct udevice * dev)309*cf885929SSimon Glass static int rt5677_probe(struct udevice *dev)
310*cf885929SSimon Glass {
311*cf885929SSimon Glass struct rt5677_priv *priv = dev_get_priv(dev);
312*cf885929SSimon Glass
313*cf885929SSimon Glass priv->dev = dev;
314*cf885929SSimon Glass
315*cf885929SSimon Glass return rt5677_device_init(priv);
316*cf885929SSimon Glass }
317*cf885929SSimon Glass
318*cf885929SSimon Glass static const struct audio_codec_ops rt5677_ops = {
319*cf885929SSimon Glass .set_params = rt5677_set_params,
320*cf885929SSimon Glass };
321*cf885929SSimon Glass
322*cf885929SSimon Glass static const struct udevice_id rt5677_ids[] = {
323*cf885929SSimon Glass { .compatible = "realtek,rt5677" },
324*cf885929SSimon Glass { }
325*cf885929SSimon Glass };
326*cf885929SSimon Glass
327*cf885929SSimon Glass U_BOOT_DRIVER(rt5677_drv) = {
328*cf885929SSimon Glass .name = "rt5677",
329*cf885929SSimon Glass .id = UCLASS_AUDIO_CODEC,
330*cf885929SSimon Glass .of_match = rt5677_ids,
331*cf885929SSimon Glass .ops = &rt5677_ops,
332*cf885929SSimon Glass .probe = rt5677_probe,
333*cf885929SSimon Glass .priv_auto_alloc_size = sizeof(struct rt5677_priv),
334*cf885929SSimon Glass };
335