xref: /openbmc/u-boot/drivers/rtc/pl031.c (revision 0ae8dcfef7c890330c62bb34c724126ffc169bef)
183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2535cfa4fSGururaja Hebbar K R /*
3535cfa4fSGururaja Hebbar K R  * (C) Copyright 2008
4535cfa4fSGururaja Hebbar K R  * Gururaja Hebbar gururajakr@sanyo.co.in
5535cfa4fSGururaja Hebbar K R  *
6535cfa4fSGururaja Hebbar K R  * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
7535cfa4fSGururaja Hebbar K R  */
8535cfa4fSGururaja Hebbar K R 
9535cfa4fSGururaja Hebbar K R #include <common.h>
10535cfa4fSGururaja Hebbar K R #include <command.h>
11*a370e429SAKASHI Takahiro #include <dm.h>
12*a370e429SAKASHI Takahiro #include <errno.h>
13535cfa4fSGururaja Hebbar K R #include <rtc.h>
14*a370e429SAKASHI Takahiro #include <asm/io.h>
15*a370e429SAKASHI Takahiro #include <asm/types.h>
16535cfa4fSGururaja Hebbar K R 
17535cfa4fSGururaja Hebbar K R /*
18535cfa4fSGururaja Hebbar K R  * Register definitions
19535cfa4fSGururaja Hebbar K R  */
20535cfa4fSGururaja Hebbar K R #define	RTC_DR		0x00	/* Data read register */
21535cfa4fSGururaja Hebbar K R #define	RTC_MR		0x04	/* Match register */
22535cfa4fSGururaja Hebbar K R #define	RTC_LR		0x08	/* Data load register */
23535cfa4fSGururaja Hebbar K R #define	RTC_CR		0x0c	/* Control register */
24535cfa4fSGururaja Hebbar K R #define	RTC_IMSC	0x10	/* Interrupt mask and set register */
25535cfa4fSGururaja Hebbar K R #define	RTC_RIS		0x14	/* Raw interrupt status register */
26535cfa4fSGururaja Hebbar K R #define	RTC_MIS		0x18	/* Masked interrupt status register */
27535cfa4fSGururaja Hebbar K R #define	RTC_ICR		0x1c	/* Interrupt clear register */
28535cfa4fSGururaja Hebbar K R 
29535cfa4fSGururaja Hebbar K R #define RTC_CR_START	(1 << 0)
30535cfa4fSGururaja Hebbar K R 
31*a370e429SAKASHI Takahiro struct pl031_platdata {
32*a370e429SAKASHI Takahiro 	phys_addr_t base;
33*a370e429SAKASHI Takahiro };
34535cfa4fSGururaja Hebbar K R 
pl031_read_reg(struct udevice * dev,int reg)35*a370e429SAKASHI Takahiro static inline u32 pl031_read_reg(struct udevice *dev, int reg)
36*a370e429SAKASHI Takahiro {
37*a370e429SAKASHI Takahiro 	struct pl031_platdata *pdata = dev_get_platdata(dev);
38535cfa4fSGururaja Hebbar K R 
39*a370e429SAKASHI Takahiro 	return readl(pdata->base + reg);
40*a370e429SAKASHI Takahiro }
41*a370e429SAKASHI Takahiro 
pl031_write_reg(struct udevice * dev,int reg,u32 value)42*a370e429SAKASHI Takahiro static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
43*a370e429SAKASHI Takahiro {
44*a370e429SAKASHI Takahiro 	struct pl031_platdata *pdata = dev_get_platdata(dev);
45*a370e429SAKASHI Takahiro 
46*a370e429SAKASHI Takahiro 	return writel(value, pdata->base + reg);
47*a370e429SAKASHI Takahiro }
48*a370e429SAKASHI Takahiro 
49*a370e429SAKASHI Takahiro /*
50*a370e429SAKASHI Takahiro  * Probe RTC device
51*a370e429SAKASHI Takahiro  */
pl031_probe(struct udevice * dev)52*a370e429SAKASHI Takahiro static int pl031_probe(struct udevice *dev)
53*a370e429SAKASHI Takahiro {
54535cfa4fSGururaja Hebbar K R 	/* Enable RTC Start in Control register*/
55*a370e429SAKASHI Takahiro 	pl031_write_reg(dev, RTC_CR, RTC_CR_START);
56535cfa4fSGururaja Hebbar K R 
57*a370e429SAKASHI Takahiro 	return 0;
58535cfa4fSGururaja Hebbar K R }
59535cfa4fSGururaja Hebbar K R 
60535cfa4fSGururaja Hebbar K R /*
61535cfa4fSGururaja Hebbar K R  * Get the current time from the RTC
62535cfa4fSGururaja Hebbar K R  */
pl031_get(struct udevice * dev,struct rtc_time * tm)63*a370e429SAKASHI Takahiro static int pl031_get(struct udevice *dev, struct rtc_time *tm)
64535cfa4fSGururaja Hebbar K R {
65*a370e429SAKASHI Takahiro 	unsigned long tim;
66535cfa4fSGururaja Hebbar K R 
67*a370e429SAKASHI Takahiro 	if (!tm)
68*a370e429SAKASHI Takahiro 		return -EINVAL;
69535cfa4fSGururaja Hebbar K R 
70*a370e429SAKASHI Takahiro 	tim = pl031_read_reg(dev, RTC_DR);
71535cfa4fSGururaja Hebbar K R 
72*a370e429SAKASHI Takahiro 	rtc_to_tm(tim, tm);
73535cfa4fSGururaja Hebbar K R 
74535cfa4fSGururaja Hebbar K R 	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
75*a370e429SAKASHI Takahiro 	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
76*a370e429SAKASHI Takahiro 	      tm->tm_hour, tm->tm_min, tm->tm_sec);
77535cfa4fSGururaja Hebbar K R 
78535cfa4fSGururaja Hebbar K R 	return 0;
79535cfa4fSGururaja Hebbar K R }
80535cfa4fSGururaja Hebbar K R 
81*a370e429SAKASHI Takahiro /*
82*a370e429SAKASHI Takahiro  * Set the RTC
83*a370e429SAKASHI Takahiro  */
pl031_set(struct udevice * dev,const struct rtc_time * tm)84*a370e429SAKASHI Takahiro static int pl031_set(struct udevice *dev, const struct rtc_time *tm)
85*a370e429SAKASHI Takahiro {
86*a370e429SAKASHI Takahiro 	unsigned long tim;
87*a370e429SAKASHI Takahiro 
88*a370e429SAKASHI Takahiro 	if (!tm)
89*a370e429SAKASHI Takahiro 		return -EINVAL;
90*a370e429SAKASHI Takahiro 
91*a370e429SAKASHI Takahiro 	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
92*a370e429SAKASHI Takahiro 	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
93*a370e429SAKASHI Takahiro 	      tm->tm_hour, tm->tm_min, tm->tm_sec);
94*a370e429SAKASHI Takahiro 
95*a370e429SAKASHI Takahiro 	/* Calculate number of seconds this incoming time represents */
96*a370e429SAKASHI Takahiro 	tim = rtc_mktime(tm);
97*a370e429SAKASHI Takahiro 
98*a370e429SAKASHI Takahiro 	pl031_write_reg(dev, RTC_LR, tim);
99*a370e429SAKASHI Takahiro 
100*a370e429SAKASHI Takahiro 	return 0;
101*a370e429SAKASHI Takahiro }
102*a370e429SAKASHI Takahiro 
103*a370e429SAKASHI Takahiro /*
104*a370e429SAKASHI Takahiro  * Reset the RTC. We set the date back to 1970-01-01.
105*a370e429SAKASHI Takahiro  */
pl031_reset(struct udevice * dev)106*a370e429SAKASHI Takahiro static int pl031_reset(struct udevice *dev)
107*a370e429SAKASHI Takahiro {
108*a370e429SAKASHI Takahiro 	pl031_write_reg(dev, RTC_LR, 0);
109*a370e429SAKASHI Takahiro 
110*a370e429SAKASHI Takahiro 	return 0;
111*a370e429SAKASHI Takahiro }
112*a370e429SAKASHI Takahiro 
113*a370e429SAKASHI Takahiro static const struct rtc_ops pl031_ops = {
114*a370e429SAKASHI Takahiro 	.get = pl031_get,
115*a370e429SAKASHI Takahiro 	.set = pl031_set,
116*a370e429SAKASHI Takahiro 	.reset = pl031_reset,
117*a370e429SAKASHI Takahiro };
118*a370e429SAKASHI Takahiro 
119*a370e429SAKASHI Takahiro static const struct udevice_id pl031_ids[] = {
120*a370e429SAKASHI Takahiro 	{ .compatible = "arm,pl031" },
121*a370e429SAKASHI Takahiro 	{ }
122*a370e429SAKASHI Takahiro };
123*a370e429SAKASHI Takahiro 
pl031_ofdata_to_platdata(struct udevice * dev)124*a370e429SAKASHI Takahiro static int pl031_ofdata_to_platdata(struct udevice *dev)
125*a370e429SAKASHI Takahiro {
126*a370e429SAKASHI Takahiro 	struct pl031_platdata *pdata = dev_get_platdata(dev);
127*a370e429SAKASHI Takahiro 
128*a370e429SAKASHI Takahiro 	pdata->base = dev_read_addr(dev);
129*a370e429SAKASHI Takahiro 
130*a370e429SAKASHI Takahiro 	return 0;
131*a370e429SAKASHI Takahiro }
132*a370e429SAKASHI Takahiro 
133*a370e429SAKASHI Takahiro U_BOOT_DRIVER(rtc_pl031) = {
134*a370e429SAKASHI Takahiro 	.name	= "rtc-pl031",
135*a370e429SAKASHI Takahiro 	.id	= UCLASS_RTC,
136*a370e429SAKASHI Takahiro 	.of_match = pl031_ids,
137*a370e429SAKASHI Takahiro 	.probe	= pl031_probe,
138*a370e429SAKASHI Takahiro 	.ofdata_to_platdata = pl031_ofdata_to_platdata,
139*a370e429SAKASHI Takahiro 	.platdata_auto_alloc_size = sizeof(struct pl031_platdata),
140*a370e429SAKASHI Takahiro 	.ops	= &pl031_ops,
141*a370e429SAKASHI Takahiro };
142