183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
29536dfccSTor Krill /*
39536dfccSTor Krill * (C) Copyright 2008
49536dfccSTor Krill * Tor Krill, Excito Elektronik i Skåne , tor@excito.com
59536dfccSTor Krill *
69536dfccSTor Krill * Modelled after the ds1337 driver
79536dfccSTor Krill */
89536dfccSTor Krill
99536dfccSTor Krill /*
109536dfccSTor Krill * Date & Time support (no alarms) for Intersil
119536dfccSTor Krill * ISL1208 Real Time Clock (RTC).
129536dfccSTor Krill */
139536dfccSTor Krill
149536dfccSTor Krill #include <common.h>
159536dfccSTor Krill #include <command.h>
1652280315SKlaus Goger #include <dm.h>
179536dfccSTor Krill #include <rtc.h>
189536dfccSTor Krill #include <i2c.h>
199536dfccSTor Krill
209536dfccSTor Krill /*---------------------------------------------------------------------*/
219536dfccSTor Krill #ifdef DEBUG_RTC
229536dfccSTor Krill #define DEBUGR(fmt,args...) printf(fmt ,##args)
239536dfccSTor Krill #else
249536dfccSTor Krill #define DEBUGR(fmt,args...)
259536dfccSTor Krill #endif
269536dfccSTor Krill /*---------------------------------------------------------------------*/
279536dfccSTor Krill
289536dfccSTor Krill /*
299536dfccSTor Krill * RTC register addresses
309536dfccSTor Krill */
319536dfccSTor Krill
329536dfccSTor Krill #define RTC_SEC_REG_ADDR 0x0
339536dfccSTor Krill #define RTC_MIN_REG_ADDR 0x1
349536dfccSTor Krill #define RTC_HR_REG_ADDR 0x2
359536dfccSTor Krill #define RTC_DATE_REG_ADDR 0x3
369536dfccSTor Krill #define RTC_MON_REG_ADDR 0x4
379536dfccSTor Krill #define RTC_YR_REG_ADDR 0x5
389536dfccSTor Krill #define RTC_DAY_REG_ADDR 0x6
399536dfccSTor Krill #define RTC_STAT_REG_ADDR 0x7
409536dfccSTor Krill /*
419536dfccSTor Krill * RTC control register bits
429536dfccSTor Krill */
439536dfccSTor Krill
449536dfccSTor Krill /*
459536dfccSTor Krill * RTC status register bits
469536dfccSTor Krill */
479536dfccSTor Krill #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
489536dfccSTor Krill #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
499536dfccSTor Krill #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
509536dfccSTor Krill #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
519536dfccSTor Krill #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
529536dfccSTor Krill #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
539536dfccSTor Krill
549536dfccSTor Krill /*
55*4a094725STrent Piepho * Read an RTC register
56*4a094725STrent Piepho */
57*4a094725STrent Piepho
isl1208_rtc_read8(struct udevice * dev,unsigned int reg)58*4a094725STrent Piepho static int isl1208_rtc_read8(struct udevice *dev, unsigned int reg)
59*4a094725STrent Piepho {
60*4a094725STrent Piepho return dm_i2c_reg_read(dev, reg);
61*4a094725STrent Piepho }
62*4a094725STrent Piepho
63*4a094725STrent Piepho /*
64*4a094725STrent Piepho * Write an RTC register
65*4a094725STrent Piepho */
66*4a094725STrent Piepho
isl1208_rtc_write8(struct udevice * dev,unsigned int reg,int val)67*4a094725STrent Piepho static int isl1208_rtc_write8(struct udevice *dev, unsigned int reg, int val)
68*4a094725STrent Piepho {
69*4a094725STrent Piepho return dm_i2c_reg_write(dev, reg, val);
70*4a094725STrent Piepho }
71*4a094725STrent Piepho
72*4a094725STrent Piepho /*
739536dfccSTor Krill * Get the current time from the RTC
749536dfccSTor Krill */
759536dfccSTor Krill
isl1208_rtc_get(struct udevice * dev,struct rtc_time * tmp)7652280315SKlaus Goger static int isl1208_rtc_get(struct udevice *dev, struct rtc_time *tmp)
779536dfccSTor Krill {
7852280315SKlaus Goger int ret;
7952280315SKlaus Goger uchar buf[8], val;
809536dfccSTor Krill
8152280315SKlaus Goger ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
8252280315SKlaus Goger if (ret < 0)
8352280315SKlaus Goger return ret;
849536dfccSTor Krill
8552280315SKlaus Goger if (buf[RTC_STAT_REG_ADDR] & RTC_STAT_BIT_RTCF) {
869536dfccSTor Krill printf ("### Warning: RTC oscillator has stopped\n");
8752280315SKlaus Goger ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
8852280315SKlaus Goger if (ret < 0)
8952280315SKlaus Goger return ret;
9052280315SKlaus Goger
9152280315SKlaus Goger val = val & ~(RTC_STAT_BIT_BAT | RTC_STAT_BIT_RTCF);
9252280315SKlaus Goger ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
9352280315SKlaus Goger if (ret < 0)
9452280315SKlaus Goger return ret;
959536dfccSTor Krill }
969536dfccSTor Krill
9752280315SKlaus Goger tmp->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
9852280315SKlaus Goger tmp->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
9952280315SKlaus Goger tmp->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
10052280315SKlaus Goger tmp->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
10152280315SKlaus Goger tmp->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
10252280315SKlaus Goger tmp->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000;
10352280315SKlaus Goger tmp->tm_wday = bcd2bin(buf[RTC_DAY_REG_ADDR] & 0x07);
1049536dfccSTor Krill tmp->tm_yday = 0;
1059536dfccSTor Krill tmp->tm_isdst= 0;
1069536dfccSTor Krill
1079536dfccSTor Krill DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1089536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1099536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
110b73a19e1SYuri Tikhonov
11152280315SKlaus Goger return 0;
1129536dfccSTor Krill }
1139536dfccSTor Krill
1149536dfccSTor Krill /*
1159536dfccSTor Krill * Set the RTC
1169536dfccSTor Krill */
isl1208_rtc_set(struct udevice * dev,const struct rtc_time * tmp)11752280315SKlaus Goger static int isl1208_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
1189536dfccSTor Krill {
11952280315SKlaus Goger int ret;
12052280315SKlaus Goger uchar val, buf[7];
12152280315SKlaus Goger
1229536dfccSTor Krill DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1239536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1249536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
1259536dfccSTor Krill
12652280315SKlaus Goger if (tmp->tm_year < 2000 || tmp->tm_year > 2099)
12752280315SKlaus Goger printf("WARNING: year should be between 2000 and 2099!\n");
1289536dfccSTor Krill
12952280315SKlaus Goger /* enable write */
13052280315SKlaus Goger ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
13152280315SKlaus Goger if (ret < 0)
13252280315SKlaus Goger return ret;
13352280315SKlaus Goger
13452280315SKlaus Goger val = val | RTC_STAT_BIT_WRTC;
13552280315SKlaus Goger
13652280315SKlaus Goger ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
13752280315SKlaus Goger if (ret < 0)
13852280315SKlaus Goger return ret;
13952280315SKlaus Goger
14052280315SKlaus Goger buf[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100);
14152280315SKlaus Goger buf[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon);
14252280315SKlaus Goger buf[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday);
14352280315SKlaus Goger buf[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday);
14452280315SKlaus Goger buf[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour) | 0x80; /* 24h clock */
14552280315SKlaus Goger buf[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min);
14652280315SKlaus Goger buf[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec);
14752280315SKlaus Goger
14852280315SKlaus Goger ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
14952280315SKlaus Goger if (ret < 0)
15052280315SKlaus Goger return ret;
1519536dfccSTor Krill
1529536dfccSTor Krill /* disable write */
15352280315SKlaus Goger ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
15452280315SKlaus Goger if (ret < 0)
15552280315SKlaus Goger return ret;
15652280315SKlaus Goger
15752280315SKlaus Goger val = val & ~RTC_STAT_BIT_WRTC;
15852280315SKlaus Goger ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
15952280315SKlaus Goger if (ret < 0)
16052280315SKlaus Goger return ret;
161d1e23194SJean-Christophe PLAGNIOL-VILLARD
162d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0;
1639536dfccSTor Krill }
1649536dfccSTor Krill
isl1208_rtc_reset(struct udevice * dev)16552280315SKlaus Goger static int isl1208_rtc_reset(struct udevice *dev)
1669536dfccSTor Krill {
16752280315SKlaus Goger return 0;
1689536dfccSTor Krill }
1699536dfccSTor Krill
isl1208_probe(struct udevice * dev)17052280315SKlaus Goger static int isl1208_probe(struct udevice *dev)
1719536dfccSTor Krill {
17252280315SKlaus Goger i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
17352280315SKlaus Goger DM_I2C_CHIP_WR_ADDRESS);
17452280315SKlaus Goger
17552280315SKlaus Goger return 0;
1769536dfccSTor Krill }
1779536dfccSTor Krill
17852280315SKlaus Goger static const struct rtc_ops isl1208_rtc_ops = {
17952280315SKlaus Goger .get = isl1208_rtc_get,
18052280315SKlaus Goger .set = isl1208_rtc_set,
18152280315SKlaus Goger .reset = isl1208_rtc_reset,
182*4a094725STrent Piepho .read8 = isl1208_rtc_read8,
183*4a094725STrent Piepho .write8 = isl1208_rtc_write8,
18452280315SKlaus Goger };
18552280315SKlaus Goger
18652280315SKlaus Goger static const struct udevice_id isl1208_rtc_ids[] = {
18752280315SKlaus Goger { .compatible = "isil,isl1208" },
18852280315SKlaus Goger { }
18952280315SKlaus Goger };
19052280315SKlaus Goger
19152280315SKlaus Goger U_BOOT_DRIVER(rtc_isl1208) = {
19252280315SKlaus Goger .name = "rtc-isl1208",
19352280315SKlaus Goger .id = UCLASS_RTC,
19452280315SKlaus Goger .probe = isl1208_probe,
19552280315SKlaus Goger .of_match = isl1208_rtc_ids,
19652280315SKlaus Goger .ops = &isl1208_rtc_ops,
19752280315SKlaus Goger };
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