xref: /openbmc/u-boot/drivers/rtc/ds1306.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
20c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
30c698dcaSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
40c698dcaSJean-Christophe PLAGNIOL-VILLARD  *
50c698dcaSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
60c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Stephan Linz <linz@li-pro.net>
70c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
80c698dcaSJean-Christophe PLAGNIOL-VILLARD 
90c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
100c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Date & Time support for DS1306 RTC using SPI:
110c698dcaSJean-Christophe PLAGNIOL-VILLARD  *
120c698dcaSJean-Christophe PLAGNIOL-VILLARD  *    - SXNI855T:    it uses its own soft SPI here in this file
130c698dcaSJean-Christophe PLAGNIOL-VILLARD  *    - all other:   use the external spi_xfer() function
140c698dcaSJean-Christophe PLAGNIOL-VILLARD  *                   (see include/spi.h)
150c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
160c698dcaSJean-Christophe PLAGNIOL-VILLARD 
170c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
180c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h>
190c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h>
200c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <spi.h>
210c698dcaSJean-Christophe PLAGNIOL-VILLARD 
22871c18ddSMichal Simek #if defined(CONFIG_CMD_DATE)
230c698dcaSJean-Christophe PLAGNIOL-VILLARD 
240c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS		0x00
250c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES		0x01
260c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS		0x02
270c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK		0x03
280c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DATE_OF_MONTH	0x04
290c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MONTH		0x05
300c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_YEAR		0x06
310c698dcaSJean-Christophe PLAGNIOL-VILLARD 
320c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS_ALARM0	0x07
330c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES_ALARM0	0x08
340c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS_ALARM0	0x09
350c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK_ALARM0	0x0a
360c698dcaSJean-Christophe PLAGNIOL-VILLARD 
370c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS_ALARM1	0x0b
380c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES_ALARM1	0x0c
390c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS_ALARM1	0x0d
400c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK_ALARM1	0x0e
410c698dcaSJean-Christophe PLAGNIOL-VILLARD 
420c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_CONTROL		0x0f
430c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_STATUS		0x10
440c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_TRICKLE_CHARGER	0x11
450c698dcaSJean-Christophe PLAGNIOL-VILLARD 
460c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_USER_RAM_BASE	0x20
470c698dcaSJean-Christophe PLAGNIOL-VILLARD 
480c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ************************************************************************* */
490c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SXNI855T		/* !!! SHOULD BE CHANGED TO NEW CODE !!! */
500c698dcaSJean-Christophe PLAGNIOL-VILLARD 
510c698dcaSJean-Christophe PLAGNIOL-VILLARD static void soft_spi_send (unsigned char n);
520c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char soft_spi_read (void);
530c698dcaSJean-Christophe PLAGNIOL-VILLARD static void init_spi (void);
540c698dcaSJean-Christophe PLAGNIOL-VILLARD 
550c698dcaSJean-Christophe PLAGNIOL-VILLARD /*-----------------------------------------------------------------------
560c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Definitions
570c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
580c698dcaSJean-Christophe PLAGNIOL-VILLARD 
590c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	PB_SPISCK	0x00000002	/* PB 30 */
600c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPIMOSI	0x00000004	/* PB 29 */
610c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPIMISO	0x00000008	/* PB 28 */
620c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPI_CE	0x00010000	/* PB 15 */
630c698dcaSJean-Christophe PLAGNIOL-VILLARD 
640c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
650c698dcaSJean-Christophe PLAGNIOL-VILLARD 
660c698dcaSJean-Christophe PLAGNIOL-VILLARD /* read clock time from DS1306 and return it in *tmp */
67b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
680c698dcaSJean-Christophe PLAGNIOL-VILLARD {
696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
700c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char spi_byte;	/* Data Byte */
710c698dcaSJean-Christophe PLAGNIOL-VILLARD 
720c698dcaSJean-Christophe PLAGNIOL-VILLARD 	init_spi ();		/* set port B for software SPI */
730c698dcaSJean-Christophe PLAGNIOL-VILLARD 
740c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the DS1306 RTC */
750c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
770c698dcaSJean-Christophe PLAGNIOL-VILLARD 
780c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Shift out the address (0) of the time in the Clock Chip */
790c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0);
800c698dcaSJean-Christophe PLAGNIOL-VILLARD 
810c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Put the clock readings into the rtc_time structure */
820c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_sec = bcd2bin (soft_spi_read ());	/* Read seconds */
830c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_min = bcd2bin (soft_spi_read ());	/* Read minutes */
840c698dcaSJean-Christophe PLAGNIOL-VILLARD 
850c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Hours are trickier */
860c698dcaSJean-Christophe PLAGNIOL-VILLARD 	spi_byte = soft_spi_read ();	/* Read Hours into temporary value */
870c698dcaSJean-Christophe PLAGNIOL-VILLARD 	if (spi_byte & 0x40) {
880c698dcaSJean-Christophe PLAGNIOL-VILLARD 		/* 12 hour mode bit is set (time is in 1-12 format) */
890c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (spi_byte & 0x20) {
900c698dcaSJean-Christophe PLAGNIOL-VILLARD 			/* since PM we add 11 to get 0-23 for hours */
910c698dcaSJean-Christophe PLAGNIOL-VILLARD 			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
920c698dcaSJean-Christophe PLAGNIOL-VILLARD 		} else {
930c698dcaSJean-Christophe PLAGNIOL-VILLARD 			/* since AM we subtract 1 to get 0-23 for hours */
940c698dcaSJean-Christophe PLAGNIOL-VILLARD 			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
950c698dcaSJean-Christophe PLAGNIOL-VILLARD 		}
960c698dcaSJean-Christophe PLAGNIOL-VILLARD 	} else {
970c698dcaSJean-Christophe PLAGNIOL-VILLARD 		/* Otherwise, 0-23 hour format */
980c698dcaSJean-Christophe PLAGNIOL-VILLARD 		tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
990c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
1000c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1010c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_read ();	/* Read and discard Day of week */
1020c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mday = bcd2bin (soft_spi_read ());	/* Read Day of the Month */
1030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mon = bcd2bin (soft_spi_read ());	/* Read Month */
1040c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Read Year and convert to this century */
1060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
1070c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can disable the DS1306 RTC */
1090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
1100c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1110c698dcaSJean-Christophe PLAGNIOL-VILLARD 
112199e87c3SSimon Glass 	rtc_calc_weekday(tmp);	/* Determine the day of week */
1130c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1140c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
1150c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1160c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
117b73a19e1SYuri Tikhonov 
118b73a19e1SYuri Tikhonov 	return 0;
1190c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1200c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1210c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
1220c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1230c698dcaSJean-Christophe PLAGNIOL-VILLARD /* set clock time in DS1306 RTC and in MPC8xx RTC */
124d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
1250c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
1270c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1280c698dcaSJean-Christophe PLAGNIOL-VILLARD 	init_spi ();		/* set port B for software SPI */
1290c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1300c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the DS1306 RTC */
1310c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
1320c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1330c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1340c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* First disable write protect in the clock chip control register */
1350c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x8F);	/* send address of the control register */
1360c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x00);	/* send control register contents */
1370c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1380c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now disable the DS1306 to terminate the write */
1390c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
1400c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1410c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1420c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now enable the DS1306 to initiate a new write */
1430c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
1440c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1450c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1460c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Next, send the address of the clock time write registers */
1470c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x80);	/* send address of the first time register */
1480c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1490c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Use Burst Mode to send all of the time data to the clock */
1500c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bin2bcd (tmp->tm_sec);
1510c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_sec));	/* Send Seconds */
1520c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_min));	/* Send Minutes */
1530c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_hour));	/* Send Hour */
1540c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_wday));	/* Send Day of the Week */
1550c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_mday));	/* Send Day of Month */
1560c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_mon));	/* Send Month */
1570c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_year - 2000));	/* Send Year */
1580c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1590c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can disable the Clock chip to terminate the burst write */
1600c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
1610c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1620c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1630c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the Clock chip to initiate a new write */
1640c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
1650c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1660c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1670c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* First we Enable write protect in the clock chip control register */
1680c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x8F);	/* send address of the control register */
1690c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x40);	/* send out Control Register contents */
1700c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1710c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now disable the DS1306 */
1720c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/*  Disable DS1306 Chip */
1730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1740c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1750c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Set standard MPC8xx clock to the same time so Linux will
1760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 * see the time even if it doesn't have a DS1306 clock driver.
1770c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 * This helps with experimenting with standard kernels.
1780c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 */
1790c698dcaSJean-Christophe PLAGNIOL-VILLARD 	{
1800c698dcaSJean-Christophe PLAGNIOL-VILLARD 		ulong tim;
1810c698dcaSJean-Christophe PLAGNIOL-VILLARD 
18271420983SSimon Glass 		tim = rtc_mktime(tmp);
1830c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1840c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_sitk.sitk_rtck = KAPWR_KEY;
1850c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_sit.sit_rtc = tim;
1860c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
1870c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1880c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
1890c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1900c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
191d1e23194SJean-Christophe PLAGNIOL-VILLARD 
192d1e23194SJean-Christophe PLAGNIOL-VILLARD 	return 0;
1930c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1940c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1950c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
1960c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1970c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Initialize Port B for software SPI */
1980c698dcaSJean-Christophe PLAGNIOL-VILLARD static void init_spi (void)
1990c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
2010c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2020c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Force output pins to begin at logic 0 */
2030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
2040c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Set these 3 signals as outputs */
2060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
2070c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdir &= ~PB_SPIMISO;	/* Make MISO pin an input */
2090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
2100c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2110c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2120c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2130c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2140c698dcaSJean-Christophe PLAGNIOL-VILLARD /* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
2150c698dcaSJean-Christophe PLAGNIOL-VILLARD static void soft_spi_send (unsigned char n)
2160c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
2180c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char bitpos;	/* bit position to receive */
2190c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char i;	/* Loop Control */
2200c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2210c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* bit position to send, start with most significant bit */
2220c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bitpos = 0x80;
2230c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2240c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Send 8 bits to software SPI */
2250c698dcaSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 8; i++) {	/* Loop for 8 bits */
2260c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */
2270c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2280c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (n & bitpos)
2290c698dcaSJean-Christophe PLAGNIOL-VILLARD 			immap->im_cpm.cp_pbdat |= PB_SPIMOSI;	/* Set MOSI to 1 */
2300c698dcaSJean-Christophe PLAGNIOL-VILLARD 		else
2310c698dcaSJean-Christophe PLAGNIOL-VILLARD 			immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI;	/* Set MOSI to 0 */
2320c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2330c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2340c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
2350c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2360c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2370c698dcaSJean-Christophe PLAGNIOL-VILLARD 		bitpos >>= 1;	/* Shift for next bit position */
2380c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
2390c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2400c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2410c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2420c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2430c698dcaSJean-Christophe PLAGNIOL-VILLARD /* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
2440c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char soft_spi_read (void)
2450c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
2470c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2480c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char spi_byte = 0;	/* Return value, assume success */
2490c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char bitpos;	/* bit position to receive */
2500c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char i;	/* Loop Control */
2510c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2520c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* bit position to receive, start with most significant bit */
2530c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bitpos = 0x80;
2540c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2550c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Read 8 bits here */
2560c698dcaSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 8; i++) {	/* Do 8 bits in loop */
2570c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */
2580c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2590c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (immap->im_cpm.cp_pbdat & PB_SPIMISO)	/* Get a bit of data */
2600c698dcaSJean-Christophe PLAGNIOL-VILLARD 			spi_byte |= bitpos;	/* Set data accordingly */
2610c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
2620c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2630c698dcaSJean-Christophe PLAGNIOL-VILLARD 		bitpos >>= 1;	/* Shift for next bit position */
2640c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
2650c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2660c698dcaSJean-Christophe PLAGNIOL-VILLARD 	return spi_byte;	/* Return the byte read */
2670c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2680c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2690c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2700c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2710c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void)
2720c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	return;			/* nothing to do */
2740c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2750c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2760c698dcaSJean-Christophe PLAGNIOL-VILLARD #else  /* not CONFIG_SXNI855T */
2770c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ************************************************************************* */
2780c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2790c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char rtc_read (unsigned char reg);
2800c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (unsigned char reg, unsigned char val);
2810c698dcaSJean-Christophe PLAGNIOL-VILLARD 
282d255bb0eSHaavard Skinnemoen static struct spi_slave *slave;
283d255bb0eSHaavard Skinnemoen 
2840c698dcaSJean-Christophe PLAGNIOL-VILLARD /* read clock time from DS1306 and return it in *tmp */
285b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
2860c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2870c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char sec, min, hour, mday, wday, mon, year;
2880c698dcaSJean-Christophe PLAGNIOL-VILLARD 
289d255bb0eSHaavard Skinnemoen 	/*
290d255bb0eSHaavard Skinnemoen 	 * Assuming Vcc = 2.0V (lowest speed)
291d255bb0eSHaavard Skinnemoen 	 *
292d255bb0eSHaavard Skinnemoen 	 * REVISIT: If we add an rtc_init() function we can do this
293d255bb0eSHaavard Skinnemoen 	 * step just once.
294d255bb0eSHaavard Skinnemoen 	 */
295d255bb0eSHaavard Skinnemoen 	if (!slave) {
2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
297d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
298d255bb0eSHaavard Skinnemoen 		if (!slave)
299d255bb0eSHaavard Skinnemoen 			return;
300d255bb0eSHaavard Skinnemoen 	}
301d255bb0eSHaavard Skinnemoen 
302d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
303d255bb0eSHaavard Skinnemoen 		return;
304d255bb0eSHaavard Skinnemoen 
3050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	sec = rtc_read (RTC_SECONDS);
3060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	min = rtc_read (RTC_MINUTES);
3070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	hour = rtc_read (RTC_HOURS);
3080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	mday = rtc_read (RTC_DATE_OF_MONTH);
3090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	wday = rtc_read (RTC_DAY_OF_WEEK);
3100c698dcaSJean-Christophe PLAGNIOL-VILLARD 	mon = rtc_read (RTC_MONTH);
3110c698dcaSJean-Christophe PLAGNIOL-VILLARD 	year = rtc_read (RTC_YEAR);
3120c698dcaSJean-Christophe PLAGNIOL-VILLARD 
313d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
314d255bb0eSHaavard Skinnemoen 
3150c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
3160c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       "hr: %02x min: %02x sec: %02x\n",
3170c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       year, mon, mday, wday, hour, min, sec);
3180c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
3190c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_DAY_OF_WEEK_ALARM0),
3200c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_HOURS_ALARM0),
3210c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
3220c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
3230c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_DAY_OF_WEEK_ALARM1),
3240c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_HOURS_ALARM1),
3250c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
3260c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3270c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_sec = bcd2bin (sec & 0x7F);	/* convert Seconds */
3280c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_min = bcd2bin (min & 0x7F);	/* convert Minutes */
3290c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3300c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* convert Hours */
3310c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_hour = (hour & 0x40)
3320c698dcaSJean-Christophe PLAGNIOL-VILLARD 		? ((hour & 0x20)	/* 12 hour mode */
3330c698dcaSJean-Christophe PLAGNIOL-VILLARD 		   ? bcd2bin (hour & 0x1F) + 11	/* PM */
3340c698dcaSJean-Christophe PLAGNIOL-VILLARD 		   : bcd2bin (hour & 0x1F) - 1	/* AM */
3350c698dcaSJean-Christophe PLAGNIOL-VILLARD 		)
3360c698dcaSJean-Christophe PLAGNIOL-VILLARD 		: bcd2bin (hour & 0x3F);	/* 24 hour mode */
3370c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3380c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mday = bcd2bin (mday & 0x3F);	/* convert Day of the Month */
3390c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mon = bcd2bin (mon & 0x1F);	/* convert Month */
3400c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_year = bcd2bin (year) + 2000;	/* convert Year */
3410c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_wday = bcd2bin (wday & 0x07) - 1;	/* convert Day of the Week */
3420c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_yday = 0;
3430c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_isdst = 0;
3440c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3450c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
3460c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
3470c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
348b73a19e1SYuri Tikhonov 
349b73a19e1SYuri Tikhonov 	return 0;
3500c698dcaSJean-Christophe PLAGNIOL-VILLARD }
3510c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3520c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
3530c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3540c698dcaSJean-Christophe PLAGNIOL-VILLARD /* set clock time from *tmp in DS1306 RTC */
355d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
3560c698dcaSJean-Christophe PLAGNIOL-VILLARD {
357d255bb0eSHaavard Skinnemoen 	/* Assuming Vcc = 2.0V (lowest speed) */
358d255bb0eSHaavard Skinnemoen 	if (!slave) {
3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
360d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
361d255bb0eSHaavard Skinnemoen 		if (!slave)
362d255bb0eSHaavard Skinnemoen 			return;
363d255bb0eSHaavard Skinnemoen 	}
364d255bb0eSHaavard Skinnemoen 
365d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
366d255bb0eSHaavard Skinnemoen 		return;
367d255bb0eSHaavard Skinnemoen 
3680c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
3690c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
3700c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
3710c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3720c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
3730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
3740c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
3750c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
3760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
3770c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
3780c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
379d255bb0eSHaavard Skinnemoen 
380d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
3810c698dcaSJean-Christophe PLAGNIOL-VILLARD }
3820c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3830c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
3840c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3850c698dcaSJean-Christophe PLAGNIOL-VILLARD /* reset the DS1306 */
3860c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void)
3870c698dcaSJean-Christophe PLAGNIOL-VILLARD {
388d255bb0eSHaavard Skinnemoen 	/* Assuming Vcc = 2.0V (lowest speed) */
389d255bb0eSHaavard Skinnemoen 	if (!slave) {
3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
391d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
392d255bb0eSHaavard Skinnemoen 		if (!slave)
393d255bb0eSHaavard Skinnemoen 			return;
394d255bb0eSHaavard Skinnemoen 	}
395d255bb0eSHaavard Skinnemoen 
396d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
397d255bb0eSHaavard Skinnemoen 		return;
398d255bb0eSHaavard Skinnemoen 
3990c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* clear the control register */
4000c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_CONTROL, 0x00);	/* 1st step: reset WP */
4010c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_CONTROL, 0x00);	/* 2nd step: reset 1Hz, AIE1, AIE0 */
4020c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* reset all alarms */
4040c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS_ALARM0, 0x00);
4050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS_ALARM1, 0x00);
4060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES_ALARM0, 0x00);
4070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES_ALARM1, 0x00);
4080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS_ALARM0, 0x00);
4090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS_ALARM1, 0x00);
4100c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
4110c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
412d255bb0eSHaavard Skinnemoen 
413d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
4140c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4150c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4160c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
4170c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4180c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char rtc_read (unsigned char reg)
4190c698dcaSJean-Christophe PLAGNIOL-VILLARD {
420d255bb0eSHaavard Skinnemoen 	int ret;
4210c698dcaSJean-Christophe PLAGNIOL-VILLARD 
422d255bb0eSHaavard Skinnemoen 	ret = spi_w8r8(slave, reg);
423d255bb0eSHaavard Skinnemoen 	return ret < 0 ? 0 : ret;
4240c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4250c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4260c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
4270c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4280c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (unsigned char reg, unsigned char val)
4290c698dcaSJean-Christophe PLAGNIOL-VILLARD {
4300c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char dout[2];	/* SPI Output Data Bytes */
4310c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char din[2];	/* SPI Input Data Bytes */
4320c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4330c698dcaSJean-Christophe PLAGNIOL-VILLARD 	dout[0] = 0x80 | reg;
4340c698dcaSJean-Christophe PLAGNIOL-VILLARD 	dout[1] = val;
4350c698dcaSJean-Christophe PLAGNIOL-VILLARD 
436d255bb0eSHaavard Skinnemoen 	spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
4370c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4380c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4390c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
4400c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4410c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
442