xref: /openbmc/u-boot/drivers/rtc/ds1306.c (revision 406fd7e207d3593f150079514a371dccdc651ce7)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
20c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
30c698dcaSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
40c698dcaSJean-Christophe PLAGNIOL-VILLARD  *
50c698dcaSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
60c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Stephan Linz <linz@li-pro.net>
70c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
80c698dcaSJean-Christophe PLAGNIOL-VILLARD 
90c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
100c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Date & Time support for DS1306 RTC using SPI:
110c698dcaSJean-Christophe PLAGNIOL-VILLARD  *
120c698dcaSJean-Christophe PLAGNIOL-VILLARD  *    - SXNI855T:    it uses its own soft SPI here in this file
130c698dcaSJean-Christophe PLAGNIOL-VILLARD  *    - all other:   use the external spi_xfer() function
140c698dcaSJean-Christophe PLAGNIOL-VILLARD  *                   (see include/spi.h)
150c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
160c698dcaSJean-Christophe PLAGNIOL-VILLARD 
170c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
180c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h>
190c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h>
200c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <spi.h>
210c698dcaSJean-Christophe PLAGNIOL-VILLARD 
220c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS		0x00
230c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES		0x01
240c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS		0x02
250c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK		0x03
260c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DATE_OF_MONTH	0x04
270c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MONTH		0x05
280c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_YEAR		0x06
290c698dcaSJean-Christophe PLAGNIOL-VILLARD 
300c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS_ALARM0	0x07
310c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES_ALARM0	0x08
320c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS_ALARM0	0x09
330c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK_ALARM0	0x0a
340c698dcaSJean-Christophe PLAGNIOL-VILLARD 
350c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_SECONDS_ALARM1	0x0b
360c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_MINUTES_ALARM1	0x0c
370c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_HOURS_ALARM1	0x0d
380c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_DAY_OF_WEEK_ALARM1	0x0e
390c698dcaSJean-Christophe PLAGNIOL-VILLARD 
400c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_CONTROL		0x0f
410c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_STATUS		0x10
420c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_TRICKLE_CHARGER	0x11
430c698dcaSJean-Christophe PLAGNIOL-VILLARD 
440c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	RTC_USER_RAM_BASE	0x20
450c698dcaSJean-Christophe PLAGNIOL-VILLARD 
460c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ************************************************************************* */
470c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SXNI855T		/* !!! SHOULD BE CHANGED TO NEW CODE !!! */
480c698dcaSJean-Christophe PLAGNIOL-VILLARD 
490c698dcaSJean-Christophe PLAGNIOL-VILLARD static void soft_spi_send (unsigned char n);
500c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char soft_spi_read (void);
510c698dcaSJean-Christophe PLAGNIOL-VILLARD static void init_spi (void);
520c698dcaSJean-Christophe PLAGNIOL-VILLARD 
530c698dcaSJean-Christophe PLAGNIOL-VILLARD /*-----------------------------------------------------------------------
540c698dcaSJean-Christophe PLAGNIOL-VILLARD  * Definitions
550c698dcaSJean-Christophe PLAGNIOL-VILLARD  */
560c698dcaSJean-Christophe PLAGNIOL-VILLARD 
570c698dcaSJean-Christophe PLAGNIOL-VILLARD #define	PB_SPISCK	0x00000002	/* PB 30 */
580c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPIMOSI	0x00000004	/* PB 29 */
590c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPIMISO	0x00000008	/* PB 28 */
600c698dcaSJean-Christophe PLAGNIOL-VILLARD #define PB_SPI_CE	0x00010000	/* PB 15 */
610c698dcaSJean-Christophe PLAGNIOL-VILLARD 
620c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
630c698dcaSJean-Christophe PLAGNIOL-VILLARD 
640c698dcaSJean-Christophe PLAGNIOL-VILLARD /* read clock time from DS1306 and return it in *tmp */
rtc_get(struct rtc_time * tmp)65b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
660c698dcaSJean-Christophe PLAGNIOL-VILLARD {
676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
680c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char spi_byte;	/* Data Byte */
690c698dcaSJean-Christophe PLAGNIOL-VILLARD 
700c698dcaSJean-Christophe PLAGNIOL-VILLARD 	init_spi ();		/* set port B for software SPI */
710c698dcaSJean-Christophe PLAGNIOL-VILLARD 
720c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the DS1306 RTC */
730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
740c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
750c698dcaSJean-Christophe PLAGNIOL-VILLARD 
760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Shift out the address (0) of the time in the Clock Chip */
770c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0);
780c698dcaSJean-Christophe PLAGNIOL-VILLARD 
790c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Put the clock readings into the rtc_time structure */
800c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_sec = bcd2bin (soft_spi_read ());	/* Read seconds */
810c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_min = bcd2bin (soft_spi_read ());	/* Read minutes */
820c698dcaSJean-Christophe PLAGNIOL-VILLARD 
830c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Hours are trickier */
840c698dcaSJean-Christophe PLAGNIOL-VILLARD 	spi_byte = soft_spi_read ();	/* Read Hours into temporary value */
850c698dcaSJean-Christophe PLAGNIOL-VILLARD 	if (spi_byte & 0x40) {
860c698dcaSJean-Christophe PLAGNIOL-VILLARD 		/* 12 hour mode bit is set (time is in 1-12 format) */
870c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (spi_byte & 0x20) {
880c698dcaSJean-Christophe PLAGNIOL-VILLARD 			/* since PM we add 11 to get 0-23 for hours */
890c698dcaSJean-Christophe PLAGNIOL-VILLARD 			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
900c698dcaSJean-Christophe PLAGNIOL-VILLARD 		} else {
910c698dcaSJean-Christophe PLAGNIOL-VILLARD 			/* since AM we subtract 1 to get 0-23 for hours */
920c698dcaSJean-Christophe PLAGNIOL-VILLARD 			tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
930c698dcaSJean-Christophe PLAGNIOL-VILLARD 		}
940c698dcaSJean-Christophe PLAGNIOL-VILLARD 	} else {
950c698dcaSJean-Christophe PLAGNIOL-VILLARD 		/* Otherwise, 0-23 hour format */
960c698dcaSJean-Christophe PLAGNIOL-VILLARD 		tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
970c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
980c698dcaSJean-Christophe PLAGNIOL-VILLARD 
990c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_read ();	/* Read and discard Day of week */
1000c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mday = bcd2bin (soft_spi_read ());	/* Read Day of the Month */
1010c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mon = bcd2bin (soft_spi_read ());	/* Read Month */
1020c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Read Year and convert to this century */
1040c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
1050c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can disable the DS1306 RTC */
1070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
1080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1090c698dcaSJean-Christophe PLAGNIOL-VILLARD 
110199e87c3SSimon Glass 	rtc_calc_weekday(tmp);	/* Determine the day of week */
1110c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1120c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
1130c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1140c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
115b73a19e1SYuri Tikhonov 
116b73a19e1SYuri Tikhonov 	return 0;
1170c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1180c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1190c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
1200c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1210c698dcaSJean-Christophe PLAGNIOL-VILLARD /* set clock time in DS1306 RTC and in MPC8xx RTC */
rtc_set(struct rtc_time * tmp)122d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
1230c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
1250c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1260c698dcaSJean-Christophe PLAGNIOL-VILLARD 	init_spi ();		/* set port B for software SPI */
1270c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1280c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the DS1306 RTC */
1290c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
1300c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1310c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1320c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* First disable write protect in the clock chip control register */
1330c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x8F);	/* send address of the control register */
1340c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x00);	/* send control register contents */
1350c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1360c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now disable the DS1306 to terminate the write */
1370c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
1380c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1390c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1400c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now enable the DS1306 to initiate a new write */
1410c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;
1420c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1430c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1440c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Next, send the address of the clock time write registers */
1450c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x80);	/* send address of the first time register */
1460c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1470c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Use Burst Mode to send all of the time data to the clock */
1480c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bin2bcd (tmp->tm_sec);
1490c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_sec));	/* Send Seconds */
1500c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_min));	/* Send Minutes */
1510c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_hour));	/* Send Hour */
1520c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_wday));	/* Send Day of the Week */
1530c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_mday));	/* Send Day of Month */
1540c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_mon));	/* Send Month */
1550c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (bin2bcd (tmp->tm_year - 2000));	/* Send Year */
1560c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1570c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can disable the Clock chip to terminate the burst write */
1580c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/* Disable DS1306 Chip */
1590c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1600c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1610c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now we can enable the Clock chip to initiate a new write */
1620c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat |= PB_SPI_CE;	/* Enable DS1306 Chip */
1630c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1640c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1650c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* First we Enable write protect in the clock chip control register */
1660c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x8F);	/* send address of the control register */
1670c698dcaSJean-Christophe PLAGNIOL-VILLARD 	soft_spi_send (0x40);	/* send out Control Register contents */
1680c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1690c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Now disable the DS1306 */
1700c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;	/*  Disable DS1306 Chip */
1710c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
1720c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Set standard MPC8xx clock to the same time so Linux will
1740c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 * see the time even if it doesn't have a DS1306 clock driver.
1750c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 * This helps with experimenting with standard kernels.
1760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	 */
1770c698dcaSJean-Christophe PLAGNIOL-VILLARD 	{
1780c698dcaSJean-Christophe PLAGNIOL-VILLARD 		ulong tim;
1790c698dcaSJean-Christophe PLAGNIOL-VILLARD 
18071420983SSimon Glass 		tim = rtc_mktime(tmp);
1810c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1820c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_sitk.sitk_rtck = KAPWR_KEY;
1830c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_sit.sit_rtc = tim;
1840c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
1850c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1860c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
1870c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1880c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
189d1e23194SJean-Christophe PLAGNIOL-VILLARD 
190d1e23194SJean-Christophe PLAGNIOL-VILLARD 	return 0;
1910c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1920c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1930c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
1940c698dcaSJean-Christophe PLAGNIOL-VILLARD 
1950c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Initialize Port B for software SPI */
init_spi(void)1960c698dcaSJean-Christophe PLAGNIOL-VILLARD static void init_spi (void)
1970c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
1990c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2000c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Force output pins to begin at logic 0 */
2010c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
2020c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Set these 3 signals as outputs */
2040c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
2050c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	immap->im_cpm.cp_pbdir &= ~PB_SPIMISO;	/* Make MISO pin an input */
2070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	udelay (10);
2080c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2090c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2100c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2110c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2120c698dcaSJean-Christophe PLAGNIOL-VILLARD /* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
soft_spi_send(unsigned char n)2130c698dcaSJean-Christophe PLAGNIOL-VILLARD static void soft_spi_send (unsigned char n)
2140c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
2160c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char bitpos;	/* bit position to receive */
2170c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char i;	/* Loop Control */
2180c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2190c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* bit position to send, start with most significant bit */
2200c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bitpos = 0x80;
2210c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2220c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Send 8 bits to software SPI */
2230c698dcaSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 8; i++) {	/* Loop for 8 bits */
2240c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */
2250c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2260c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (n & bitpos)
2270c698dcaSJean-Christophe PLAGNIOL-VILLARD 			immap->im_cpm.cp_pbdat |= PB_SPIMOSI;	/* Set MOSI to 1 */
2280c698dcaSJean-Christophe PLAGNIOL-VILLARD 		else
2290c698dcaSJean-Christophe PLAGNIOL-VILLARD 			immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI;	/* Set MOSI to 0 */
2300c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2310c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2320c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
2330c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2340c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2350c698dcaSJean-Christophe PLAGNIOL-VILLARD 		bitpos >>= 1;	/* Shift for next bit position */
2360c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
2370c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2380c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2390c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2400c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2410c698dcaSJean-Christophe PLAGNIOL-VILLARD /* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
soft_spi_read(void)2420c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char soft_spi_read (void)
2430c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
2450c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2460c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char spi_byte = 0;	/* Return value, assume success */
2470c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char bitpos;	/* bit position to receive */
2480c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char i;	/* Loop Control */
2490c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2500c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* bit position to receive, start with most significant bit */
2510c698dcaSJean-Christophe PLAGNIOL-VILLARD 	bitpos = 0x80;
2520c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2530c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* Read 8 bits here */
2540c698dcaSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 8; i++) {	/* Do 8 bits in loop */
2550c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat |= PB_SPISCK;	/* Raise SCK */
2560c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2570c698dcaSJean-Christophe PLAGNIOL-VILLARD 		if (immap->im_cpm.cp_pbdat & PB_SPIMISO)	/* Get a bit of data */
2580c698dcaSJean-Christophe PLAGNIOL-VILLARD 			spi_byte |= bitpos;	/* Set data accordingly */
2590c698dcaSJean-Christophe PLAGNIOL-VILLARD 		immap->im_cpm.cp_pbdat &= ~PB_SPISCK;	/* Lower SCK */
2600c698dcaSJean-Christophe PLAGNIOL-VILLARD 		udelay (10);
2610c698dcaSJean-Christophe PLAGNIOL-VILLARD 		bitpos >>= 1;	/* Shift for next bit position */
2620c698dcaSJean-Christophe PLAGNIOL-VILLARD 	}
2630c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2640c698dcaSJean-Christophe PLAGNIOL-VILLARD 	return spi_byte;	/* Return the byte read */
2650c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2660c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2670c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
2680c698dcaSJean-Christophe PLAGNIOL-VILLARD 
rtc_reset(void)2690c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void)
2700c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2710c698dcaSJean-Christophe PLAGNIOL-VILLARD 	return;			/* nothing to do */
2720c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2730c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2740c698dcaSJean-Christophe PLAGNIOL-VILLARD #else  /* not CONFIG_SXNI855T */
2750c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ************************************************************************* */
2760c698dcaSJean-Christophe PLAGNIOL-VILLARD 
2770c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char rtc_read (unsigned char reg);
2780c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (unsigned char reg, unsigned char val);
2790c698dcaSJean-Christophe PLAGNIOL-VILLARD 
280d255bb0eSHaavard Skinnemoen static struct spi_slave *slave;
281d255bb0eSHaavard Skinnemoen 
2820c698dcaSJean-Christophe PLAGNIOL-VILLARD /* read clock time from DS1306 and return it in *tmp */
rtc_get(struct rtc_time * tmp)283b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
2840c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2850c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char sec, min, hour, mday, wday, mon, year;
2860c698dcaSJean-Christophe PLAGNIOL-VILLARD 
287d255bb0eSHaavard Skinnemoen 	/*
288d255bb0eSHaavard Skinnemoen 	 * Assuming Vcc = 2.0V (lowest speed)
289d255bb0eSHaavard Skinnemoen 	 *
290d255bb0eSHaavard Skinnemoen 	 * REVISIT: If we add an rtc_init() function we can do this
291d255bb0eSHaavard Skinnemoen 	 * step just once.
292d255bb0eSHaavard Skinnemoen 	 */
293d255bb0eSHaavard Skinnemoen 	if (!slave) {
2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
295d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
296d255bb0eSHaavard Skinnemoen 		if (!slave)
297d255bb0eSHaavard Skinnemoen 			return;
298d255bb0eSHaavard Skinnemoen 	}
299d255bb0eSHaavard Skinnemoen 
300d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
301d255bb0eSHaavard Skinnemoen 		return;
302d255bb0eSHaavard Skinnemoen 
3030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	sec = rtc_read (RTC_SECONDS);
3040c698dcaSJean-Christophe PLAGNIOL-VILLARD 	min = rtc_read (RTC_MINUTES);
3050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	hour = rtc_read (RTC_HOURS);
3060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	mday = rtc_read (RTC_DATE_OF_MONTH);
3070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	wday = rtc_read (RTC_DAY_OF_WEEK);
3080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	mon = rtc_read (RTC_MONTH);
3090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	year = rtc_read (RTC_YEAR);
3100c698dcaSJean-Christophe PLAGNIOL-VILLARD 
311d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
312d255bb0eSHaavard Skinnemoen 
3130c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
3140c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       "hr: %02x min: %02x sec: %02x\n",
3150c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       year, mon, mday, wday, hour, min, sec);
3160c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
3170c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_DAY_OF_WEEK_ALARM0),
3180c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_HOURS_ALARM0),
3190c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
3200c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
3210c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_DAY_OF_WEEK_ALARM1),
3220c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_HOURS_ALARM1),
3230c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
3240c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3250c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_sec = bcd2bin (sec & 0x7F);	/* convert Seconds */
3260c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_min = bcd2bin (min & 0x7F);	/* convert Minutes */
3270c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3280c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* convert Hours */
3290c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_hour = (hour & 0x40)
3300c698dcaSJean-Christophe PLAGNIOL-VILLARD 		? ((hour & 0x20)	/* 12 hour mode */
3310c698dcaSJean-Christophe PLAGNIOL-VILLARD 		   ? bcd2bin (hour & 0x1F) + 11	/* PM */
3320c698dcaSJean-Christophe PLAGNIOL-VILLARD 		   : bcd2bin (hour & 0x1F) - 1	/* AM */
3330c698dcaSJean-Christophe PLAGNIOL-VILLARD 		)
3340c698dcaSJean-Christophe PLAGNIOL-VILLARD 		: bcd2bin (hour & 0x3F);	/* 24 hour mode */
3350c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3360c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mday = bcd2bin (mday & 0x3F);	/* convert Day of the Month */
3370c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_mon = bcd2bin (mon & 0x1F);	/* convert Month */
3380c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_year = bcd2bin (year) + 2000;	/* convert Year */
3390c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_wday = bcd2bin (wday & 0x07) - 1;	/* convert Day of the Week */
3400c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_yday = 0;
3410c698dcaSJean-Christophe PLAGNIOL-VILLARD 	tmp->tm_isdst = 0;
3420c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3430c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
3440c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
3450c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
346b73a19e1SYuri Tikhonov 
347b73a19e1SYuri Tikhonov 	return 0;
3480c698dcaSJean-Christophe PLAGNIOL-VILLARD }
3490c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3500c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
3510c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3520c698dcaSJean-Christophe PLAGNIOL-VILLARD /* set clock time from *tmp in DS1306 RTC */
rtc_set(struct rtc_time * tmp)353d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
3540c698dcaSJean-Christophe PLAGNIOL-VILLARD {
355d255bb0eSHaavard Skinnemoen 	/* Assuming Vcc = 2.0V (lowest speed) */
356d255bb0eSHaavard Skinnemoen 	if (!slave) {
3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
358d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
359d255bb0eSHaavard Skinnemoen 		if (!slave)
360d255bb0eSHaavard Skinnemoen 			return;
361d255bb0eSHaavard Skinnemoen 	}
362d255bb0eSHaavard Skinnemoen 
363d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
364d255bb0eSHaavard Skinnemoen 		return;
365d255bb0eSHaavard Skinnemoen 
3660c698dcaSJean-Christophe PLAGNIOL-VILLARD 	debug ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
3670c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
3680c698dcaSJean-Christophe PLAGNIOL-VILLARD 	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
3690c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3700c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
3710c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
3720c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
3730c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
3740c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
3750c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
3760c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
377d255bb0eSHaavard Skinnemoen 
378d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
3790c698dcaSJean-Christophe PLAGNIOL-VILLARD }
3800c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3810c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
3820c698dcaSJean-Christophe PLAGNIOL-VILLARD 
3830c698dcaSJean-Christophe PLAGNIOL-VILLARD /* reset the DS1306 */
rtc_reset(void)3840c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void)
3850c698dcaSJean-Christophe PLAGNIOL-VILLARD {
386d255bb0eSHaavard Skinnemoen 	/* Assuming Vcc = 2.0V (lowest speed) */
387d255bb0eSHaavard Skinnemoen 	if (!slave) {
3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
389d255bb0eSHaavard Skinnemoen 				SPI_MODE_3 | SPI_CS_HIGH);
390d255bb0eSHaavard Skinnemoen 		if (!slave)
391d255bb0eSHaavard Skinnemoen 			return;
392d255bb0eSHaavard Skinnemoen 	}
393d255bb0eSHaavard Skinnemoen 
394d255bb0eSHaavard Skinnemoen 	if (spi_claim_bus(slave))
395d255bb0eSHaavard Skinnemoen 		return;
396d255bb0eSHaavard Skinnemoen 
3970c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* clear the control register */
3980c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_CONTROL, 0x00);	/* 1st step: reset WP */
3990c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_CONTROL, 0x00);	/* 2nd step: reset 1Hz, AIE1, AIE0 */
4000c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4010c698dcaSJean-Christophe PLAGNIOL-VILLARD 	/* reset all alarms */
4020c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS_ALARM0, 0x00);
4030c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_SECONDS_ALARM1, 0x00);
4040c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES_ALARM0, 0x00);
4050c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_MINUTES_ALARM1, 0x00);
4060c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS_ALARM0, 0x00);
4070c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_HOURS_ALARM1, 0x00);
4080c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
4090c698dcaSJean-Christophe PLAGNIOL-VILLARD 	rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
410d255bb0eSHaavard Skinnemoen 
411d255bb0eSHaavard Skinnemoen 	spi_release_bus(slave);
4120c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4130c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4140c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
4150c698dcaSJean-Christophe PLAGNIOL-VILLARD 
rtc_read(unsigned char reg)4160c698dcaSJean-Christophe PLAGNIOL-VILLARD static unsigned char rtc_read (unsigned char reg)
4170c698dcaSJean-Christophe PLAGNIOL-VILLARD {
418d255bb0eSHaavard Skinnemoen 	int ret;
4190c698dcaSJean-Christophe PLAGNIOL-VILLARD 
420d255bb0eSHaavard Skinnemoen 	ret = spi_w8r8(slave, reg);
421d255bb0eSHaavard Skinnemoen 	return ret < 0 ? 0 : ret;
4220c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4230c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4240c698dcaSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
4250c698dcaSJean-Christophe PLAGNIOL-VILLARD 
rtc_write(unsigned char reg,unsigned char val)4260c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (unsigned char reg, unsigned char val)
4270c698dcaSJean-Christophe PLAGNIOL-VILLARD {
4280c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char dout[2];	/* SPI Output Data Bytes */
4290c698dcaSJean-Christophe PLAGNIOL-VILLARD 	unsigned char din[2];	/* SPI Input Data Bytes */
4300c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4310c698dcaSJean-Christophe PLAGNIOL-VILLARD 	dout[0] = 0x80 | reg;
4320c698dcaSJean-Christophe PLAGNIOL-VILLARD 	dout[1] = val;
4330c698dcaSJean-Christophe PLAGNIOL-VILLARD 
434d255bb0eSHaavard Skinnemoen 	spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
4350c698dcaSJean-Christophe PLAGNIOL-VILLARD }
4360c698dcaSJean-Christophe PLAGNIOL-VILLARD 
4370c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
438