1 /* 2 * (C) Copyright 2017 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 #include <asm/arch/fmc.h> 14 #include <asm/arch/stm32.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 struct stm32_sdram_control { 19 u8 no_columns; 20 u8 no_rows; 21 u8 memory_width; 22 u8 no_banks; 23 u8 cas_latency; 24 u8 rd_burst; 25 u8 rd_pipe_delay; 26 }; 27 28 struct stm32_sdram_timing { 29 u8 tmrd; 30 u8 txsr; 31 u8 tras; 32 u8 trc; 33 u8 trp; 34 u8 trcd; 35 }; 36 struct stm32_sdram_params { 37 u8 no_sdram_banks; 38 struct stm32_sdram_control sdram_control; 39 struct stm32_sdram_timing sdram_timing; 40 }; 41 static inline u32 _ns2clk(u32 ns, u32 freq) 42 { 43 u32 tmp = freq/1000000; 44 return (tmp * ns) / 1000; 45 } 46 47 #define NS2CLK(ns) (_ns2clk(ns, freq)) 48 49 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) 50 51 #define SDRAM_MODE_BL_SHIFT 0 52 #define SDRAM_MODE_CAS_SHIFT 4 53 #define SDRAM_MODE_BL 0 54 #define SDRAM_MODE_CAS 3 55 56 #define SDRAM_TRDL 12 57 58 int stm32_sdram_init(struct udevice *dev) 59 { 60 u32 freq; 61 u32 sdram_twr; 62 struct stm32_sdram_params *params = dev_get_platdata(dev); 63 64 /* 65 * Get frequency for NS2CLK calculation. 66 */ 67 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 68 debug("%s, sdram freq = %d\n", __func__, freq); 69 70 /* Last data in to row precharge, need also comply ineq on page 1648 */ 71 sdram_twr = max( 72 max(SDRAM_TRDL, params->sdram_timing.tras 73 - params->sdram_timing.trcd), 74 params->sdram_timing.trc - params->sdram_timing.trcd 75 - params->sdram_timing.trp 76 ); 77 78 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 79 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT 80 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT 81 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT 82 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT 83 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT 84 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 85 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, 86 &STM32_SDRAM_FMC->sdcr1); 87 88 writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT 89 | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT 90 | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT 91 | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT 92 | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT 93 | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT 94 | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT, 95 &STM32_SDRAM_FMC->sdtr1); 96 97 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, 98 &STM32_SDRAM_FMC->sdcmr); 99 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 100 FMC_BUSY_WAIT(); 101 102 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, 103 &STM32_SDRAM_FMC->sdcmr); 104 udelay(100); 105 FMC_BUSY_WAIT(); 106 107 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH 108 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 109 udelay(100); 110 FMC_BUSY_WAIT(); 111 112 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 113 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 114 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 115 &STM32_SDRAM_FMC->sdcmr); 116 udelay(100); 117 FMC_BUSY_WAIT(); 118 119 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, 120 &STM32_SDRAM_FMC->sdcmr); 121 FMC_BUSY_WAIT(); 122 123 /* Refresh timer */ 124 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 125 126 return 0; 127 } 128 129 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 130 { 131 int ret; 132 int node = dev->of_offset; 133 const void *blob = gd->fdt_blob; 134 struct stm32_sdram_params *params = dev_get_platdata(dev); 135 136 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); 137 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 138 139 fdt_for_each_subnode(node, blob, node) { 140 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", 141 (u8 *)¶ms->sdram_control, 142 sizeof(params->sdram_control)); 143 if (ret) 144 return ret; 145 146 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", 147 (u8 *)¶ms->sdram_timing, 148 sizeof(params->sdram_timing)); 149 if (ret) 150 return ret; 151 } 152 153 return 0; 154 } 155 156 static int stm32_fmc_probe(struct udevice *dev) 157 { 158 #ifdef CONFIG_CLK 159 int ret; 160 struct clk clk; 161 162 ret = clk_get_by_index(dev, 0, &clk); 163 if (ret < 0) 164 return ret; 165 166 ret = clk_enable(&clk); 167 168 if (ret) { 169 dev_err(dev, "failed to enable clock\n"); 170 return ret; 171 } 172 #endif 173 ret = stm32_sdram_init(dev); 174 if (ret) 175 return ret; 176 177 return 0; 178 } 179 180 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 181 { 182 info->size = CONFIG_SYS_RAM_SIZE; 183 return 0; 184 } 185 186 static struct ram_ops stm32_fmc_ops = { 187 .get_info = stm32_fmc_get_info, 188 }; 189 190 static const struct udevice_id stm32_fmc_ids[] = { 191 { .compatible = "st,stm32-fmc" }, 192 { } 193 }; 194 195 U_BOOT_DRIVER(stm32_fmc) = { 196 .name = "stm32_fmc", 197 .id = UCLASS_RAM, 198 .of_match = stm32_fmc_ids, 199 .ops = &stm32_fmc_ops, 200 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 201 .probe = stm32_fmc_probe, 202 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 203 }; 204