1 /* 2 * (C) Copyright 2016-2017 Rockchip Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Adapted from coreboot. 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <ram.h> 14 #include <regmap.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sdram_common.h> 19 #include <asm/arch/sdram_rk3399.h> 20 #include <asm/arch/cru_rk3399.h> 21 #include <asm/arch/grf_rk3399.h> 22 #include <asm/arch/hardware.h> 23 #include <linux/err.h> 24 #include <time.h> 25 26 struct chan_info { 27 struct rk3399_ddr_pctl_regs *pctl; 28 struct rk3399_ddr_pi_regs *pi; 29 struct rk3399_ddr_publ_regs *publ; 30 struct rk3399_msch_regs *msch; 31 }; 32 33 struct dram_info { 34 #ifdef CONFIG_SPL_BUILD 35 struct chan_info chan[2]; 36 struct clk ddr_clk; 37 struct rk3399_cru *cru; 38 struct rk3399_pmucru *pmucru; 39 struct rk3399_pmusgrf_regs *pmusgrf; 40 struct rk3399_ddr_cic_regs *cic; 41 #endif 42 struct ram_info info; 43 struct rk3399_pmugrf_regs *pmugrf; 44 }; 45 46 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) 47 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) 48 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) 49 50 #define PHY_DRV_ODT_Hi_Z 0x0 51 #define PHY_DRV_ODT_240 0x1 52 #define PHY_DRV_ODT_120 0x8 53 #define PHY_DRV_ODT_80 0x9 54 #define PHY_DRV_ODT_60 0xc 55 #define PHY_DRV_ODT_48 0xd 56 #define PHY_DRV_ODT_40 0xe 57 #define PHY_DRV_ODT_34_3 0xf 58 59 #ifdef CONFIG_SPL_BUILD 60 61 struct rockchip_dmc_plat { 62 #if CONFIG_IS_ENABLED(OF_PLATDATA) 63 struct dtd_rockchip_rk3399_dmc dtplat; 64 #else 65 struct rk3399_sdram_params sdram_params; 66 #endif 67 struct regmap *map; 68 }; 69 70 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 71 { 72 int i; 73 74 for (i = 0; i < n / sizeof(u32); i++) { 75 writel(*src, dest); 76 src++; 77 dest++; 78 } 79 } 80 81 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, 82 u32 freq) 83 { 84 u32 *denali_phy = ddr_publ_regs->denali_phy; 85 86 /* From IP spec, only freq small than 125 can enter dll bypass mode */ 87 if (freq <= 125) { 88 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 89 setbits_le32(&denali_phy[86], (0x3 << 2) << 8); 90 setbits_le32(&denali_phy[214], (0x3 << 2) << 8); 91 setbits_le32(&denali_phy[342], (0x3 << 2) << 8); 92 setbits_le32(&denali_phy[470], (0x3 << 2) << 8); 93 94 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 95 setbits_le32(&denali_phy[547], (0x3 << 2) << 16); 96 setbits_le32(&denali_phy[675], (0x3 << 2) << 16); 97 setbits_le32(&denali_phy[803], (0x3 << 2) << 16); 98 } else { 99 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 100 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); 101 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); 102 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); 103 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); 104 105 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 106 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); 107 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); 108 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); 109 } 110 } 111 112 static void set_memory_map(const struct chan_info *chan, u32 channel, 113 const struct rk3399_sdram_params *sdram_params) 114 { 115 const struct rk3399_sdram_channel *sdram_ch = 116 &sdram_params->ch[channel]; 117 u32 *denali_ctl = chan->pctl->denali_ctl; 118 u32 *denali_pi = chan->pi->denali_pi; 119 u32 cs_map; 120 u32 reduc; 121 u32 row; 122 123 /* Get row number from ddrconfig setting */ 124 if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) 125 row = 16; 126 else if (sdram_ch->ddrconfig == 3) 127 row = 14; 128 else 129 row = 15; 130 131 cs_map = (sdram_ch->rank > 1) ? 3 : 1; 132 reduc = (sdram_ch->bw == 2) ? 0 : 1; 133 134 /* Set the dram configuration to ctrl */ 135 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); 136 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), 137 ((3 - sdram_ch->bk) << 16) | 138 ((16 - row) << 24)); 139 140 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), 141 cs_map | (reduc << 16)); 142 143 /* PI_199 PI_COL_DIFF:RW:0:4 */ 144 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); 145 146 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ 147 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), 148 ((3 - sdram_ch->bk) << 16) | 149 ((16 - row) << 24)); 150 /* PI_41 PI_CS_MAP:RW:24:4 */ 151 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); 152 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) 153 writel(0x2EC7FFFF, &denali_pi[34]); 154 } 155 156 static void set_ds_odt(const struct chan_info *chan, 157 const struct rk3399_sdram_params *sdram_params) 158 { 159 u32 *denali_phy = chan->publ->denali_phy; 160 161 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; 162 u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; 163 u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; 164 u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; 165 u32 reg_value; 166 167 if (sdram_params->base.dramtype == LPDDR4) { 168 tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; 169 tsel_wr_select_p = PHY_DRV_ODT_40; 170 ca_tsel_wr_select_p = PHY_DRV_ODT_40; 171 tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; 172 173 tsel_rd_select_n = PHY_DRV_ODT_240; 174 tsel_wr_select_n = PHY_DRV_ODT_40; 175 ca_tsel_wr_select_n = PHY_DRV_ODT_40; 176 tsel_idle_select_n = PHY_DRV_ODT_240; 177 } else if (sdram_params->base.dramtype == LPDDR3) { 178 tsel_rd_select_p = PHY_DRV_ODT_240; 179 tsel_wr_select_p = PHY_DRV_ODT_34_3; 180 ca_tsel_wr_select_p = PHY_DRV_ODT_48; 181 tsel_idle_select_p = PHY_DRV_ODT_240; 182 183 tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; 184 tsel_wr_select_n = PHY_DRV_ODT_34_3; 185 ca_tsel_wr_select_n = PHY_DRV_ODT_48; 186 tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; 187 } else { 188 tsel_rd_select_p = PHY_DRV_ODT_240; 189 tsel_wr_select_p = PHY_DRV_ODT_34_3; 190 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; 191 tsel_idle_select_p = PHY_DRV_ODT_240; 192 193 tsel_rd_select_n = PHY_DRV_ODT_240; 194 tsel_wr_select_n = PHY_DRV_ODT_34_3; 195 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; 196 tsel_idle_select_n = PHY_DRV_ODT_240; 197 } 198 199 if (sdram_params->base.odt == 1) 200 tsel_rd_en = 1; 201 else 202 tsel_rd_en = 0; 203 204 tsel_wr_en = 0; 205 tsel_idle_en = 0; 206 207 /* 208 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 209 * sets termination values for read/idle cycles and drive strength 210 * for write cycles for DQ/DM 211 */ 212 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | 213 (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | 214 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); 215 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); 216 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); 217 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); 218 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); 219 220 /* 221 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 222 * sets termination values for read/idle cycles and drive strength 223 * for write cycles for DQS 224 */ 225 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); 226 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); 227 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); 228 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); 229 230 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ 231 reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); 232 clrsetbits_le32(&denali_phy[544], 0xff, reg_value); 233 clrsetbits_le32(&denali_phy[672], 0xff, reg_value); 234 clrsetbits_le32(&denali_phy[800], 0xff, reg_value); 235 236 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ 237 clrsetbits_le32(&denali_phy[928], 0xff, reg_value); 238 239 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ 240 clrsetbits_le32(&denali_phy[937], 0xff, reg_value); 241 242 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ 243 clrsetbits_le32(&denali_phy[935], 0xff, reg_value); 244 245 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ 246 clrsetbits_le32(&denali_phy[939], 0xff, reg_value); 247 248 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ 249 clrsetbits_le32(&denali_phy[929], 0xff, reg_value); 250 251 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ 252 clrsetbits_le32(&denali_phy[924], 0xff, 253 tsel_wr_select_n | (tsel_wr_select_p << 4)); 254 clrsetbits_le32(&denali_phy[925], 0xff, 255 tsel_rd_select_n | (tsel_rd_select_p << 4)); 256 257 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ 258 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) 259 << 16; 260 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); 261 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); 262 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); 263 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); 264 265 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ 266 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) 267 << 24; 268 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); 269 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); 270 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); 271 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); 272 273 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ 274 reg_value = tsel_wr_en << 8; 275 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); 276 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); 277 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); 278 279 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ 280 reg_value = tsel_wr_en << 17; 281 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); 282 /* 283 * pad_rst/cke/cs/clk_term tsel 1bits 284 * DENALI_PHY_938/936/940/934 offset_17 285 */ 286 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); 287 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); 288 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); 289 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); 290 291 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ 292 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); 293 } 294 295 static int phy_io_config(const struct chan_info *chan, 296 const struct rk3399_sdram_params *sdram_params) 297 { 298 u32 *denali_phy = chan->publ->denali_phy; 299 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; 300 u32 mode_sel; 301 u32 reg_value; 302 u32 drv_value, odt_value; 303 u32 speed; 304 305 /* vref setting */ 306 if (sdram_params->base.dramtype == LPDDR4) { 307 /* LPDDR4 */ 308 vref_mode_dq = 0x6; 309 vref_value_dq = 0x1f; 310 vref_mode_ac = 0x6; 311 vref_value_ac = 0x1f; 312 } else if (sdram_params->base.dramtype == LPDDR3) { 313 if (sdram_params->base.odt == 1) { 314 vref_mode_dq = 0x5; /* LPDDR3 ODT */ 315 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; 316 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; 317 if (drv_value == PHY_DRV_ODT_48) { 318 switch (odt_value) { 319 case PHY_DRV_ODT_240: 320 vref_value_dq = 0x16; 321 break; 322 case PHY_DRV_ODT_120: 323 vref_value_dq = 0x26; 324 break; 325 case PHY_DRV_ODT_60: 326 vref_value_dq = 0x36; 327 break; 328 default: 329 debug("Invalid ODT value.\n"); 330 return -EINVAL; 331 } 332 } else if (drv_value == PHY_DRV_ODT_40) { 333 switch (odt_value) { 334 case PHY_DRV_ODT_240: 335 vref_value_dq = 0x19; 336 break; 337 case PHY_DRV_ODT_120: 338 vref_value_dq = 0x23; 339 break; 340 case PHY_DRV_ODT_60: 341 vref_value_dq = 0x31; 342 break; 343 default: 344 debug("Invalid ODT value.\n"); 345 return -EINVAL; 346 } 347 } else if (drv_value == PHY_DRV_ODT_34_3) { 348 switch (odt_value) { 349 case PHY_DRV_ODT_240: 350 vref_value_dq = 0x17; 351 break; 352 case PHY_DRV_ODT_120: 353 vref_value_dq = 0x20; 354 break; 355 case PHY_DRV_ODT_60: 356 vref_value_dq = 0x2e; 357 break; 358 default: 359 debug("Invalid ODT value.\n"); 360 return -EINVAL; 361 } 362 } else { 363 debug("Invalid DRV value.\n"); 364 return -EINVAL; 365 } 366 } else { 367 vref_mode_dq = 0x2; /* LPDDR3 */ 368 vref_value_dq = 0x1f; 369 } 370 vref_mode_ac = 0x2; 371 vref_value_ac = 0x1f; 372 } else if (sdram_params->base.dramtype == DDR3) { 373 /* DDR3L */ 374 vref_mode_dq = 0x1; 375 vref_value_dq = 0x1f; 376 vref_mode_ac = 0x1; 377 vref_value_ac = 0x1f; 378 } else { 379 debug("Unknown DRAM type.\n"); 380 return -EINVAL; 381 } 382 383 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; 384 385 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ 386 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); 387 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ 388 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); 389 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ 390 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); 391 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ 392 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); 393 394 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; 395 396 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ 397 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); 398 399 if (sdram_params->base.dramtype == LPDDR4) 400 mode_sel = 0x6; 401 else if (sdram_params->base.dramtype == LPDDR3) 402 mode_sel = 0x0; 403 else if (sdram_params->base.dramtype == DDR3) 404 mode_sel = 0x1; 405 else 406 return -EINVAL; 407 408 /* PHY_924 PHY_PAD_FDBK_DRIVE */ 409 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); 410 /* PHY_926 PHY_PAD_DATA_DRIVE */ 411 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); 412 /* PHY_927 PHY_PAD_DQS_DRIVE */ 413 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); 414 /* PHY_928 PHY_PAD_ADDR_DRIVE */ 415 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); 416 /* PHY_929 PHY_PAD_CLK_DRIVE */ 417 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); 418 /* PHY_935 PHY_PAD_CKE_DRIVE */ 419 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); 420 /* PHY_937 PHY_PAD_RST_DRIVE */ 421 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); 422 /* PHY_939 PHY_PAD_CS_DRIVE */ 423 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); 424 425 426 /* speed setting */ 427 if (sdram_params->base.ddr_freq < 400) 428 speed = 0x0; 429 else if (sdram_params->base.ddr_freq < 800) 430 speed = 0x1; 431 else if (sdram_params->base.ddr_freq < 1200) 432 speed = 0x2; 433 else 434 speed = 0x3; 435 436 /* PHY_924 PHY_PAD_FDBK_DRIVE */ 437 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); 438 /* PHY_926 PHY_PAD_DATA_DRIVE */ 439 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); 440 /* PHY_927 PHY_PAD_DQS_DRIVE */ 441 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); 442 /* PHY_928 PHY_PAD_ADDR_DRIVE */ 443 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); 444 /* PHY_929 PHY_PAD_CLK_DRIVE */ 445 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); 446 /* PHY_935 PHY_PAD_CKE_DRIVE */ 447 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); 448 /* PHY_937 PHY_PAD_RST_DRIVE */ 449 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); 450 /* PHY_939 PHY_PAD_CS_DRIVE */ 451 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); 452 453 return 0; 454 } 455 456 static int pctl_cfg(const struct chan_info *chan, u32 channel, 457 const struct rk3399_sdram_params *sdram_params) 458 { 459 u32 *denali_ctl = chan->pctl->denali_ctl; 460 u32 *denali_pi = chan->pi->denali_pi; 461 u32 *denali_phy = chan->publ->denali_phy; 462 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; 463 const u32 *params_phy = sdram_params->phy_regs.denali_phy; 464 u32 tmp, tmp1, tmp2; 465 u32 pwrup_srefresh_exit; 466 int ret; 467 const ulong timeout_ms = 200; 468 469 /* 470 * work around controller bug: 471 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed 472 */ 473 copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], 474 sizeof(struct rk3399_ddr_pctl_regs) - 4); 475 writel(params_ctl[0], &denali_ctl[0]); 476 copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], 477 sizeof(struct rk3399_ddr_pi_regs)); 478 /* rank count need to set for init */ 479 set_memory_map(chan, channel, sdram_params); 480 481 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); 482 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); 483 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); 484 485 pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; 486 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); 487 488 /* PHY_DLL_RST_EN */ 489 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); 490 491 setbits_le32(&denali_pi[0], START); 492 setbits_le32(&denali_ctl[0], START); 493 494 /* Wating for phy DLL lock */ 495 while (1) { 496 tmp = readl(&denali_phy[920]); 497 tmp1 = readl(&denali_phy[921]); 498 tmp2 = readl(&denali_phy[922]); 499 if ((((tmp >> 16) & 0x1) == 0x1) && 500 (((tmp1 >> 16) & 0x1) == 0x1) && 501 (((tmp1 >> 0) & 0x1) == 0x1) && 502 (((tmp2 >> 0) & 0x1) == 0x1)) 503 break; 504 } 505 506 copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); 507 copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); 508 copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); 509 copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); 510 copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); 511 copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); 512 copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); 513 copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); 514 set_ds_odt(chan, sdram_params); 515 516 /* 517 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 518 * dqs_tsel_wr_end[7:4] add Half cycle 519 */ 520 tmp = (readl(&denali_phy[84]) >> 8) & 0xff; 521 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); 522 tmp = (readl(&denali_phy[212]) >> 8) & 0xff; 523 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); 524 tmp = (readl(&denali_phy[340]) >> 8) & 0xff; 525 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); 526 tmp = (readl(&denali_phy[468]) >> 8) & 0xff; 527 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); 528 529 /* 530 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 531 * dq_tsel_wr_end[7:4] add Half cycle 532 */ 533 tmp = (readl(&denali_phy[83]) >> 16) & 0xff; 534 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); 535 tmp = (readl(&denali_phy[211]) >> 16) & 0xff; 536 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); 537 tmp = (readl(&denali_phy[339]) >> 16) & 0xff; 538 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); 539 tmp = (readl(&denali_phy[467]) >> 16) & 0xff; 540 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); 541 542 ret = phy_io_config(chan, sdram_params); 543 if (ret) 544 return ret; 545 546 /* PHY_DLL_RST_EN */ 547 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); 548 549 /* Wating for PHY and DRAM init complete */ 550 tmp = get_timer(0); 551 do { 552 if (get_timer(tmp) > timeout_ms) { 553 pr_err("DRAM (%s): phy failed to lock within %ld ms\n", 554 __func__, timeout_ms); 555 return -ETIME; 556 } 557 } while (!(readl(&denali_ctl[203]) & (1 << 3))); 558 debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); 559 560 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, 561 pwrup_srefresh_exit); 562 return 0; 563 } 564 565 static void select_per_cs_training_index(const struct chan_info *chan, 566 u32 rank) 567 { 568 u32 *denali_phy = chan->publ->denali_phy; 569 570 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ 571 if ((readl(&denali_phy[84])>>16) & 1) { 572 /* 573 * PHY_8/136/264/392 574 * phy_per_cs_training_index_X 1bit offset_24 575 */ 576 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); 577 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); 578 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); 579 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); 580 } 581 } 582 583 static void override_write_leveling_value(const struct chan_info *chan) 584 { 585 u32 *denali_ctl = chan->pctl->denali_ctl; 586 u32 *denali_phy = chan->publ->denali_phy; 587 u32 byte; 588 589 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 590 setbits_le32(&denali_phy[896], 1); 591 592 /* 593 * PHY_8/136/264/392 594 * phy_per_cs_training_multicast_en_X 1bit offset_16 595 */ 596 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); 597 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); 598 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); 599 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); 600 601 for (byte = 0; byte < 4; byte++) 602 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, 603 0x200 << 16); 604 605 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 606 clrbits_le32(&denali_phy[896], 1); 607 608 /* CTL_200 ctrlupd_req 1bit offset_8 */ 609 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); 610 } 611 612 static int data_training_ca(const struct chan_info *chan, u32 channel, 613 const struct rk3399_sdram_params *sdram_params) 614 { 615 u32 *denali_pi = chan->pi->denali_pi; 616 u32 *denali_phy = chan->publ->denali_phy; 617 u32 i, tmp; 618 u32 obs_0, obs_1, obs_2, obs_err = 0; 619 u32 rank = sdram_params->ch[channel].rank; 620 621 for (i = 0; i < rank; i++) { 622 select_per_cs_training_index(chan, i); 623 /* PI_100 PI_CALVL_EN:RW:8:2 */ 624 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); 625 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ 626 clrsetbits_le32(&denali_pi[92], 627 (0x1 << 16) | (0x3 << 24), 628 (0x1 << 16) | (i << 24)); 629 630 /* Waiting for training complete */ 631 while (1) { 632 /* PI_174 PI_INT_STATUS:RD:8:18 */ 633 tmp = readl(&denali_pi[174]) >> 8; 634 /* 635 * check status obs 636 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 637 */ 638 obs_0 = readl(&denali_phy[532]); 639 obs_1 = readl(&denali_phy[660]); 640 obs_2 = readl(&denali_phy[788]); 641 if (((obs_0 >> 30) & 0x3) || 642 ((obs_1 >> 30) & 0x3) || 643 ((obs_2 >> 30) & 0x3)) 644 obs_err = 1; 645 if ((((tmp >> 11) & 0x1) == 0x1) && 646 (((tmp >> 13) & 0x1) == 0x1) && 647 (((tmp >> 5) & 0x1) == 0x0) && 648 (obs_err == 0)) 649 break; 650 else if ((((tmp >> 5) & 0x1) == 0x1) || 651 (obs_err == 1)) 652 return -EIO; 653 } 654 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 655 writel(0x00003f7c, (&denali_pi[175])); 656 } 657 clrbits_le32(&denali_pi[100], 0x3 << 8); 658 659 return 0; 660 } 661 662 static int data_training_wl(const struct chan_info *chan, u32 channel, 663 const struct rk3399_sdram_params *sdram_params) 664 { 665 u32 *denali_pi = chan->pi->denali_pi; 666 u32 *denali_phy = chan->publ->denali_phy; 667 u32 i, tmp; 668 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; 669 u32 rank = sdram_params->ch[channel].rank; 670 671 for (i = 0; i < rank; i++) { 672 select_per_cs_training_index(chan, i); 673 /* PI_60 PI_WRLVL_EN:RW:8:2 */ 674 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); 675 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ 676 clrsetbits_le32(&denali_pi[59], 677 (0x1 << 8) | (0x3 << 16), 678 (0x1 << 8) | (i << 16)); 679 680 /* Waiting for training complete */ 681 while (1) { 682 /* PI_174 PI_INT_STATUS:RD:8:18 */ 683 tmp = readl(&denali_pi[174]) >> 8; 684 685 /* 686 * check status obs, if error maybe can not 687 * get leveling done PHY_40/168/296/424 688 * phy_wrlvl_status_obs_X:0:13 689 */ 690 obs_0 = readl(&denali_phy[40]); 691 obs_1 = readl(&denali_phy[168]); 692 obs_2 = readl(&denali_phy[296]); 693 obs_3 = readl(&denali_phy[424]); 694 if (((obs_0 >> 12) & 0x1) || 695 ((obs_1 >> 12) & 0x1) || 696 ((obs_2 >> 12) & 0x1) || 697 ((obs_3 >> 12) & 0x1)) 698 obs_err = 1; 699 if ((((tmp >> 10) & 0x1) == 0x1) && 700 (((tmp >> 13) & 0x1) == 0x1) && 701 (((tmp >> 4) & 0x1) == 0x0) && 702 (obs_err == 0)) 703 break; 704 else if ((((tmp >> 4) & 0x1) == 0x1) || 705 (obs_err == 1)) 706 return -EIO; 707 } 708 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 709 writel(0x00003f7c, (&denali_pi[175])); 710 } 711 712 override_write_leveling_value(chan); 713 clrbits_le32(&denali_pi[60], 0x3 << 8); 714 715 return 0; 716 } 717 718 static int data_training_rg(const struct chan_info *chan, u32 channel, 719 const struct rk3399_sdram_params *sdram_params) 720 { 721 u32 *denali_pi = chan->pi->denali_pi; 722 u32 *denali_phy = chan->publ->denali_phy; 723 u32 i, tmp; 724 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; 725 u32 rank = sdram_params->ch[channel].rank; 726 727 for (i = 0; i < rank; i++) { 728 select_per_cs_training_index(chan, i); 729 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ 730 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); 731 /* 732 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 733 * PI_RDLVL_CS:RW:24:2 734 */ 735 clrsetbits_le32(&denali_pi[74], 736 (0x1 << 16) | (0x3 << 24), 737 (0x1 << 16) | (i << 24)); 738 739 /* Waiting for training complete */ 740 while (1) { 741 /* PI_174 PI_INT_STATUS:RD:8:18 */ 742 tmp = readl(&denali_pi[174]) >> 8; 743 744 /* 745 * check status obs 746 * PHY_43/171/299/427 747 * PHY_GTLVL_STATUS_OBS_x:16:8 748 */ 749 obs_0 = readl(&denali_phy[43]); 750 obs_1 = readl(&denali_phy[171]); 751 obs_2 = readl(&denali_phy[299]); 752 obs_3 = readl(&denali_phy[427]); 753 if (((obs_0 >> (16 + 6)) & 0x3) || 754 ((obs_1 >> (16 + 6)) & 0x3) || 755 ((obs_2 >> (16 + 6)) & 0x3) || 756 ((obs_3 >> (16 + 6)) & 0x3)) 757 obs_err = 1; 758 if ((((tmp >> 9) & 0x1) == 0x1) && 759 (((tmp >> 13) & 0x1) == 0x1) && 760 (((tmp >> 3) & 0x1) == 0x0) && 761 (obs_err == 0)) 762 break; 763 else if ((((tmp >> 3) & 0x1) == 0x1) || 764 (obs_err == 1)) 765 return -EIO; 766 } 767 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 768 writel(0x00003f7c, (&denali_pi[175])); 769 } 770 clrbits_le32(&denali_pi[80], 0x3 << 24); 771 772 return 0; 773 } 774 775 static int data_training_rl(const struct chan_info *chan, u32 channel, 776 const struct rk3399_sdram_params *sdram_params) 777 { 778 u32 *denali_pi = chan->pi->denali_pi; 779 u32 i, tmp; 780 u32 rank = sdram_params->ch[channel].rank; 781 782 for (i = 0; i < rank; i++) { 783 select_per_cs_training_index(chan, i); 784 /* PI_80 PI_RDLVL_EN:RW:16:2 */ 785 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); 786 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ 787 clrsetbits_le32(&denali_pi[74], 788 (0x1 << 8) | (0x3 << 24), 789 (0x1 << 8) | (i << 24)); 790 791 /* Waiting for training complete */ 792 while (1) { 793 /* PI_174 PI_INT_STATUS:RD:8:18 */ 794 tmp = readl(&denali_pi[174]) >> 8; 795 796 /* 797 * make sure status obs not report error bit 798 * PHY_46/174/302/430 799 * phy_rdlvl_status_obs_X:16:8 800 */ 801 if ((((tmp >> 8) & 0x1) == 0x1) && 802 (((tmp >> 13) & 0x1) == 0x1) && 803 (((tmp >> 2) & 0x1) == 0x0)) 804 break; 805 else if (((tmp >> 2) & 0x1) == 0x1) 806 return -EIO; 807 } 808 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 809 writel(0x00003f7c, (&denali_pi[175])); 810 } 811 clrbits_le32(&denali_pi[80], 0x3 << 16); 812 813 return 0; 814 } 815 816 static int data_training_wdql(const struct chan_info *chan, u32 channel, 817 const struct rk3399_sdram_params *sdram_params) 818 { 819 u32 *denali_pi = chan->pi->denali_pi; 820 u32 i, tmp; 821 u32 rank = sdram_params->ch[channel].rank; 822 823 for (i = 0; i < rank; i++) { 824 select_per_cs_training_index(chan, i); 825 /* 826 * disable PI_WDQLVL_VREF_EN before wdq leveling? 827 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 828 */ 829 clrbits_le32(&denali_pi[181], 0x1 << 8); 830 /* PI_124 PI_WDQLVL_EN:RW:16:2 */ 831 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); 832 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ 833 clrsetbits_le32(&denali_pi[121], 834 (0x1 << 8) | (0x3 << 16), 835 (0x1 << 8) | (i << 16)); 836 837 /* Waiting for training complete */ 838 while (1) { 839 /* PI_174 PI_INT_STATUS:RD:8:18 */ 840 tmp = readl(&denali_pi[174]) >> 8; 841 if ((((tmp >> 12) & 0x1) == 0x1) && 842 (((tmp >> 13) & 0x1) == 0x1) && 843 (((tmp >> 6) & 0x1) == 0x0)) 844 break; 845 else if (((tmp >> 6) & 0x1) == 0x1) 846 return -EIO; 847 } 848 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 849 writel(0x00003f7c, (&denali_pi[175])); 850 } 851 clrbits_le32(&denali_pi[124], 0x3 << 16); 852 853 return 0; 854 } 855 856 static int data_training(const struct chan_info *chan, u32 channel, 857 const struct rk3399_sdram_params *sdram_params, 858 u32 training_flag) 859 { 860 u32 *denali_phy = chan->publ->denali_phy; 861 862 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 863 setbits_le32(&denali_phy[927], (1 << 22)); 864 865 if (training_flag == PI_FULL_TRAINING) { 866 if (sdram_params->base.dramtype == LPDDR4) { 867 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 868 PI_READ_GATE_TRAINING | 869 PI_READ_LEVELING | PI_WDQ_LEVELING; 870 } else if (sdram_params->base.dramtype == LPDDR3) { 871 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 872 PI_READ_GATE_TRAINING; 873 } else if (sdram_params->base.dramtype == DDR3) { 874 training_flag = PI_WRITE_LEVELING | 875 PI_READ_GATE_TRAINING | 876 PI_READ_LEVELING; 877 } 878 } 879 880 /* ca training(LPDDR4,LPDDR3 support) */ 881 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) 882 data_training_ca(chan, channel, sdram_params); 883 884 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ 885 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) 886 data_training_wl(chan, channel, sdram_params); 887 888 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ 889 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) 890 data_training_rg(chan, channel, sdram_params); 891 892 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ 893 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) 894 data_training_rl(chan, channel, sdram_params); 895 896 /* wdq leveling(LPDDR4 support) */ 897 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) 898 data_training_wdql(chan, channel, sdram_params); 899 900 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 901 clrbits_le32(&denali_phy[927], (1 << 22)); 902 903 return 0; 904 } 905 906 static void set_ddrconfig(const struct chan_info *chan, 907 const struct rk3399_sdram_params *sdram_params, 908 unsigned char channel, u32 ddrconfig) 909 { 910 /* only need to set ddrconfig */ 911 struct rk3399_msch_regs *ddr_msch_regs = chan->msch; 912 unsigned int cs0_cap = 0; 913 unsigned int cs1_cap = 0; 914 915 cs0_cap = (1 << (sdram_params->ch[channel].cs0_row 916 + sdram_params->ch[channel].col 917 + sdram_params->ch[channel].bk 918 + sdram_params->ch[channel].bw - 20)); 919 if (sdram_params->ch[channel].rank > 1) 920 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row 921 - sdram_params->ch[channel].cs1_row); 922 if (sdram_params->ch[channel].row_3_4) { 923 cs0_cap = cs0_cap * 3 / 4; 924 cs1_cap = cs1_cap * 3 / 4; 925 } 926 927 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); 928 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), 929 &ddr_msch_regs->ddrsize); 930 } 931 932 static void dram_all_config(struct dram_info *dram, 933 const struct rk3399_sdram_params *sdram_params) 934 { 935 u32 sys_reg = 0; 936 unsigned int channel, idx; 937 938 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; 939 sys_reg |= (sdram_params->base.num_channels - 1) 940 << SYS_REG_NUM_CH_SHIFT; 941 for (channel = 0, idx = 0; 942 (idx < sdram_params->base.num_channels) && (channel < 2); 943 channel++) { 944 const struct rk3399_sdram_channel *info = 945 &sdram_params->ch[channel]; 946 struct rk3399_msch_regs *ddr_msch_regs; 947 const struct rk3399_msch_timings *noc_timing; 948 949 if (sdram_params->ch[channel].col == 0) 950 continue; 951 idx++; 952 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); 953 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); 954 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); 955 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); 956 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); 957 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); 958 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); 959 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); 960 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); 961 962 ddr_msch_regs = dram->chan[channel].msch; 963 noc_timing = &sdram_params->ch[channel].noc_timings; 964 writel(noc_timing->ddrtiminga0, 965 &ddr_msch_regs->ddrtiminga0); 966 writel(noc_timing->ddrtimingb0, 967 &ddr_msch_regs->ddrtimingb0); 968 writel(noc_timing->ddrtimingc0, 969 &ddr_msch_regs->ddrtimingc0); 970 writel(noc_timing->devtodev0, 971 &ddr_msch_regs->devtodev0); 972 writel(noc_timing->ddrmode, 973 &ddr_msch_regs->ddrmode); 974 975 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ 976 if (sdram_params->ch[channel].rank == 1) 977 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 978 1 << 17); 979 } 980 981 writel(sys_reg, &dram->pmugrf->os_reg2); 982 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, 983 sdram_params->base.stride << 10); 984 985 /* reboot hold register set */ 986 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | 987 PRESET_GPIO1_HOLD(1), 988 &dram->pmucru->pmucru_rstnhold_con[1]); 989 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); 990 } 991 992 static int switch_to_phy_index1(struct dram_info *dram, 993 const struct rk3399_sdram_params *sdram_params) 994 { 995 u32 channel; 996 u32 *denali_phy; 997 u32 ch_count = sdram_params->base.num_channels; 998 int ret; 999 int i = 0; 1000 1001 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, 1002 1 << 4 | 1 << 2 | 1), 1003 &dram->cic->cic_ctrl0); 1004 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { 1005 mdelay(10); 1006 i++; 1007 if (i > 10) { 1008 debug("index1 frequency change overtime\n"); 1009 return -ETIME; 1010 } 1011 } 1012 1013 i = 0; 1014 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); 1015 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { 1016 mdelay(10); 1017 i++; 1018 if (i > 10) { 1019 debug("index1 frequency done overtime\n"); 1020 return -ETIME; 1021 } 1022 } 1023 1024 for (channel = 0; channel < ch_count; channel++) { 1025 denali_phy = dram->chan[channel].publ->denali_phy; 1026 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); 1027 ret = data_training(&dram->chan[channel], channel, 1028 sdram_params, PI_FULL_TRAINING); 1029 if (ret) { 1030 debug("index1 training failed\n"); 1031 return ret; 1032 } 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int sdram_init(struct dram_info *dram, 1039 const struct rk3399_sdram_params *sdram_params) 1040 { 1041 unsigned char dramtype = sdram_params->base.dramtype; 1042 unsigned int ddr_freq = sdram_params->base.ddr_freq; 1043 int channel; 1044 1045 debug("Starting SDRAM initialization...\n"); 1046 1047 if ((dramtype == DDR3 && ddr_freq > 933) || 1048 (dramtype == LPDDR3 && ddr_freq > 933) || 1049 (dramtype == LPDDR4 && ddr_freq > 800)) { 1050 debug("SDRAM frequency is to high!"); 1051 return -E2BIG; 1052 } 1053 1054 for (channel = 0; channel < 2; channel++) { 1055 const struct chan_info *chan = &dram->chan[channel]; 1056 struct rk3399_ddr_publ_regs *publ = chan->publ; 1057 1058 phy_dll_bypass_set(publ, ddr_freq); 1059 1060 if (channel >= sdram_params->base.num_channels) 1061 continue; 1062 1063 if (pctl_cfg(chan, channel, sdram_params) != 0) { 1064 printf("pctl_cfg fail, reset\n"); 1065 return -EIO; 1066 } 1067 1068 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 1069 if (dramtype == LPDDR3) 1070 udelay(10); 1071 1072 if (data_training(chan, channel, 1073 sdram_params, PI_FULL_TRAINING)) { 1074 printf("SDRAM initialization failed, reset\n"); 1075 return -EIO; 1076 } 1077 1078 set_ddrconfig(chan, sdram_params, channel, 1079 sdram_params->ch[channel].ddrconfig); 1080 } 1081 dram_all_config(dram, sdram_params); 1082 switch_to_phy_index1(dram, sdram_params); 1083 1084 debug("Finish SDRAM initialization...\n"); 1085 return 0; 1086 } 1087 1088 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) 1089 { 1090 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1091 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1092 int ret; 1093 1094 ret = dev_read_u32_array(dev, "rockchip,sdram-params", 1095 (u32 *)&plat->sdram_params, 1096 sizeof(plat->sdram_params) / sizeof(u32)); 1097 if (ret) { 1098 printf("%s: Cannot read rockchip,sdram-params %d\n", 1099 __func__, ret); 1100 return ret; 1101 } 1102 ret = regmap_init_mem(dev, &plat->map); 1103 if (ret) 1104 printf("%s: regmap failed %d\n", __func__, ret); 1105 1106 #endif 1107 return 0; 1108 } 1109 1110 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1111 static int conv_of_platdata(struct udevice *dev) 1112 { 1113 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1114 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; 1115 int ret; 1116 1117 ret = regmap_init_mem_platdata(dev, dtplat->reg, 1118 ARRAY_SIZE(dtplat->reg) / 2, 1119 &plat->map); 1120 if (ret) 1121 return ret; 1122 1123 return 0; 1124 } 1125 #endif 1126 1127 static int rk3399_dmc_init(struct udevice *dev) 1128 { 1129 struct dram_info *priv = dev_get_priv(dev); 1130 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1131 int ret; 1132 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1133 struct rk3399_sdram_params *params = &plat->sdram_params; 1134 #else 1135 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; 1136 struct rk3399_sdram_params *params = 1137 (void *)dtplat->rockchip_sdram_params; 1138 1139 ret = conv_of_platdata(dev); 1140 if (ret) 1141 return ret; 1142 #endif 1143 1144 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); 1145 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 1146 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); 1147 priv->pmucru = rockchip_get_pmucru(); 1148 priv->cru = rockchip_get_cru(); 1149 priv->chan[0].pctl = regmap_get_range(plat->map, 0); 1150 priv->chan[0].pi = regmap_get_range(plat->map, 1); 1151 priv->chan[0].publ = regmap_get_range(plat->map, 2); 1152 priv->chan[0].msch = regmap_get_range(plat->map, 3); 1153 priv->chan[1].pctl = regmap_get_range(plat->map, 4); 1154 priv->chan[1].pi = regmap_get_range(plat->map, 5); 1155 priv->chan[1].publ = regmap_get_range(plat->map, 6); 1156 priv->chan[1].msch = regmap_get_range(plat->map, 7); 1157 1158 debug("con reg %p %p %p %p %p %p %p %p\n", 1159 priv->chan[0].pctl, priv->chan[0].pi, 1160 priv->chan[0].publ, priv->chan[0].msch, 1161 priv->chan[1].pctl, priv->chan[1].pi, 1162 priv->chan[1].publ, priv->chan[1].msch); 1163 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, 1164 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); 1165 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1166 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); 1167 #else 1168 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 1169 #endif 1170 if (ret) { 1171 printf("%s clk get failed %d\n", __func__, ret); 1172 return ret; 1173 } 1174 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); 1175 if (ret < 0) { 1176 printf("%s clk set failed %d\n", __func__, ret); 1177 return ret; 1178 } 1179 ret = sdram_init(priv, params); 1180 if (ret < 0) { 1181 printf("%s DRAM init failed%d\n", __func__, ret); 1182 return ret; 1183 } 1184 1185 return 0; 1186 } 1187 #endif 1188 1189 static int rk3399_dmc_probe(struct udevice *dev) 1190 { 1191 #ifdef CONFIG_SPL_BUILD 1192 if (rk3399_dmc_init(dev)) 1193 return 0; 1194 #else 1195 struct dram_info *priv = dev_get_priv(dev); 1196 1197 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 1198 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); 1199 priv->info.base = CONFIG_SYS_SDRAM_BASE; 1200 priv->info.size = rockchip_sdram_size( 1201 (phys_addr_t)&priv->pmugrf->os_reg2); 1202 #endif 1203 return 0; 1204 } 1205 1206 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) 1207 { 1208 struct dram_info *priv = dev_get_priv(dev); 1209 1210 *info = priv->info; 1211 1212 return 0; 1213 } 1214 1215 static struct ram_ops rk3399_dmc_ops = { 1216 .get_info = rk3399_dmc_get_info, 1217 }; 1218 1219 1220 static const struct udevice_id rk3399_dmc_ids[] = { 1221 { .compatible = "rockchip,rk3399-dmc" }, 1222 { } 1223 }; 1224 1225 U_BOOT_DRIVER(dmc_rk3399) = { 1226 .name = "rockchip_rk3399_dmc", 1227 .id = UCLASS_RAM, 1228 .of_match = rk3399_dmc_ids, 1229 .ops = &rk3399_dmc_ops, 1230 #ifdef CONFIG_SPL_BUILD 1231 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, 1232 #endif 1233 .probe = rk3399_dmc_probe, 1234 .priv_auto_alloc_size = sizeof(struct dram_info), 1235 #ifdef CONFIG_SPL_BUILD 1236 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), 1237 #endif 1238 }; 1239