1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2600.h> 17 #include <asm/arch/sdram_ast2600.h> 18 #include <linux/err.h> 19 #include <linux/kernel.h> 20 #include <dt-bindings/clock/ast2600-clock.h> 21 #include "sdram_phy_ast2600.h" 22 23 /* in order to speed up DRAM init time, write pre-defined values to registers 24 * directly */ 25 #define AST2600_SDRAMMC_MANUAL_CLK 26 27 /* register offset */ 28 #define AST_SCU_FPGA_STATUS 0x004 29 #define AST_SCU_HANDSHAKE 0x100 30 #define AST_SCU_MPLL 0x220 31 #define AST_SCU_MPLL_EXT 0x224 32 #define AST_SCU_FPGA_PLL 0x400 33 #define AST_SCU_HW_STRAP 0x500 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 #define SCU_HWSTRAP_DDR3 BIT(25) 40 41 42 /* bit-field of AST_SCU_HANDSHAKE */ 43 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 44 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 45 46 /* bit-field of AST_SCU_MPLL */ 47 #define SCU_MPLL_RESET BIT(25) 48 #define SCU_MPLL_BYPASS BIT(24) 49 #define SCU_MPLL_TURN_OFF BIT(23) 50 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 51 52 #define SCU_MPLL_FREQ_400M 0x0008405F 53 #define SCU_MPLL_EXT_400M 0x00000031 54 //#define SCU_MPLL_FREQ_400M 0x0038007F 55 //#define SCU_MPLL_EXT_400M 0x0000003F 56 #define SCU_MPLL_FREQ_200M 0x0078007F 57 #define SCU_MPLL_EXT_200M 0x0000003F 58 59 /* MPLL configuration */ 60 #if defined(CONFIG_ASPEED_DDR4_800) 61 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 62 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 63 #elif defined(CONFIG_ASPEED_DDR4_1600) 64 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 65 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 66 #else 67 #error "undefined DDR4 target rate\n" 68 #endif 69 70 /* AC timing and SDRAM mode registers */ 71 #ifdef CONFIG_FPGA_ASPEED 72 /* mode register settings for FPGA are fixed */ 73 #define DDR4_MR01_MODE 0x03010100 74 #define DDR4_MR23_MODE 0x00000000 75 #define DDR4_MR45_MODE 0x04C00000 76 #define DDR4_MR6_MODE 0x00000050 77 #define DDR4_TRFC_FPGA 0x17263434 78 79 /* FPGA need for an additional initialization procedure: search read window */ 80 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 81 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 82 #define SEARCH_RDWIN_PTRN_0 0x12345678 83 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 84 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 85 #else 86 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 87 #define DDR4_MR01_MODE 0x03010510 88 #define DDR4_MR23_MODE 0x00000000 89 #define DDR4_MR45_MODE 0x04000000 90 #define DDR4_MR6_MODE 0x00000400 91 #define DDR4_TRFC_1600 0x467299f1 92 #define DDR4_TRFC_800 0x23394c78 93 #endif /* end of "#ifdef CONFIG_FPGA_ASPEED" */ 94 95 #if defined(CONFIG_FPGA_ASPEED) 96 #define DDR4_TRFC DDR4_TRFC_FPGA 97 #else 98 /* real chip setting */ 99 #if defined(CONFIG_ASPEED_DDR4_1600) 100 #define DDR4_TRFC DDR4_TRFC_1600 101 #define DDR4_PHY_TRAIN_TRFC 0xc30 102 #elif defined(CONFIG_ASPEED_DDR4_800) 103 #define DDR4_TRFC DDR4_TRFC_800 104 #define DDR4_PHY_TRAIN_TRFC 0x618 105 #else 106 #error "undefined tRFC setting" 107 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 108 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED)" */ 109 110 /* supported SDRAM size */ 111 #define SDRAM_SIZE_1KB (1024U) 112 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 113 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 114 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 115 116 117 DECLARE_GLOBAL_DATA_PTR; 118 119 /* 120 * Bandwidth configuration parameters for different SDRAM requests. 121 * These are hardcoded settings taken from Aspeed SDK. 122 */ 123 #ifdef CONFIG_FPGA_ASPEED 124 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 125 0x00000140}; 126 127 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 128 0x88888888}; 129 #else 130 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 131 0x00001240}; 132 133 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 134 0x44444444}; 135 #endif 136 137 struct dram_info { 138 struct ram_info info; 139 struct clk ddr_clk; 140 struct ast2600_sdrammc_regs *regs; 141 void __iomem *scu; 142 struct ast2600_ddr_phy *phy; 143 void __iomem *phy_setting; 144 void __iomem *phy_status; 145 ulong clock_rate; 146 }; 147 148 static void ast2600_sdramphy_kick_training(struct dram_info *info) 149 { 150 #ifndef CONFIG_FPGA_ASPEED 151 struct ast2600_sdrammc_regs *regs = info->regs; 152 u32 data; 153 154 writel(0, ®s->phy_ctrl[0]); 155 udelay(5000); 156 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 157 udelay(1000); 158 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 159 udelay(1000); 160 /* wait for (PLL_LOCKED == 1) and (INIT == 0) */ 161 debug("%s: wait for PHY PLL lock\n", __func__); 162 while (1) { 163 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_PLL_LOCKED; 164 if (data) { 165 break; 166 } 167 } 168 169 debug("%s: wait for PHY init done\n", __func__); 170 while (1) { 171 data = readl(®s->phy_ctrl[0]) | SDRAM_PHYCTRL0_INIT; 172 if (~data) { 173 break; 174 } 175 } 176 177 #ifdef CONFIG_ASPEED_DDR4_800 178 do { 179 data = readl(0x1e6e0400); 180 } while((data & 0x7) != 0x7); 181 #endif 182 #endif 183 } 184 185 /** 186 * @brief load DDR-PHY configurations table to the PHY registers 187 * @param[in] p_tbl - pointer to the configuration table 188 * @param[in] info - pointer to the DRAM info struct 189 * 190 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 191 * system: one is in the SDRAM MC (memory controller) which is used in run 192 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 193 * training. To make these two configurations align, we overwrite the DDR-PHY 194 * setting by the MC setting before DDR-PHY training. 195 */ 196 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 197 { 198 #ifndef CONFIG_FPGA_ASPEED 199 u32 reg_base = (u32)info->phy_setting; 200 u32 addr = p_tbl[0]; 201 u32 data; 202 int i = 1; 203 204 debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, 205 addr); 206 207 /* load PHY configuration table into PHY-setting registers */ 208 while (1) { 209 if (addr < reg_base) { 210 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 211 break; 212 } 213 data = p_tbl[i++]; 214 215 if (DDR_PHY_TBL_END == data) { 216 break; 217 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 218 addr = p_tbl[i++]; 219 } else { 220 writel(data, addr); 221 addr += 4; 222 } 223 } 224 225 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 226 data |= DDR4_PHY_TRAIN_TRFC; 227 writel(data, info->phy_setting + 0x84); 228 229 #ifdef CONFIG_ASPEED_DDR4_800 230 231 debug("Overwrite DDR-PHY MRS by MCR config\n"); 232 /* MR0 and MR1 */ 233 data = readl(&info->regs->mr01_mode_setting); 234 data = 235 ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16); 236 writel(data, reg_base + 0x58); 237 debug("[%08x] 0x%08x\n", reg_base + 0x58, data); 238 239 /* MR2 and MR3 */ 240 data = readl(&info->regs->mr23_mode_setting); 241 writel(data, reg_base + 0x54); 242 debug("[%08x] 0x%08x\n", reg_base + 0x54, data); 243 244 /* MR4 and MR5 */ 245 data = readl(&info->regs->mr45_mode_setting); 246 writel(data, reg_base + 0x5c); 247 debug("[%08x] 0x%08x\n", reg_base + 0x5c, data); 248 249 /* MR6 */ 250 data = readl(&info->regs->mr6_mode_setting); 251 writel(data, reg_base + 0x60); 252 debug("[%08x] 0x%08x\n", reg_base + 0x60, data); 253 #endif 254 #endif 255 } 256 257 static void ast2600_sdramphy_show_status(struct dram_info *info) 258 { 259 #ifndef CONFIG_FPGA_ASPEED 260 u32 value, tmp; 261 u32 reg_base = (u32)info->phy_status; 262 263 printf("\nSDRAM PHY training report:\n"); 264 /* training status */ 265 value = readl(reg_base + 0x00); 266 printf("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 267 if (value & BIT(3)) { 268 debug("\tinitial PVT calibration fail\n"); 269 } 270 if (value & BIT(5)) { 271 debug("\truntime calibration fail\n"); 272 } 273 274 /* PU & PD */ 275 value = readl(reg_base + 0x30); 276 printf("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 277 printf(" PU = 0x%02x\n", value & 0xff); 278 printf(" PD = 0x%02x\n", (value >> 16) & 0xff); 279 280 /* read eye window */ 281 value = readl(reg_base + 0x68); 282 printf("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 283 printf(" rising edge of read data eye training pass window\n"); 284 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 285 printf(" B0:%d%%\n", tmp); 286 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 287 printf(" B1:%d%%\n", tmp); 288 289 value = readl(reg_base + 0xC8); 290 printf("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 291 printf(" falling edge of read data eye training pass window\n"); 292 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 293 printf(" B0:%d%%\n", tmp); 294 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 295 printf(" B1:%d%%\n", tmp); 296 297 /* write eye window */ 298 value = readl(reg_base + 0x7c); 299 printf("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 300 printf(" rising edge of write data eye training pass window\n"); 301 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 302 printf(" B0:%d%%\n", tmp); 303 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 304 printf(" B1:%d%%\n", tmp); 305 306 /* read Vref training result */ 307 value = readl(reg_base + 0x88); 308 printf("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 309 printf(" read Vref training result\n"); 310 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 311 printf(" B0:%d%%\n", tmp); 312 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 313 printf(" B1:%d%%\n", tmp); 314 315 /* write Vref training result */ 316 value = readl(reg_base + 0x90); 317 printf("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 318 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 319 printf(" write Vref training result = %d%%\n", tmp); 320 321 /* gate train */ 322 value = readl(reg_base + 0x50); 323 printf("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 324 printf(" gate training pass window\n"); 325 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 326 printf(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 327 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 328 printf(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 329 #endif 330 } 331 332 #define MC_TEST_PATTERN_N 8 333 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 334 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 335 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 336 337 #define DRAM_MapAdr 81000000 338 #define TIMEOUT_DRAM 5000000 339 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 340 { 341 unsigned int data; 342 unsigned int timeout = 0; 343 struct ast2600_sdrammc_regs *regs = info->regs; 344 345 writel(0, ®s->ecc_test_ctrl); 346 if (mode == 0) { 347 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 348 } else { 349 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 350 } 351 352 do { 353 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 354 355 if (data & BIT(13)) 356 return (0); 357 358 if (++timeout > TIMEOUT_DRAM) { 359 printf("Timeout!!\n"); 360 writel(0, ®s->ecc_test_ctrl); 361 362 return (0); 363 } 364 } while (!data); 365 366 writel(0, ®s->ecc_test_ctrl); 367 368 return (1); 369 } 370 371 int ast2600_sdrammc_cbr_test(struct dram_info *info) 372 { 373 struct ast2600_sdrammc_regs *regs = info->regs; 374 u32 i; 375 376 writel((DRAM_MapAdr | 0x7fffff), ®s->test_addr); 377 378 /* single */ 379 for (i=0; i<8; i++) { 380 if(!ast2600_sdrammc_dg_test(info, i, 0)) return(0); 381 } 382 383 /* burst */ 384 for (i=0; i<8; i++) { 385 if(!ast2600_sdrammc_dg_test(info, i, i)) return(0); 386 } 387 388 return(1); 389 } 390 391 static int ast2600_sdrammc_test(struct dram_info *info) 392 { 393 struct ast2600_sdrammc_regs *regs = info->regs; 394 395 u32 pass_cnt = 0; 396 u32 fail_cnt = 0; 397 u32 target_cnt = 4; 398 u32 test_cnt = 0; 399 u32 pattern; 400 u32 i = 0; 401 bool finish = false; 402 403 printf("sdram mc test:\n"); 404 while (finish == false) { 405 pattern = as2600_sdrammc_test_pattern[i++]; 406 i = i % MC_TEST_PATTERN_N; 407 printf(" pattern = %08X : ",pattern); 408 writel(pattern, regs->test_init_val); 409 410 if (!ast2600_sdrammc_cbr_test(info)) { 411 printf("fail\n"); 412 fail_cnt++; 413 } else { 414 printf("pass\n"); 415 pass_cnt++; 416 } 417 418 if (++test_cnt == target_cnt) { 419 finish = true; 420 } 421 } 422 printf("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 423 target_cnt); 424 return fail_cnt; 425 } 426 427 /** 428 * scu500[14:13] 429 * 2b'00: VGA memory size = 8MB * 2^((0+1) & 0x3) = 16MB 430 * 2b'01: VGA memory size = 8MB * 2^((1+1) & 0x3) = 32MB 431 * 2b'10: VGA memory size = 8MB * 2^((2+1) & 0x3) = 64MB 432 * 2b'11: VGA memory size = 8MB * 2^((3+1) & 0x3) = 8MB 433 * 434 * mcr04[3:2] 435 * 2b'00: VGA memory size = 8MB 436 * 2b'01: VGA memory size = 16MB 437 * 2b'10: VGA memory size = 32MB 438 * 2b'11: VGA memory size = 64MB 439 */ 440 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 441 { 442 u32 vga_hwconf; 443 size_t vga_mem_size_base = 8 * 1024 * 1024; 444 445 vga_hwconf = 446 (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >> 447 SCU_HWSTRAP_VGAMEM_SHIFT; 448 449 vga_hwconf = (vga_hwconf + 1) & 0x3; 450 451 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 452 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 453 SDRAM_CONF_VGA_SIZE_MASK)); 454 455 return vga_mem_size_base << vga_hwconf; 456 } 457 #ifdef CONFIG_FPGA_ASPEED 458 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 459 { 460 u32 data; 461 u32 scu_base = (u32)info->scu; 462 463 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 464 465 do { 466 data = readl(scu_base + AST_SCU_FPGA_STATUS); 467 } while (!(data & 0x100)); 468 469 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 470 } 471 472 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 473 { 474 u32 pll, pll_min, pll_max, dat1, offset; 475 u32 win = 0x03, gwin = 0, gwinsize = 0; 476 u32 phy_setting = (u32)info->phy_setting; 477 478 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 479 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 480 481 while (gwin == 0) { 482 while (!(win & 0x80)) { 483 debug("Window = 0x%X\n", win); 484 writel(win, phy_setting + 0x0000); 485 486 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 487 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 488 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 489 ast2600_sdrammc_fpga_set_pll(info); 490 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 491 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 492 } 493 494 pll_min = 0xfff; 495 pll_max = 0x0; 496 pll = 0; 497 while (pll_max > 0 || pll < 256) { 498 ast2600_sdrammc_fpga_set_pll(info); 499 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 500 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 501 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 502 if (pll_min > pll) { 503 pll_min = pll; 504 } 505 if (pll_max < pll) { 506 pll_max = pll; 507 } 508 debug("%3d_(%3d:%3d)\n", pll, pll_min, 509 pll_max); 510 } else if (pll_max > 0) { 511 pll_min = pll_max - pll_min; 512 if (gwinsize < pll_min) { 513 gwin = win; 514 gwinsize = pll_min; 515 } 516 break; 517 } 518 pll += 1; 519 } 520 521 if (gwin != 0 && pll_max == 0) { 522 break; 523 } 524 win = win << 1; 525 } 526 if (gwin == 0) { 527 win = 0x7; 528 } 529 } 530 debug("Set PLL Read Gating Window = %x\n", gwin); 531 writel(gwin, phy_setting + 0x0000); 532 533 debug("PLL Read Window training\n"); 534 pll_min = 0xfff; 535 pll_max = 0x0; 536 537 debug("Search Window Start\n"); 538 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 539 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 540 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 541 ast2600_sdrammc_fpga_set_pll(info); 542 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 543 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 544 } 545 546 debug("Search Window Margin\n"); 547 pll = 0; 548 while (pll_max > 0 || pll < 256) { 549 ast2600_sdrammc_fpga_set_pll(info); 550 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 551 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 552 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 553 if (pll_min > pll) { 554 pll_min = pll; 555 } 556 if (pll_max < pll) { 557 pll_max = pll; 558 } 559 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 560 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 561 break; 562 } else if (pll_max > 0) { 563 pll_min = 0xfff; 564 pll_max = 0x0; 565 } 566 pll += 1; 567 } 568 if (pll_min < pll_max) { 569 debug("PLL Read window = %d\n", (pll_max - pll_min)); 570 offset = (pll_max - pll_min) >> 1; 571 pll_min = 0xfff; 572 pll = 0; 573 while (pll < (pll_min + offset)) { 574 ast2600_sdrammc_fpga_set_pll(info); 575 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 576 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 577 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 578 if (pll_min > pll) { 579 pll_min = pll; 580 } 581 debug("%d\n", pll); 582 } else { 583 pll_min = 0xfff; 584 pll_max = 0x0; 585 } 586 pll += 1; 587 } 588 return (1); 589 } else { 590 debug("PLL Read window training fail\n"); 591 return (0); 592 } 593 } 594 #endif /* end of "#ifdef CONFIG_FPGA_ASPEED" */ 595 596 /* 597 * Find out RAM size and save it in dram_info 598 * 599 * The procedure is taken from Aspeed SDK 600 */ 601 static void ast2600_sdrammc_calc_size(struct dram_info *info) 602 { 603 /* The controller supports 256/512/1024/2048 MB ram */ 604 size_t ram_size = SDRAM_MIN_SIZE; 605 const int write_test_offset = 0x100000; 606 u32 test_pattern = 0xdeadbeef; 607 u32 cap_param = SDRAM_CONF_CAP_2048M; 608 u32 refresh_timing_param = DDR4_TRFC; 609 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 610 611 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 612 ram_size >>= 1) { 613 writel(test_pattern, write_addr_base + (ram_size >> 1)); 614 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 615 } 616 617 /* One last write to overwrite all wrapped values */ 618 writel(test_pattern, write_addr_base); 619 620 /* Reset the pattern and see which value was really written */ 621 test_pattern = 0xdeadbeef; 622 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 623 ram_size >>= 1) { 624 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 625 break; 626 627 --cap_param; 628 refresh_timing_param >>= 8; 629 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 630 } 631 632 clrsetbits_le32(&info->regs->ac_timing[1], 633 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 634 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 635 << SDRAM_AC_TRFC_SHIFT)); 636 637 info->info.base = CONFIG_SYS_SDRAM_BASE; 638 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 639 640 clrsetbits_le32( 641 &info->regs->config, SDRAM_CONF_CAP_MASK, 642 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 643 } 644 645 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 646 { 647 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 648 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 649 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 650 (0x1 << MCR34_ODT_EXT_SHIFT); 651 652 #ifdef CONFIG_ASPEED_DDR4_DUALX8 653 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8); 654 #else 655 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4); 656 #endif 657 658 /* init SDRAM-PHY only on real chip */ 659 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 660 ast2600_sdramphy_kick_training(info); 661 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 662 &info->regs->power_ctrl); 663 udelay(500); 664 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 665 666 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 667 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 668 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 669 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 670 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 671 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 672 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 673 &info->regs->mode_setting_control); 674 675 #ifdef CONFIG_FPGA_ASPEED 676 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 677 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 678 &info->regs->refresh_timing); 679 #else 680 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 681 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 682 &info->regs->refresh_timing); 683 #endif 684 685 /* wait self-refresh idle */ 686 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 687 ; 688 689 #ifdef CONFIG_FPGA_ASPEED 690 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 691 SDRAM_REFRESH_ZQCS_EN | 692 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 693 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 694 &info->regs->refresh_timing); 695 #else 696 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 697 SDRAM_REFRESH_ZQCS_EN | 698 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 699 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 700 &info->regs->refresh_timing); 701 #endif 702 703 writel(power_ctrl, &info->regs->power_ctrl); 704 udelay(500); 705 706 #ifdef CONFIG_FPGA_ASPEED 707 /* toggle Vref training */ 708 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 709 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 710 &info->regs->mode_setting_control); 711 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 712 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 713 &info->regs->mode_setting_control); 714 #endif 715 return 0; 716 } 717 718 static void ast2600_sdrammc_unlock(struct dram_info *info) 719 { 720 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 721 while (!readl(&info->regs->protection_key)) 722 ; 723 } 724 725 static void ast2600_sdrammc_lock(struct dram_info *info) 726 { 727 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 728 while (readl(&info->regs->protection_key)) 729 ; 730 } 731 732 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 733 { 734 int i; 735 736 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 737 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 738 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 739 ®s->arbitration_ctrl); 740 writel(0xFFFFFFFF, ®s->req_limit_mask); 741 742 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 743 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 744 745 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 746 747 /* FIXME: the sample code does NOT match the datasheet */ 748 writel(0x7FFFFFF, ®s->ecc_range_ctrl); 749 750 writel(0, ®s->ecc_test_ctrl); 751 writel(0, ®s->test_addr); 752 writel(0, ®s->test_fail_dq_bit); 753 writel(0, ®s->test_init_val); 754 755 writel(0xFFFFFFFF, ®s->req_input_ctrl); 756 writel(0, ®s->req_high_pri_ctrl); 757 758 udelay(500); 759 760 /* set capacity to the max size */ 761 clrsetbits_le32(®s->config, SDRAM_CONF_CAP_MASK, 762 SDRAM_CONF_CAP_2048M); 763 764 /* load controller setting */ 765 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 766 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 767 768 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 769 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 770 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 771 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 772 } 773 774 static int ast2600_sdrammc_probe(struct udevice *dev) 775 { 776 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 777 struct ast2600_sdrammc_regs *regs = priv->regs; 778 struct udevice *clk_dev; 779 int ret; 780 uint32_t reg; 781 782 /* find SCU base address from clock device */ 783 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 784 &clk_dev); 785 if (ret) { 786 debug("clock device not defined\n"); 787 return ret; 788 } 789 790 priv->scu = devfdt_get_addr_ptr(clk_dev); 791 if (IS_ERR(priv->scu)) { 792 debug("%s(): can't get SCU\n", __func__); 793 return PTR_ERR(priv->scu); 794 } 795 796 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 797 debug("%s(): DDR SDRAM had been initialized\n", __func__); 798 ast2600_sdrammc_calc_size(priv); 799 return 0; 800 } 801 802 #ifdef AST2600_SDRAMMC_MANUAL_CLK 803 reg = readl(priv->scu + AST_SCU_MPLL); 804 reg &= ~(BIT(24) | GENMASK(22, 0)); 805 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 806 writel(reg, priv->scu + AST_SCU_MPLL); 807 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 808 udelay(100); 809 reg &= ~(BIT(25) | BIT(23)); 810 writel(reg, priv->scu + AST_SCU_MPLL); 811 while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))); 812 #else 813 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 814 if (ret) { 815 debug("DDR:No CLK\n"); 816 return ret; 817 } 818 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 819 #endif 820 821 #if 0 822 /* FIXME: enable the following code if reset-driver is ready */ 823 struct reset_ctl reset_ctl; 824 ret = reset_get_by_index(dev, 0, &reset_ctl); 825 if (ret) { 826 debug("%s(): Failed to get reset signal\n", __func__); 827 return ret; 828 } 829 830 ret = reset_assert(&reset_ctl); 831 if (ret) { 832 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 833 return ret; 834 } 835 #endif 836 837 ast2600_sdrammc_unlock(priv); 838 ast2600_sdrammc_common_init(regs); 839 840 if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) { 841 debug("Unsupported SDRAM type: DDR3\n"); 842 return -EINVAL; 843 } else { 844 ast2600_sdrammc_init_ddr4(priv); 845 } 846 847 #ifdef CONFIG_FPGA_ASPEED 848 ast2600_sdrammc_search_read_window(priv); 849 #endif 850 851 ast2600_sdramphy_show_status(priv); 852 ast2600_sdrammc_calc_size(priv); 853 854 if (0 != ast2600_sdrammc_test(priv)) { 855 printf("%s: DDR4 init fail\n", __func__); 856 return -EINVAL; 857 } 858 859 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 860 priv->scu + AST_SCU_HANDSHAKE); 861 862 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 863 ast2600_sdrammc_lock(priv); 864 return 0; 865 } 866 867 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 868 { 869 struct dram_info *priv = dev_get_priv(dev); 870 871 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 872 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 873 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 874 875 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 876 "clock-frequency", 0); 877 if (!priv->clock_rate) { 878 debug("DDR Clock Rate not defined\n"); 879 return -EINVAL; 880 } 881 882 return 0; 883 } 884 885 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 886 { 887 struct dram_info *priv = dev_get_priv(dev); 888 889 *info = priv->info; 890 891 return 0; 892 } 893 894 static struct ram_ops ast2600_sdrammc_ops = { 895 .get_info = ast2600_sdrammc_get_info, 896 }; 897 898 static const struct udevice_id ast2600_sdrammc_ids[] = { 899 { .compatible = "aspeed,ast2600-sdrammc" }, 900 { } 901 }; 902 903 U_BOOT_DRIVER(sdrammc_ast2600) = { 904 .name = "aspeed_ast2600_sdrammc", 905 .id = UCLASS_RAM, 906 .of_match = ast2600_sdrammc_ids, 907 .ops = &ast2600_sdrammc_ops, 908 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 909 .probe = ast2600_sdrammc_probe, 910 .priv_auto_alloc_size = sizeof(struct dram_info), 911 }; 912