1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 45 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 46 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 47 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 48 #define SCU_HANDSHAKE_MASK \ 49 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 50 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 51 52 /* bit-field of AST_SCU_MPLL */ 53 #define SCU_MPLL_RESET BIT(25) 54 #define SCU_MPLL_BYPASS BIT(24) 55 #define SCU_MPLL_TURN_OFF BIT(23) 56 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 57 58 #define SCU_MPLL_FREQ_400M 0x0008405F 59 #define SCU_MPLL_EXT_400M 0x0000002F 60 //#define SCU_MPLL_FREQ_400M 0x0038007F 61 //#define SCU_MPLL_EXT_400M 0x0000003F 62 #define SCU_MPLL_FREQ_333M 0x00488299 63 #define SCU_MPLL_EXT_333M 0x0000014C 64 #define SCU_MPLL_FREQ_200M 0x0078007F 65 #define SCU_MPLL_EXT_200M 0x0000003F 66 #define SCU_MPLL_FREQ_100M 0x0078003F 67 #define SCU_MPLL_EXT_100M 0x0000001F 68 /* MPLL configuration */ 69 #if defined(CONFIG_ASPEED_DDR4_1600) 70 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 71 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 72 #elif defined(CONFIG_ASPEED_DDR4_1333) 73 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 74 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 75 #elif defined(CONFIG_ASPEED_DDR4_800) 76 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 77 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 78 #elif defined(CONFIG_ASPEED_DDR4_400) 79 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 80 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 81 #else 82 #error "undefined DDR4 target rate\n" 83 #endif 84 85 /** 86 * MR01[26:24] - ODT configuration (DRAM side) 87 * b'001 : 60 ohm 88 * b'101 : 48 ohm 89 * b'011 : 40 ohm (default) 90 */ 91 #if defined(CONFIG_ASPEED_DDR4_DRAM_ODT60) 92 #define MR01_DRAM_ODT (0x1 << 24) 93 #elif defined(CONFIG_ASPEED_DDR4_DRAM_ODT48) 94 #define MR01_DRAM_ODT (0x5 << 24) 95 #else 96 #define MR01_DRAM_ODT (0x3 << 24) 97 #endif 98 99 /* AC timing and SDRAM mode registers */ 100 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 101 /* mode register settings for FPGA are fixed */ 102 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010100) 103 #define DDR4_MR23_MODE 0x00000000 104 #define DDR4_MR45_MODE 0x04C00000 105 #define DDR4_MR6_MODE 0x00000050 106 #define DDR4_TRFC_FPGA 0x17263434 107 #define DDR4_TRFI 0x5d 108 109 /* FPGA need for an additional initialization procedure: search read window */ 110 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 111 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 112 #define SEARCH_RDWIN_PTRN_0 0x12345678 113 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 114 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 115 #else 116 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 117 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010510) 118 #define DDR4_MR23_MODE 0x00000000 119 #define DDR4_MR45_MODE 0x04000000 120 #define DDR4_MR6_MODE 0x00000400 121 #define DDR4_TRFC_1600 0x467299f1 122 #define DDR4_TRFC_1333 0x3a5f80c9 123 #define DDR4_TRFC_800 0x23394c78 124 #define DDR4_TRFC_400 0x111c263c 125 /* 126 * tRFI calculation 127 * DDR4 spec. : 128 * tRFI = 7.8 us if temperature is Less/equal than 85 degree celsius 129 * tRFI = 3.9 us if temperature is greater than 85 degree celsius 130 * 131 * tRFI in MCR0C = floor(tRFI * 12.5M) - margin 132 * normal temp. -> floor(7.8 * 12.5) - 2 = 0x5f 133 * high temp. -> floor(3.9 * 12.5) - 1 = 0x2f 134 */ 135 #ifdef CONFIG_ASPEED_HI_TEMP_TRFI 136 #define DDR4_TRFI 0x2f /* High temperature tRFI */ 137 #else 138 #define DDR4_TRFI 0x5f /* Normal temperature tRFI */ 139 #endif /* end of "#ifdef CONFIG_ASPEED_HI_TEMP_TRFI" */ 140 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 141 defined(CONFIG_ASPEED_PALLADIUM)" */ 142 143 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 144 #define DDR4_TRFC DDR4_TRFC_FPGA 145 #else 146 /* real chip setting */ 147 #if defined(CONFIG_ASPEED_DDR4_1600) 148 #define DDR4_TRFC DDR4_TRFC_1600 149 #define DDR4_PHY_TRAIN_TRFC 0xc30 150 #elif defined(CONFIG_ASPEED_DDR4_1333) 151 #define DDR4_TRFC DDR4_TRFC_1333 152 #define DDR4_PHY_TRAIN_TRFC 0xa25 153 #elif defined(CONFIG_ASPEED_DDR4_800) 154 #define DDR4_TRFC DDR4_TRFC_800 155 #define DDR4_PHY_TRAIN_TRFC 0x618 156 #elif defined(CONFIG_ASPEED_DDR4_400) 157 #define DDR4_TRFC DDR4_TRFC_400 158 #define DDR4_PHY_TRAIN_TRFC 0x30c 159 #else 160 #error "undefined tRFC setting" 161 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 162 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 163 defined(CONFIG_ASPEED_PALLADIUM)" */ 164 165 /* supported SDRAM size */ 166 #define SDRAM_SIZE_1KB (1024U) 167 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 168 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 169 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 170 171 172 DECLARE_GLOBAL_DATA_PTR; 173 174 /* 175 * Bandwidth configuration parameters for different SDRAM requests. 176 * These are hardcoded settings taken from Aspeed SDK. 177 */ 178 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 179 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 180 0x00000140 }; 181 182 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 183 0x88888888 }; 184 #else 185 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 186 0x00001240 }; 187 188 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 189 0x44444444 }; 190 #endif 191 192 struct dram_info { 193 struct ram_info info; 194 struct clk ddr_clk; 195 struct ast2600_sdrammc_regs *regs; 196 void __iomem *scu; 197 struct ast2600_ddr_phy *phy; 198 void __iomem *phy_setting; 199 void __iomem *phy_status; 200 ulong clock_rate; 201 }; 202 203 static void ast2600_sdramphy_kick_training(struct dram_info *info) 204 { 205 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 206 struct ast2600_sdrammc_regs *regs = info->regs; 207 u32 volatile data; 208 209 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 210 udelay(5); 211 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 212 udelay(1000); 213 214 while (1) { 215 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 216 if (~data) { 217 break; 218 } 219 } 220 221 #if 0 222 while (1) { 223 data = readl(0x1e6e0400) & BIT(1); 224 if (data) { 225 break; 226 } 227 } 228 #endif 229 #endif 230 } 231 232 /** 233 * @brief load DDR-PHY configurations table to the PHY registers 234 * @param[in] p_tbl - pointer to the configuration table 235 * @param[in] info - pointer to the DRAM info struct 236 * 237 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 238 * system: one is in the SDRAM MC (memory controller) which is used in run 239 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 240 * training. 241 */ 242 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 243 { 244 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 245 u32 reg_base = (u32)info->phy_setting; 246 u32 addr = p_tbl[0]; 247 u32 data; 248 int i = 1; 249 250 writel(0, &info->regs->phy_ctrl[0]); 251 udelay(10); 252 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 253 254 /* load PHY configuration table into PHY-setting registers */ 255 while (1) { 256 if (addr < reg_base) { 257 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 258 break; 259 } 260 data = p_tbl[i++]; 261 262 if (data == DDR_PHY_TBL_END) { 263 break; 264 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 265 addr = p_tbl[i++]; 266 } else { 267 writel(data, addr); 268 addr += 4; 269 } 270 } 271 272 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 273 data |= DDR4_PHY_TRAIN_TRFC; 274 writel(data, info->phy_setting + 0x84); 275 #endif 276 } 277 278 static int ast2600_sdramphy_check_status(struct dram_info *info) 279 { 280 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 281 u32 value, tmp; 282 u32 reg_base = (u32)info->phy_status; 283 int need_retrain = 0; 284 285 debug("\nSDRAM PHY training report:\n"); 286 /* training status */ 287 value = readl(reg_base + 0x00); 288 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 289 if (value & BIT(3)) { 290 debug("\tinitial PVT calibration fail\n"); 291 } 292 if (value & BIT(5)) { 293 debug("\truntime calibration fail\n"); 294 } 295 296 /* PU & PD */ 297 value = readl(reg_base + 0x30); 298 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 299 debug(" PU = 0x%02x\n", value & 0xff); 300 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 301 302 /* read eye window */ 303 value = readl(reg_base + 0x68); 304 if (0 == (value & GENMASK(7, 0))) { 305 need_retrain = 1; 306 } 307 308 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 309 debug(" rising edge of read data eye training pass window\n"); 310 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 311 debug(" B0:%d%%\n", tmp); 312 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 313 debug(" B1:%d%%\n", tmp); 314 315 value = readl(reg_base + 0xC8); 316 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 317 debug(" falling edge of read data eye training pass window\n"); 318 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 319 debug(" B0:%d%%\n", tmp); 320 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 321 debug(" B1:%d%%\n", tmp); 322 323 /* write eye window */ 324 value = readl(reg_base + 0x7c); 325 if (0 == (value & GENMASK(7, 0))) { 326 need_retrain = 1; 327 } 328 329 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 330 debug(" rising edge of write data eye training pass window\n"); 331 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 332 debug(" B0:%d%%\n", tmp); 333 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 334 debug(" B1:%d%%\n", tmp); 335 336 /* read Vref (PHY side) training result */ 337 value = readl(reg_base + 0x88); 338 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 339 340 /* write Vref (DRAM side) training result */ 341 value = readl(reg_base + 0x90); 342 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 343 344 /* gate train */ 345 value = readl(reg_base + 0x50); 346 if ((0 == (value & GENMASK(15, 0))) || 347 (0 == (value & GENMASK(31, 16)))) { 348 need_retrain = 1; 349 } 350 #if 0 351 if (((value >> 24) & 0xff) < 3) 352 need_retrain = 1; 353 else 354 need_retrain = 0; 355 #endif 356 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 357 #if 0 358 debug(" gate training pass window\n"); 359 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 360 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 361 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 362 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 363 #endif 364 365 return need_retrain; 366 #else 367 return 0; 368 #endif 369 } 370 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 371 #define MC_TEST_PATTERN_N 8 372 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 373 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 374 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 375 }; 376 377 #define TIMEOUT_DRAM 5000000 378 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 379 { 380 unsigned int data; 381 unsigned int timeout = 0; 382 struct ast2600_sdrammc_regs *regs = info->regs; 383 384 writel(0, ®s->ecc_test_ctrl); 385 if (mode == 0) 386 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 387 else 388 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 389 390 do { 391 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 392 393 if (data & BIT(13)) 394 return 0; 395 396 if (++timeout > TIMEOUT_DRAM) { 397 printf("Timeout!!\n"); 398 writel(0, ®s->ecc_test_ctrl); 399 400 return 0; 401 } 402 } while (!data); 403 404 writel(0, ®s->ecc_test_ctrl); 405 406 return 1; 407 } 408 409 int ast2600_sdrammc_cbr_test(struct dram_info *info) 410 { 411 struct ast2600_sdrammc_regs *regs = info->regs; 412 u32 i; 413 414 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 415 416 /* single */ 417 for (i = 0; i < 8; i++) { 418 if (!ast2600_sdrammc_dg_test(info, i, 0)) 419 return (0); 420 } 421 422 /* burst */ 423 for (i = 0; i < 8; i++) { 424 if (!ast2600_sdrammc_dg_test(info, i, i)) 425 return (0); 426 } 427 428 return(1); 429 } 430 431 static int ast2600_sdrammc_test(struct dram_info *info) 432 { 433 struct ast2600_sdrammc_regs *regs = info->regs; 434 435 u32 pass_cnt = 0; 436 u32 fail_cnt = 0; 437 u32 target_cnt = 2; 438 u32 test_cnt = 0; 439 u32 pattern; 440 u32 i = 0; 441 bool finish = false; 442 443 debug("sdram mc test:\n"); 444 while (finish == false) { 445 pattern = as2600_sdrammc_test_pattern[i++]; 446 i = i % MC_TEST_PATTERN_N; 447 debug(" pattern = %08x : ", pattern); 448 writel(pattern, ®s->test_init_val); 449 450 if (!ast2600_sdrammc_cbr_test(info)) { 451 debug("fail\n"); 452 fail_cnt++; 453 } else { 454 debug("pass\n"); 455 pass_cnt++; 456 } 457 458 if (++test_cnt == target_cnt) { 459 finish = true; 460 } 461 } 462 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 463 target_cnt); 464 return fail_cnt; 465 } 466 #endif 467 /** 468 * scu500[14:13] 469 * 2b'00: VGA memory size = 16MB 470 * 2b'01: VGA memory size = 16MB 471 * 2b'10: VGA memory size = 32MB 472 * 2b'11: VGA memory size = 64MB 473 * 474 * mcr04[3:2] 475 * 2b'00: VGA memory size = 8MB 476 * 2b'01: VGA memory size = 16MB 477 * 2b'10: VGA memory size = 32MB 478 * 2b'11: VGA memory size = 64MB 479 */ 480 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 481 { 482 u32 vga_hwconf; 483 size_t vga_mem_size_base = 8 * 1024 * 1024; 484 485 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 486 SCU_HWSTRAP_VGAMEM_MASK) >> 487 SCU_HWSTRAP_VGAMEM_SHIFT; 488 489 if (vga_hwconf == 0) { 490 vga_hwconf = 1; 491 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 492 info->scu + AST_SCU_HW_STRAP); 493 } 494 495 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 496 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 497 SDRAM_CONF_VGA_SIZE_MASK)); 498 499 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 500 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 501 return 0; 502 503 return vga_mem_size_base << vga_hwconf; 504 } 505 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 506 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 507 { 508 u32 data; 509 u32 scu_base = (u32)info->scu; 510 511 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 512 513 do { 514 data = readl(scu_base + AST_SCU_FPGA_STATUS); 515 } while (!(data & 0x100)); 516 517 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 518 } 519 520 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 521 { 522 u32 pll, pll_min, pll_max, dat1, offset; 523 u32 win = 0x03, gwin = 0, gwinsize = 0; 524 u32 phy_setting = (u32)info->phy_setting; 525 526 #ifdef CONFIG_ASPEED_PALLADIUM 527 writel(0xc, phy_setting + 0x0000); 528 return 1; 529 #endif 530 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 531 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 532 533 while (gwin == 0) { 534 while (!(win & 0x80)) { 535 debug("Window = 0x%X\n", win); 536 writel(win, phy_setting + 0x0000); 537 538 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 539 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 540 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 541 ast2600_sdrammc_fpga_set_pll(info); 542 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 543 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 544 } 545 546 pll_min = 0xfff; 547 pll_max = 0x0; 548 pll = 0; 549 while (pll_max > 0 || pll < 256) { 550 ast2600_sdrammc_fpga_set_pll(info); 551 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 552 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 553 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 554 if (pll_min > pll) 555 pll_min = pll; 556 557 if (pll_max < pll) 558 pll_max = pll; 559 560 debug("%3d_(%3d:%3d)\n", pll, pll_min, 561 pll_max); 562 } else if (pll_max > 0) { 563 pll_min = pll_max - pll_min; 564 if (gwinsize < pll_min) { 565 gwin = win; 566 gwinsize = pll_min; 567 } 568 break; 569 } 570 pll += 1; 571 } 572 573 if (gwin != 0 && pll_max == 0) 574 break; 575 576 win = win << 1; 577 } 578 if (gwin == 0) 579 win = 0x7; 580 } 581 debug("Set PLL Read Gating Window = %x\n", gwin); 582 writel(gwin, phy_setting + 0x0000); 583 584 debug("PLL Read Window training\n"); 585 pll_min = 0xfff; 586 pll_max = 0x0; 587 588 debug("Search Window Start\n"); 589 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 590 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 591 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 592 ast2600_sdrammc_fpga_set_pll(info); 593 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 594 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 595 } 596 597 debug("Search Window Margin\n"); 598 pll = 0; 599 while (pll_max > 0 || pll < 256) { 600 ast2600_sdrammc_fpga_set_pll(info); 601 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 602 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 603 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 604 if (pll_min > pll) 605 pll_min = pll; 606 607 if (pll_max < pll) 608 pll_max = pll; 609 610 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 611 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 612 break; 613 } else if (pll_max > 0) { 614 pll_min = 0xfff; 615 pll_max = 0x0; 616 } 617 pll += 1; 618 } 619 if (pll_min < pll_max) { 620 debug("PLL Read window = %d\n", (pll_max - pll_min)); 621 offset = (pll_max - pll_min) >> 1; 622 pll_min = 0xfff; 623 pll = 0; 624 while (pll < (pll_min + offset)) { 625 ast2600_sdrammc_fpga_set_pll(info); 626 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 627 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 628 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 629 if (pll_min > pll) { 630 pll_min = pll; 631 } 632 debug("%d\n", pll); 633 } else { 634 pll_min = 0xfff; 635 pll_max = 0x0; 636 } 637 pll += 1; 638 } 639 return (1); 640 } else { 641 debug("PLL Read window training fail\n"); 642 return 0; 643 } 644 } 645 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 646 defined(CONFIG_ASPEED_PALLADIUM)" */ 647 648 /* 649 * Find out RAM size and save it in dram_info 650 * 651 * The procedure is taken from Aspeed SDK 652 */ 653 static void ast2600_sdrammc_calc_size(struct dram_info *info) 654 { 655 /* The controller supports 256/512/1024/2048 MB ram */ 656 size_t ram_size = SDRAM_MIN_SIZE; 657 const int write_test_offset = 0x100000; 658 u32 test_pattern = 0xdeadbeef; 659 u32 cap_param = SDRAM_CONF_CAP_2048M; 660 u32 refresh_timing_param = DDR4_TRFC; 661 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 662 663 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 664 ram_size >>= 1) { 665 writel(test_pattern, write_addr_base + (ram_size >> 1)); 666 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 667 } 668 669 /* One last write to overwrite all wrapped values */ 670 writel(test_pattern, write_addr_base); 671 672 /* Reset the pattern and see which value was really written */ 673 test_pattern = 0xdeadbeef; 674 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 675 ram_size >>= 1) { 676 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 677 break; 678 679 --cap_param; 680 refresh_timing_param >>= 8; 681 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 682 } 683 684 clrsetbits_le32(&info->regs->ac_timing[1], 685 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 686 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 687 << SDRAM_AC_TRFC_SHIFT)); 688 689 info->info.base = CONFIG_SYS_SDRAM_BASE; 690 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 691 692 clrsetbits_le32( 693 &info->regs->config, SDRAM_CONF_CAP_MASK, 694 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 695 } 696 697 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 698 { 699 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 700 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 701 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 702 (0x1 << MCR34_ODT_EXT_SHIFT); 703 704 /* init SDRAM-PHY only on real chip */ 705 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 706 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 707 &info->regs->power_ctrl); 708 udelay(5); 709 ast2600_sdramphy_kick_training(info); 710 udelay(500); 711 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 712 713 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 714 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 715 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 716 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 717 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 718 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 719 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 720 &info->regs->mode_setting_control); 721 722 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 723 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT), 724 &info->regs->refresh_timing); 725 726 /* wait self-refresh idle */ 727 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 728 ; 729 730 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 731 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 732 SDRAM_REFRESH_ZQCS_EN | 733 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 734 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 735 &info->regs->refresh_timing); 736 #else 737 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 738 SDRAM_REFRESH_ZQCS_EN | 739 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 740 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 741 &info->regs->refresh_timing); 742 #endif 743 744 writel(power_ctrl, &info->regs->power_ctrl); 745 udelay(500); 746 747 #if defined(CONFIG_FPGA_ASPEED) 748 /* toggle Vref training */ 749 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 750 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 751 &info->regs->mode_setting_control); 752 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 753 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 754 &info->regs->mode_setting_control); 755 #endif 756 return 0; 757 } 758 759 static void ast2600_sdrammc_unlock(struct dram_info *info) 760 { 761 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 762 while (!readl(&info->regs->protection_key)) 763 ; 764 } 765 766 static void ast2600_sdrammc_lock(struct dram_info *info) 767 { 768 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 769 while (readl(&info->regs->protection_key)) 770 ; 771 } 772 773 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 774 { 775 int i; 776 777 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 778 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 779 /* [6:0] : Group 1 request queued number = 16 780 * [14:8] : Group 2 request queued number = 16 781 * [20:16] : R/W max-grant count for RQ output arbitration = 16 782 */ 783 writel(0x101010, ®s->arbitration_ctrl); 784 /* Request Queued Limitation for REQ8/9 USB1/2 */ 785 writel(0x0FFF3CEF, ®s->req_limit_mask); 786 787 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 788 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 789 790 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 791 792 /* FIXME: the sample code does NOT match the datasheet */ 793 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 794 795 writel(0, ®s->ecc_test_ctrl); 796 writel(0x80000001, ®s->test_addr); 797 writel(0, ®s->test_fail_dq_bit); 798 writel(0, ®s->test_init_val); 799 800 writel(0xFFFFFFFF, ®s->req_input_ctrl); 801 writel(0x300, ®s->req_high_pri_ctrl); 802 803 udelay(600); 804 805 #ifdef CONFIG_ASPEED_DDR4_DUALX8 806 writel(0xa037, ®s->config); 807 #else 808 writel(0xa017, ®s->config); 809 #endif 810 811 /* load controller setting */ 812 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 813 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 814 815 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 816 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 817 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 818 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 819 } 820 /* 821 * Update size info according to the ECC HW setting 822 * 823 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 824 * don't need to calculate the ECC size again but read from MCR04 and derive the 825 * size from its value. 826 */ 827 static void ast2600_sdrammc_update_size(struct dram_info *info) 828 { 829 struct ast2600_sdrammc_regs *regs = info->regs; 830 size_t hw_size; 831 size_t ram_size = SDRAM_MAX_SIZE; 832 u32 cap_param; 833 834 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 835 switch (cap_param) 836 { 837 case SDRAM_CONF_CAP_2048M: 838 ram_size = 2048 * SDRAM_SIZE_1MB; 839 break; 840 case SDRAM_CONF_CAP_1024M: 841 ram_size = 1024 * SDRAM_SIZE_1MB; 842 break; 843 case SDRAM_CONF_CAP_512M: 844 ram_size = 512 * SDRAM_SIZE_1MB; 845 break; 846 case SDRAM_CONF_CAP_256M: 847 ram_size = 256 * SDRAM_SIZE_1MB; 848 break; 849 } 850 851 info->info.base = CONFIG_SYS_SDRAM_BASE; 852 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 853 854 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 855 return; 856 857 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 858 hw_size += (1 << 20); 859 860 info->info.size = hw_size; 861 } 862 #ifdef CONFIG_ASPEED_ECC 863 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 864 { 865 struct ast2600_sdrammc_regs *regs = info->regs; 866 size_t conf_size; 867 u32 reg; 868 869 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 870 if (conf_size > info->info.size) { 871 printf("warning: ECC configured %dMB but actual size is %dMB\n", 872 CONFIG_ASPEED_ECC_SIZE, 873 info->info.size / SDRAM_SIZE_1MB); 874 conf_size = info->info.size; 875 } else if (conf_size == 0) { 876 conf_size = info->info.size; 877 } 878 879 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 880 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 881 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 882 writel(reg, ®s->config); 883 884 writel(0, ®s->test_init_val); 885 writel(0x80000001, ®s->test_addr); 886 writel(0x221, ®s->ecc_test_ctrl); 887 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 888 ; 889 writel(0, ®s->ecc_test_ctrl); 890 writel(BIT(31), ®s->intr_ctrl); 891 writel(0, ®s->intr_ctrl); 892 } 893 #endif 894 895 static int ast2600_sdrammc_probe(struct udevice *dev) 896 { 897 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 898 struct ast2600_sdrammc_regs *regs = priv->regs; 899 struct udevice *clk_dev; 900 int ret; 901 volatile uint32_t reg; 902 903 /* find SCU base address from clock device */ 904 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 905 &clk_dev); 906 if (ret) { 907 debug("clock device not defined\n"); 908 return ret; 909 } 910 911 priv->scu = devfdt_get_addr_ptr(clk_dev); 912 if (IS_ERR(priv->scu)) { 913 debug("%s(): can't get SCU\n", __func__); 914 return PTR_ERR(priv->scu); 915 } 916 917 reg = readl(priv->scu + AST_SCU_HANDSHAKE); 918 if (reg & SCU_SDRAM_INIT_READY_MASK) { 919 printf("already initialized, "); 920 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 921 ast2600_sdrammc_update_size(priv); 922 return 0; 923 } 924 925 #ifdef AST2600_SDRAMMC_MANUAL_CLK 926 reg = readl(priv->scu + AST_SCU_MPLL); 927 reg &= ~(BIT(24) | GENMASK(22, 0)); 928 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 929 writel(reg, priv->scu + AST_SCU_MPLL); 930 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 931 udelay(100); 932 reg &= ~(BIT(25) | BIT(23)); 933 writel(reg, priv->scu + AST_SCU_MPLL); 934 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 935 ; 936 #else 937 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 938 if (ret) { 939 debug("DDR:No CLK\n"); 940 return ret; 941 } 942 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 943 #endif 944 945 #if 0 946 /* FIXME: enable the following code if reset-driver is ready */ 947 struct reset_ctl reset_ctl; 948 ret = reset_get_by_index(dev, 0, &reset_ctl); 949 if (ret) { 950 debug("%s(): Failed to get reset signal\n", __func__); 951 return ret; 952 } 953 954 ret = reset_assert(&reset_ctl); 955 if (ret) { 956 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 957 return ret; 958 } 959 #endif 960 961 ast2600_sdrammc_unlock(priv); 962 ast2600_sdrammc_common_init(regs); 963 L_ast2600_sdramphy_train: 964 ast2600_sdrammc_init_ddr4(priv); 965 966 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 967 ast2600_sdrammc_search_read_window(priv); 968 #else 969 /* make sure DDR-PHY is ready before access */ 970 do { 971 reg = readl(priv->phy_status) & BIT(1); 972 } while (reg == 0); 973 #endif 974 975 ret = ast2600_sdramphy_check_status(priv); 976 if (ret) { 977 printf("DDR4 PHY training fail, retrain\n"); 978 goto L_ast2600_sdramphy_train; 979 } 980 981 ast2600_sdrammc_calc_size(priv); 982 983 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 984 ret = ast2600_sdrammc_test(priv); 985 if (ret) { 986 printf("%s: DDR4 init fail\n", __func__); 987 return -EINVAL; 988 } 989 #endif 990 991 #ifdef CONFIG_ASPEED_ECC 992 ast2600_sdrammc_ecc_enable(priv); 993 #endif 994 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 995 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 996 ast2600_sdrammc_lock(priv); 997 return 0; 998 } 999 1000 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 1001 { 1002 struct dram_info *priv = dev_get_priv(dev); 1003 1004 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 1005 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 1006 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 1007 1008 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 1009 "clock-frequency", 0); 1010 if (!priv->clock_rate) { 1011 debug("DDR Clock Rate not defined\n"); 1012 return -EINVAL; 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 1019 { 1020 struct dram_info *priv = dev_get_priv(dev); 1021 1022 *info = priv->info; 1023 1024 return 0; 1025 } 1026 1027 static struct ram_ops ast2600_sdrammc_ops = { 1028 .get_info = ast2600_sdrammc_get_info, 1029 }; 1030 1031 static const struct udevice_id ast2600_sdrammc_ids[] = { 1032 { .compatible = "aspeed,ast2600-sdrammc" }, 1033 { } 1034 }; 1035 1036 U_BOOT_DRIVER(sdrammc_ast2600) = { 1037 .name = "aspeed_ast2600_sdrammc", 1038 .id = UCLASS_RAM, 1039 .of_match = ast2600_sdrammc_ids, 1040 .ops = &ast2600_sdrammc_ops, 1041 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1042 .probe = ast2600_sdrammc_probe, 1043 .priv_auto_alloc_size = sizeof(struct dram_info), 1044 }; 1045