1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27737d5c6SDave Liu /* 37737d5c6SDave Liu * Copyright (C) 2006 Freescale Semiconductor, Inc. 47737d5c6SDave Liu * 57737d5c6SDave Liu * Dave Liu <daveliu@freescale.com> 67737d5c6SDave Liu * based on source code of Shlomi Gridish 77737d5c6SDave Liu */ 87737d5c6SDave Liu 97737d5c6SDave Liu #ifndef __UCCF_H__ 107737d5c6SDave Liu #define __UCCF_H__ 117737d5c6SDave Liu 127737d5c6SDave Liu #include "common.h" 1338d67a4eSZhao Qiang #include "linux/immap_qe.h" 142459afb1SQianyu Gong #include <fsl_qe.h> 157737d5c6SDave Liu 167737d5c6SDave Liu /* Fast or Giga ethernet 177737d5c6SDave Liu */ 187737d5c6SDave Liu typedef enum enet_type { 197737d5c6SDave Liu FAST_ETH, 207737d5c6SDave Liu GIGA_ETH, 217737d5c6SDave Liu } enet_type_e; 227737d5c6SDave Liu 237737d5c6SDave Liu /* General UCC Extended Mode Register 247737d5c6SDave Liu */ 257737d5c6SDave Liu #define UCC_GUEMR_MODE_MASK_RX 0x02 267737d5c6SDave Liu #define UCC_GUEMR_MODE_MASK_TX 0x01 277737d5c6SDave Liu #define UCC_GUEMR_MODE_FAST_RX 0x02 287737d5c6SDave Liu #define UCC_GUEMR_MODE_FAST_TX 0x01 297737d5c6SDave Liu #define UCC_GUEMR_MODE_SLOW_RX 0x00 307737d5c6SDave Liu #define UCC_GUEMR_MODE_SLOW_TX 0x00 317737d5c6SDave Liu #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ 327737d5c6SDave Liu 337737d5c6SDave Liu /* General UCC FAST Mode Register 347737d5c6SDave Liu */ 357737d5c6SDave Liu #define UCC_FAST_GUMR_TCI 0x20000000 367737d5c6SDave Liu #define UCC_FAST_GUMR_TRX 0x10000000 377737d5c6SDave Liu #define UCC_FAST_GUMR_TTX 0x08000000 387737d5c6SDave Liu #define UCC_FAST_GUMR_CDP 0x04000000 397737d5c6SDave Liu #define UCC_FAST_GUMR_CTSP 0x02000000 407737d5c6SDave Liu #define UCC_FAST_GUMR_CDS 0x01000000 417737d5c6SDave Liu #define UCC_FAST_GUMR_CTSS 0x00800000 427737d5c6SDave Liu #define UCC_FAST_GUMR_TXSY 0x00020000 437737d5c6SDave Liu #define UCC_FAST_GUMR_RSYN 0x00010000 447737d5c6SDave Liu #define UCC_FAST_GUMR_RTSM 0x00002000 457737d5c6SDave Liu #define UCC_FAST_GUMR_REVD 0x00000400 467737d5c6SDave Liu #define UCC_FAST_GUMR_ENR 0x00000020 477737d5c6SDave Liu #define UCC_FAST_GUMR_ENT 0x00000010 487737d5c6SDave Liu 497737d5c6SDave Liu /* GUMR [MODE] bit maps 507737d5c6SDave Liu */ 517737d5c6SDave Liu #define UCC_FAST_GUMR_HDLC 0x00000000 527737d5c6SDave Liu #define UCC_FAST_GUMR_QMC 0x00000002 537737d5c6SDave Liu #define UCC_FAST_GUMR_UART 0x00000004 547737d5c6SDave Liu #define UCC_FAST_GUMR_BISYNC 0x00000008 557737d5c6SDave Liu #define UCC_FAST_GUMR_ATM 0x0000000a 567737d5c6SDave Liu #define UCC_FAST_GUMR_ETH 0x0000000c 577737d5c6SDave Liu 587737d5c6SDave Liu /* Transmit On Demand (UTORD) 597737d5c6SDave Liu */ 607737d5c6SDave Liu #define UCC_SLOW_TOD 0x8000 617737d5c6SDave Liu #define UCC_FAST_TOD 0x8000 627737d5c6SDave Liu 637737d5c6SDave Liu /* Fast Ethernet (10/100 Mbps) 647737d5c6SDave Liu */ 657737d5c6SDave Liu #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ 667737d5c6SDave Liu #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ 677737d5c6SDave Liu #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ 687737d5c6SDave Liu #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ 697737d5c6SDave Liu #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 707737d5c6SDave Liu #define UCC_GETH_UTFTT_INIT 128 717737d5c6SDave Liu 727737d5c6SDave Liu /* Gigabit Ethernet (1000 Mbps) 737737d5c6SDave Liu */ 747737d5c6SDave Liu #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ 757737d5c6SDave Liu #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 767737d5c6SDave Liu #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 777737d5c6SDave Liu #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ 787737d5c6SDave Liu #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ 797737d5c6SDave Liu #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ 807737d5c6SDave Liu 817737d5c6SDave Liu /* UCC fast alignment 827737d5c6SDave Liu */ 837737d5c6SDave Liu #define UCC_FAST_RX_ALIGN 4 847737d5c6SDave Liu #define UCC_FAST_MRBLR_ALIGNMENT 4 857737d5c6SDave Liu #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 867737d5c6SDave Liu 877737d5c6SDave Liu /* Sizes 887737d5c6SDave Liu */ 897737d5c6SDave Liu #define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 907737d5c6SDave Liu 917737d5c6SDave Liu /* UCC fast structure. 927737d5c6SDave Liu */ 937737d5c6SDave Liu typedef struct ucc_fast_info { 947737d5c6SDave Liu int ucc_num; 957737d5c6SDave Liu qe_clock_e rx_clock; 967737d5c6SDave Liu qe_clock_e tx_clock; 977737d5c6SDave Liu enet_type_e eth_type; 987737d5c6SDave Liu } ucc_fast_info_t; 997737d5c6SDave Liu 1007737d5c6SDave Liu typedef struct ucc_fast_private { 1017737d5c6SDave Liu ucc_fast_info_t *uf_info; 1027737d5c6SDave Liu ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ 1037737d5c6SDave Liu u32 *p_ucce; /* a pointer to the event register */ 1047737d5c6SDave Liu u32 *p_uccm; /* a pointer to the mask register */ 1057737d5c6SDave Liu int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ 1067737d5c6SDave Liu int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ 1077737d5c6SDave Liu u32 ucc_fast_tx_virtual_fifo_base_offset; 1087737d5c6SDave Liu u32 ucc_fast_rx_virtual_fifo_base_offset; 1097737d5c6SDave Liu } ucc_fast_private_t; 1107737d5c6SDave Liu 1117737d5c6SDave Liu void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); 1127737d5c6SDave Liu u32 ucc_fast_get_qe_cr_subblock(int ucc_num); 1137737d5c6SDave Liu void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); 1147737d5c6SDave Liu void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); 1157737d5c6SDave Liu int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); 1167737d5c6SDave Liu 1177737d5c6SDave Liu #endif /* __UCCF_H__ */ 118