1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <asm/io.h> 10 #include <linux/bitops.h> 11 #include <asm/arch/pinctrl.h> 12 #include <asm/arch/scu_ast2600.h> 13 #include <dm/pinctrl.h> 14 #include "pinctrl-aspeed.h" 15 /* 16 * This driver works with very simple configuration that has the same name 17 * for group and function. This way it is compatible with the Linux Kernel 18 * driver. 19 */ 20 21 struct ast2600_pinctrl_priv { 22 struct ast2600_scu *scu; 23 }; 24 25 static int ast2600_pinctrl_probe(struct udevice *dev) 26 { 27 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 28 struct udevice *clk_dev; 29 int ret = 0; 30 31 /* find SCU base address from clock device */ 32 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 33 &clk_dev); 34 if (ret) { 35 debug("clock device not found\n"); 36 return ret; 37 } 38 39 priv->scu = devfdt_get_addr_ptr(clk_dev); 40 if (IS_ERR(priv->scu)) { 41 debug("%s(): can't get SCU\n", __func__); 42 return PTR_ERR(priv->scu); 43 } 44 45 return 0; 46 } 47 48 static struct aspeed_sig_desc mac1_link[] = { 49 #ifdef CONFIG_FPGA_ASPEED 50 { 0x410, BIT(4), 0 }, 51 #else 52 { 0x400, GENMASK(11, 0), 0 }, 53 { 0x410, BIT(4), 0 }, 54 { 0x470, BIT(4), 1 }, 55 #endif 56 }; 57 58 static struct aspeed_sig_desc mac2_link[] = { 59 { 0x400, GENMASK(23, 12), 0 }, 60 { 0x410, BIT(5), 0 }, 61 { 0x470, BIT(5), 1 }, 62 }; 63 64 static struct aspeed_sig_desc mac3_link[] = { 65 { 0x410, GENMASK(27, 16), 0 }, 66 { 0x410, BIT(6), 0 }, 67 { 0x470, BIT(6), 1 }, 68 }; 69 70 static struct aspeed_sig_desc mac4_link[] = { 71 { 0x410, GENMASK(31, 28), 1 }, 72 { 0x4b0, GENMASK(31, 28), 0 }, 73 { 0x474, GENMASK(7, 0), 1 }, 74 { 0x414, GENMASK(7, 0), 1 }, 75 { 0x4b4, GENMASK(7, 0), 0 }, 76 { 0x410, BIT(7), 0 }, 77 { 0x470, BIT(7), 1 }, 78 }; 79 80 static struct aspeed_sig_desc mdio1_link[] = { 81 { 0x430, BIT(17) | BIT(16), 0 }, 82 }; 83 84 static struct aspeed_sig_desc mdio2_link[] = { 85 { 0x470, BIT(13) | BIT(12), 1 }, 86 { 0x410, BIT(13) | BIT(12), 0 }, 87 }; 88 89 static struct aspeed_sig_desc mdio3_link[] = { 90 { 0x470, BIT(1) | BIT(0), 1 }, 91 { 0x410, BIT(1) | BIT(0), 0 }, 92 }; 93 94 static struct aspeed_sig_desc mdio4_link[] = { 95 { 0x470, BIT(3) | BIT(2), 1 }, 96 { 0x410, BIT(3) | BIT(2), 0 }, 97 }; 98 99 static struct aspeed_sig_desc sdio2_link[] = { 100 { 0x414, GENMASK(23, 16), 1 }, 101 { 0x4B4, GENMASK(23, 16), 0 }, 102 { 0x450, BIT(1), 0 }, 103 }; 104 105 static struct aspeed_sig_desc sdio1_link[] = { 106 { 0x414, GENMASK(15, 8), 0 }, 107 }; 108 109 //when sdio1 8bits, sdio2 can't use 110 static struct aspeed_sig_desc sdio1_8bit_link[] = { 111 { 0x414, GENMASK(15, 8), 0 }, 112 { 0x4b4, GENMASK(21, 18), 0 }, 113 { 0x450, BIT(3), 0 }, 114 { 0x450, BIT(1), 1 }, 115 }; 116 117 static struct aspeed_sig_desc emmc_link[] = { 118 { 0x400, GENMASK(31, 24), 0 }, 119 #if 0 //8bit emmc 120 { 0x404, GENMASK(3, 0), 0 }, 121 { 0x500, BIT(3), 1 }, 122 { 0x500, BIT(5), 1 }, 123 #endif 124 }; 125 126 static struct aspeed_sig_desc fmcquad_link[] = { 127 { 0x438, GENMASK(5, 4), 0 }, 128 }; 129 130 static const struct aspeed_group_config ast2600_groups[] = { 131 { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, 132 { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, 133 { "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link }, 134 { "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link }, 135 { "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link }, 136 { "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link }, 137 { "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link }, 138 { "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link }, 139 { "SD1", ARRAY_SIZE(sdio1_link), sdio1_link }, 140 { "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link }, 141 { "SD2", ARRAY_SIZE(sdio2_link), sdio2_link }, 142 { "EMMC", ARRAY_SIZE(emmc_link), emmc_link }, 143 { "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link }, 144 }; 145 146 static int ast2600_pinctrl_get_groups_count(struct udevice *dev) 147 { 148 debug("PINCTRL: get_(functions/groups)_count\n"); 149 150 return ARRAY_SIZE(ast2600_groups); 151 } 152 153 static const char *ast2600_pinctrl_get_group_name(struct udevice *dev, 154 unsigned selector) 155 { 156 debug("PINCTRL: get_(function/group)_name %u\n", selector); 157 158 return ast2600_groups[selector].group_name; 159 } 160 161 static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector, 162 unsigned func_selector) 163 { 164 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 165 const struct aspeed_group_config *config; 166 const struct aspeed_sig_desc *descs; 167 u32 ctrl_reg = (u32)priv->scu; 168 u32 i; 169 170 debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector); 171 if (selector >= ARRAY_SIZE(ast2600_groups)) 172 return -EINVAL; 173 174 config = &ast2600_groups[selector]; 175 for (i = 0; i < config->ndescs; i++) { 176 descs = &config->descs[i]; 177 if (descs->clr) { 178 clrbits_le32((u32)ctrl_reg + descs->offset, 179 descs->reg_set); 180 } else { 181 setbits_le32((u32)ctrl_reg + descs->offset, 182 descs->reg_set); 183 } 184 } 185 186 return 0; 187 } 188 189 static struct pinctrl_ops ast2600_pinctrl_ops = { 190 .set_state = pinctrl_generic_set_state, 191 .get_groups_count = ast2600_pinctrl_get_groups_count, 192 .get_group_name = ast2600_pinctrl_get_group_name, 193 .get_functions_count = ast2600_pinctrl_get_groups_count, 194 .get_function_name = ast2600_pinctrl_get_group_name, 195 .pinmux_group_set = ast2600_pinctrl_group_set, 196 }; 197 198 static const struct udevice_id ast2600_pinctrl_ids[] = { 199 { .compatible = "aspeed,g6-pinctrl" }, 200 { } 201 }; 202 203 U_BOOT_DRIVER(pinctrl_aspeed) = { 204 .name = "aspeed_ast2600_pinctrl", 205 .id = UCLASS_PINCTRL, 206 .of_match = ast2600_pinctrl_ids, 207 .priv_auto_alloc_size = sizeof(struct ast2600_pinctrl_priv), 208 .ops = &ast2600_pinctrl_ops, 209 .probe = ast2600_pinctrl_probe, 210 }; 211