1 /* 2 * Meson GXL and GXM USB2 PHY driver 3 * 4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * Copyright (C) 2018 BayLibre, SAS 6 * Author: Neil Armstrong <narmstron@baylibre.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <bitfield.h> 14 #include <dm.h> 15 #include <errno.h> 16 #include <generic-phy.h> 17 #include <regmap.h> 18 #include <power/regulator.h> 19 #include <clk.h> 20 21 #include <linux/bitops.h> 22 #include <linux/compat.h> 23 24 /* bits [31:27] are read-only */ 25 #define U2P_R0 0x0 26 #define U2P_R0_BYPASS_SEL BIT(0) 27 #define U2P_R0_BYPASS_DM_EN BIT(1) 28 #define U2P_R0_BYPASS_DP_EN BIT(2) 29 #define U2P_R0_TXBITSTUFF_ENH BIT(3) 30 #define U2P_R0_TXBITSTUFF_EN BIT(4) 31 #define U2P_R0_DM_PULLDOWN BIT(5) 32 #define U2P_R0_DP_PULLDOWN BIT(6) 33 #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) 34 #define U2P_R0_DP_VBUS_VLD_EXT BIT(8) 35 #define U2P_R0_ADP_PRB_EN BIT(9) 36 #define U2P_R0_ADP_DISCHARGE BIT(10) 37 #define U2P_R0_ADP_CHARGE BIT(11) 38 #define U2P_R0_DRV_VBUS BIT(12) 39 #define U2P_R0_ID_PULLUP BIT(13) 40 #define U2P_R0_LOOPBACK_EN_B BIT(14) 41 #define U2P_R0_OTG_DISABLE BIT(15) 42 #define U2P_R0_COMMON_ONN BIT(16) 43 #define U2P_R0_FSEL_MASK GENMASK(19, 17) 44 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) 45 #define U2P_R0_POWER_ON_RESET BIT(22) 46 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) 47 #define U2P_R0_ID_SET_ID_DQ BIT(25) 48 #define U2P_R0_ATE_RESET BIT(26) 49 #define U2P_R0_FSV_MINUS BIT(27) 50 #define U2P_R0_FSV_PLUS BIT(28) 51 #define U2P_R0_BYPASS_DM_DATA BIT(29) 52 #define U2P_R0_BYPASS_DP_DATA BIT(30) 53 54 #define U2P_R1 0x4 55 #define U2P_R1_BURN_IN_TEST BIT(0) 56 #define U2P_R1_ACA_ENABLE BIT(1) 57 #define U2P_R1_DCD_ENABLE BIT(2) 58 #define U2P_R1_VDAT_SRC_EN_B BIT(3) 59 #define U2P_R1_VDAT_DET_EN_B BIT(4) 60 #define U2P_R1_CHARGES_SEL BIT(5) 61 #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) 62 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) 63 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) 64 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) 65 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) 66 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) 67 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) 68 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) 69 #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) 70 #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) 71 72 /* bits [31:14] are read-only */ 73 #define U2P_R2 0x8 74 #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0) 75 #define U2P_R2_TESTADDR_MASK GENMASK(11, 8) 76 #define U2P_R2_TESTDATA_OUT_SEL BIT(12) 77 #define U2P_R2_TESTCLK BIT(13) 78 #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14) 79 #define U2P_R2_ACA_PIN_RANGE_C BIT(18) 80 #define U2P_R2_ACA_PIN_RANGE_B BIT(19) 81 #define U2P_R2_ACA_PIN_RANGE_A BIT(20) 82 #define U2P_R2_ACA_PIN_GND BIT(21) 83 #define U2P_R2_ACA_PIN_FLOAT BIT(22) 84 #define U2P_R2_CHARGE_DETECT BIT(23) 85 #define U2P_R2_DEVICE_SESSION_VALID BIT(24) 86 #define U2P_R2_ADP_PROBE BIT(25) 87 #define U2P_R2_ADP_SENSE BIT(26) 88 #define U2P_R2_SESSION_END BIT(27) 89 #define U2P_R2_VBUS_VALID BIT(28) 90 #define U2P_R2_B_VALID BIT(29) 91 #define U2P_R2_A_VALID BIT(30) 92 #define U2P_R2_ID_DIG BIT(31) 93 94 #define U2P_R3 0xc 95 96 #define RESET_COMPLETE_TIME 500 97 98 struct phy_meson_gxl_usb2_priv { 99 struct regmap *regmap; 100 #if CONFIG_IS_ENABLED(DM_REGULATOR) 101 struct udevice *phy_supply; 102 #endif 103 #if CONFIG_IS_ENABLED(CLK) 104 struct clk clk; 105 #endif 106 }; 107 108 static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv) 109 { 110 uint val; 111 112 regmap_read(priv->regmap, U2P_R0, &val); 113 114 /* reset the PHY and wait until settings are stabilized */ 115 val |= U2P_R0_POWER_ON_RESET; 116 regmap_write(priv->regmap, U2P_R0, val); 117 udelay(RESET_COMPLETE_TIME); 118 119 val &= ~U2P_R0_POWER_ON_RESET; 120 regmap_write(priv->regmap, U2P_R0, val); 121 udelay(RESET_COMPLETE_TIME); 122 } 123 124 static void 125 phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv) 126 { 127 uint val; 128 129 regmap_read(priv->regmap, U2P_R0, &val); 130 val |= U2P_R0_DM_PULLDOWN; 131 val |= U2P_R0_DP_PULLDOWN; 132 val &= ~U2P_R0_ID_PULLUP; 133 regmap_write(priv->regmap, U2P_R0, val); 134 135 phy_meson_gxl_usb2_reset(priv); 136 } 137 138 static int phy_meson_gxl_usb2_power_on(struct phy *phy) 139 { 140 struct udevice *dev = phy->dev; 141 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); 142 uint val; 143 144 regmap_read(priv->regmap, U2P_R0, &val); 145 /* power on the PHY by taking it out of reset mode */ 146 val &= ~U2P_R0_POWER_ON_RESET; 147 regmap_write(priv->regmap, U2P_R0, val); 148 149 phy_meson_gxl_usb2_set_host_mode(priv); 150 151 #if CONFIG_IS_ENABLED(DM_REGULATOR) 152 if (priv->phy_supply) { 153 int ret = regulator_set_enable(priv->phy_supply, true); 154 if (ret) 155 return ret; 156 } 157 #endif 158 159 return 0; 160 } 161 162 static int phy_meson_gxl_usb2_power_off(struct phy *phy) 163 { 164 struct udevice *dev = phy->dev; 165 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); 166 uint val; 167 168 regmap_read(priv->regmap, U2P_R0, &val); 169 /* power off the PHY by putting it into reset mode */ 170 val |= U2P_R0_POWER_ON_RESET; 171 regmap_write(priv->regmap, U2P_R0, val); 172 173 #if CONFIG_IS_ENABLED(DM_REGULATOR) 174 if (priv->phy_supply) { 175 int ret = regulator_set_enable(priv->phy_supply, false); 176 if (ret) { 177 pr_err("Error disabling PHY supply\n"); 178 return ret; 179 } 180 } 181 #endif 182 183 return 0; 184 } 185 186 struct phy_ops meson_gxl_usb2_phy_ops = { 187 .power_on = phy_meson_gxl_usb2_power_on, 188 .power_off = phy_meson_gxl_usb2_power_off, 189 }; 190 191 int meson_gxl_usb2_phy_probe(struct udevice *dev) 192 { 193 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); 194 int ret; 195 196 ret = regmap_init_mem(dev, &priv->regmap); 197 if (ret) 198 return ret; 199 200 #if CONFIG_IS_ENABLED(CLK) 201 ret = clk_get_by_index(dev, 0, &priv->clk); 202 if (ret < 0) 203 return ret; 204 205 ret = clk_enable(&priv->clk); 206 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { 207 pr_err("failed to enable PHY clock\n"); 208 clk_free(&priv->clk); 209 return ret; 210 } 211 #endif 212 213 #if CONFIG_IS_ENABLED(DM_REGULATOR) 214 ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); 215 if (ret && ret != -ENOENT) { 216 pr_err("Failed to get PHY regulator\n"); 217 return ret; 218 } 219 #endif 220 221 return 0; 222 } 223 224 static const struct udevice_id meson_gxl_usb2_phy_ids[] = { 225 { .compatible = "amlogic,meson-gxl-usb2-phy" }, 226 { } 227 }; 228 229 U_BOOT_DRIVER(meson_gxl_usb2_phy) = { 230 .name = "meson_gxl_usb2_phy", 231 .id = UCLASS_PHY, 232 .of_match = meson_gxl_usb2_phy_ids, 233 .probe = meson_gxl_usb2_phy_probe, 234 .ops = &meson_gxl_usb2_phy_ops, 235 .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv), 236 }; 237