1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 27d436078SPrabhakar Kushwaha /* 37d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 47d436078SPrabhakar Kushwaha */ 57d436078SPrabhakar Kushwaha #include <common.h> 67d436078SPrabhakar Kushwaha #include <phy.h> 77d436078SPrabhakar Kushwaha #include <fm_eth.h> 87d436078SPrabhakar Kushwaha #include <asm/io.h> 97d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 107d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 117d436078SPrabhakar Kushwaha fman_port_enet_if(enum fm_port port)127d436078SPrabhakar Kushwahaphy_interface_t fman_port_enet_if(enum fm_port port) 137d436078SPrabhakar Kushwaha { 145b7672fcSPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 155b7672fcSPrabhakar Kushwaha u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 165b7672fcSPrabhakar Kushwaha 175b7672fcSPrabhakar Kushwaha /* handle RGMII first */ 185b7672fcSPrabhakar Kushwaha if ((port == FM1_DTSEC2) && 195b7672fcSPrabhakar Kushwaha ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 205b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { 215b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 225b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 235b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 245b7672fcSPrabhakar Kushwaha else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 255b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 265b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_MII; 275b7672fcSPrabhakar Kushwaha } 285b7672fcSPrabhakar Kushwaha 295b7672fcSPrabhakar Kushwaha if ((port == FM1_DTSEC4) && 305b7672fcSPrabhakar Kushwaha ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 315b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { 325b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 335b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 345b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 355b7672fcSPrabhakar Kushwaha else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 365b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 375b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_MII; 385b7672fcSPrabhakar Kushwaha } 395b7672fcSPrabhakar Kushwaha 405b7672fcSPrabhakar Kushwaha if (port == FM1_DTSEC5) { 415b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 425b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) 435b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 445b7672fcSPrabhakar Kushwaha } 455b7672fcSPrabhakar Kushwaha 465b7672fcSPrabhakar Kushwaha switch (port) { 475b7672fcSPrabhakar Kushwaha case FM1_DTSEC1: 485b7672fcSPrabhakar Kushwaha case FM1_DTSEC2: 4927b57569SCodrin Ciubotariu if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || 5027b57569SCodrin Ciubotariu is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) 515b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_QSGMII; 525b7672fcSPrabhakar Kushwaha case FM1_DTSEC3: 535b7672fcSPrabhakar Kushwaha case FM1_DTSEC4: 545b7672fcSPrabhakar Kushwaha case FM1_DTSEC5: 555b7672fcSPrabhakar Kushwaha if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 565b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_SGMII; 575b7672fcSPrabhakar Kushwaha break; 585b7672fcSPrabhakar Kushwaha default: 595b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 605b7672fcSPrabhakar Kushwaha } 615b7672fcSPrabhakar Kushwaha 627d436078SPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 637d436078SPrabhakar Kushwaha } 64