1*f6050790SShengzhou Liu /* Copyright 2014 Freescale Semiconductor, Inc. 2*f6050790SShengzhou Liu * 3*f6050790SShengzhou Liu * Shengzhou Liu <Shengzhou.Liu@freescale.com> 4*f6050790SShengzhou Liu * 5*f6050790SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 6*f6050790SShengzhou Liu */ 7*f6050790SShengzhou Liu 8*f6050790SShengzhou Liu #include <common.h> 9*f6050790SShengzhou Liu #include <phy.h> 10*f6050790SShengzhou Liu #include <fm_eth.h> 11*f6050790SShengzhou Liu #include <asm/immap_85xx.h> 12*f6050790SShengzhou Liu #include <asm/fsl_serdes.h> 13*f6050790SShengzhou Liu 14*f6050790SShengzhou Liu u32 port_to_devdisr[] = { 15*f6050790SShengzhou Liu [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16*f6050790SShengzhou Liu [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17*f6050790SShengzhou Liu [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18*f6050790SShengzhou Liu [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19*f6050790SShengzhou Liu [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ 20*f6050790SShengzhou Liu }; 21*f6050790SShengzhou Liu 22*f6050790SShengzhou Liu static int is_device_disabled(enum fm_port port) 23*f6050790SShengzhou Liu { 24*f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 25*f6050790SShengzhou Liu u32 devdisr2 = in_be32(&gur->devdisr2); 26*f6050790SShengzhou Liu 27*f6050790SShengzhou Liu return port_to_devdisr[port] & devdisr2; 28*f6050790SShengzhou Liu } 29*f6050790SShengzhou Liu 30*f6050790SShengzhou Liu void fman_disable_port(enum fm_port port) 31*f6050790SShengzhou Liu { 32*f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33*f6050790SShengzhou Liu 34*f6050790SShengzhou Liu setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 35*f6050790SShengzhou Liu } 36*f6050790SShengzhou Liu 37*f6050790SShengzhou Liu phy_interface_t fman_port_enet_if(enum fm_port port) 38*f6050790SShengzhou Liu { 39*f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 40*f6050790SShengzhou Liu u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 41*f6050790SShengzhou Liu 42*f6050790SShengzhou Liu if (is_device_disabled(port)) 43*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_NONE; 44*f6050790SShengzhou Liu 45*f6050790SShengzhou Liu if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) 46*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_XGMII; 47*f6050790SShengzhou Liu 48*f6050790SShengzhou Liu if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 49*f6050790SShengzhou Liu FSL_CORENET_RCWSR13_EC2_RGMII) && 50*f6050790SShengzhou Liu (!is_serdes_configured(QSGMII_FM1_A))) 51*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_RGMII; 52*f6050790SShengzhou Liu 53*f6050790SShengzhou Liu if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 54*f6050790SShengzhou Liu FSL_CORENET_RCWSR13_EC1_RGMII) && 55*f6050790SShengzhou Liu (!is_serdes_configured(QSGMII_FM1_A))) 56*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_RGMII; 57*f6050790SShengzhou Liu 58*f6050790SShengzhou Liu /* handle SGMII */ 59*f6050790SShengzhou Liu switch (port) { 60*f6050790SShengzhou Liu case FM1_DTSEC1: 61*f6050790SShengzhou Liu case FM1_DTSEC2: 62*f6050790SShengzhou Liu case FM1_DTSEC3: 63*f6050790SShengzhou Liu if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 64*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_SGMII; 65*f6050790SShengzhou Liu else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 66*f6050790SShengzhou Liu + port - FM1_DTSEC1)) 67*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_SGMII_2500; 68*f6050790SShengzhou Liu break; 69*f6050790SShengzhou Liu default: 70*f6050790SShengzhou Liu break; 71*f6050790SShengzhou Liu } 72*f6050790SShengzhou Liu 73*f6050790SShengzhou Liu /* handle QSGMII */ 74*f6050790SShengzhou Liu switch (port) { 75*f6050790SShengzhou Liu case FM1_DTSEC1: 76*f6050790SShengzhou Liu case FM1_DTSEC2: 77*f6050790SShengzhou Liu case FM1_DTSEC3: 78*f6050790SShengzhou Liu case FM1_DTSEC4: 79*f6050790SShengzhou Liu /* check lane A on SerDes1 */ 80*f6050790SShengzhou Liu if (is_serdes_configured(QSGMII_FM1_A)) 81*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_QSGMII; 82*f6050790SShengzhou Liu break; 83*f6050790SShengzhou Liu default: 84*f6050790SShengzhou Liu break; 85*f6050790SShengzhou Liu } 86*f6050790SShengzhou Liu 87*f6050790SShengzhou Liu return PHY_INTERFACE_MODE_NONE; 88*f6050790SShengzhou Liu } 89