1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2f6050790SShengzhou Liu /* Copyright 2014 Freescale Semiconductor, Inc. 3f6050790SShengzhou Liu * 4f6050790SShengzhou Liu * Shengzhou Liu <Shengzhou.Liu@freescale.com> 5f6050790SShengzhou Liu */ 6f6050790SShengzhou Liu 7f6050790SShengzhou Liu #include <common.h> 8f6050790SShengzhou Liu #include <phy.h> 9f6050790SShengzhou Liu #include <fm_eth.h> 10f6050790SShengzhou Liu #include <asm/immap_85xx.h> 11f6050790SShengzhou Liu #include <asm/fsl_serdes.h> 12f6050790SShengzhou Liu 13f6050790SShengzhou Liu u32 port_to_devdisr[] = { 14f6050790SShengzhou Liu [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 15f6050790SShengzhou Liu [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 16f6050790SShengzhou Liu [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 17f6050790SShengzhou Liu [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 18f6050790SShengzhou Liu [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ 19f6050790SShengzhou Liu }; 20f6050790SShengzhou Liu is_device_disabled(enum fm_port port)21f6050790SShengzhou Liustatic int is_device_disabled(enum fm_port port) 22f6050790SShengzhou Liu { 23f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 24f6050790SShengzhou Liu u32 devdisr2 = in_be32(&gur->devdisr2); 25f6050790SShengzhou Liu 26f6050790SShengzhou Liu return port_to_devdisr[port] & devdisr2; 27f6050790SShengzhou Liu } 28f6050790SShengzhou Liu fman_disable_port(enum fm_port port)29f6050790SShengzhou Liuvoid fman_disable_port(enum fm_port port) 30f6050790SShengzhou Liu { 31f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 32f6050790SShengzhou Liu 33f6050790SShengzhou Liu setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 34f6050790SShengzhou Liu } 35f6050790SShengzhou Liu fman_port_enet_if(enum fm_port port)36f6050790SShengzhou Liuphy_interface_t fman_port_enet_if(enum fm_port port) 37f6050790SShengzhou Liu { 38f6050790SShengzhou Liu ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 39f6050790SShengzhou Liu u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 40f6050790SShengzhou Liu 41f6050790SShengzhou Liu if (is_device_disabled(port)) 42f6050790SShengzhou Liu return PHY_INTERFACE_MODE_NONE; 43f6050790SShengzhou Liu 44f6050790SShengzhou Liu if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) 45f6050790SShengzhou Liu return PHY_INTERFACE_MODE_XGMII; 46f6050790SShengzhou Liu 47f6050790SShengzhou Liu if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 48f6050790SShengzhou Liu FSL_CORENET_RCWSR13_EC2_RGMII) && 49f6050790SShengzhou Liu (!is_serdes_configured(QSGMII_FM1_A))) 50f6050790SShengzhou Liu return PHY_INTERFACE_MODE_RGMII; 51f6050790SShengzhou Liu 52f6050790SShengzhou Liu if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 53f6050790SShengzhou Liu FSL_CORENET_RCWSR13_EC1_RGMII) && 54f6050790SShengzhou Liu (!is_serdes_configured(QSGMII_FM1_A))) 55f6050790SShengzhou Liu return PHY_INTERFACE_MODE_RGMII; 56f6050790SShengzhou Liu 57f6050790SShengzhou Liu /* handle SGMII */ 58f6050790SShengzhou Liu switch (port) { 59f6050790SShengzhou Liu case FM1_DTSEC1: 60f6050790SShengzhou Liu case FM1_DTSEC2: 61f6050790SShengzhou Liu case FM1_DTSEC3: 62f6050790SShengzhou Liu if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 63f6050790SShengzhou Liu return PHY_INTERFACE_MODE_SGMII; 64f6050790SShengzhou Liu else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 65f6050790SShengzhou Liu + port - FM1_DTSEC1)) 66f6050790SShengzhou Liu return PHY_INTERFACE_MODE_SGMII_2500; 67f6050790SShengzhou Liu break; 68f6050790SShengzhou Liu default: 69f6050790SShengzhou Liu break; 70f6050790SShengzhou Liu } 71f6050790SShengzhou Liu 72f6050790SShengzhou Liu /* handle QSGMII */ 73f6050790SShengzhou Liu switch (port) { 74f6050790SShengzhou Liu case FM1_DTSEC1: 75f6050790SShengzhou Liu case FM1_DTSEC2: 76f6050790SShengzhou Liu case FM1_DTSEC3: 77f6050790SShengzhou Liu case FM1_DTSEC4: 78f6050790SShengzhou Liu /* check lane A on SerDes1 */ 79f6050790SShengzhou Liu if (is_serdes_configured(QSGMII_FM1_A)) 80f6050790SShengzhou Liu return PHY_INTERFACE_MODE_QSGMII; 81f6050790SShengzhou Liu break; 82f6050790SShengzhou Liu default: 83f6050790SShengzhou Liu break; 84f6050790SShengzhou Liu } 85f6050790SShengzhou Liu 86f6050790SShengzhou Liu return PHY_INTERFACE_MODE_NONE; 87f6050790SShengzhou Liu } 88