1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 #include <common.h> 20 #include <phy.h> 21 #include <fm_eth.h> 22 #include <asm/io.h> 23 #include <asm/immap_85xx.h> 24 #include <asm/fsl_serdes.h> 25 26 u32 port_to_devdisr[] = { 27 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 28 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 29 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 30 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 31 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, 32 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, 33 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, 34 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, 35 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, 36 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, 37 }; 38 39 static int is_device_disabled(enum fm_port port) 40 { 41 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42 u32 devdisr2 = in_be32(&gur->devdisr2); 43 44 return port_to_devdisr[port] & devdisr2; 45 } 46 47 phy_interface_t fman_port_enet_if(enum fm_port port) 48 { 49 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 51 52 if (is_device_disabled(port)) 53 return PHY_INTERFACE_MODE_NONE; 54 55 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) 56 return PHY_INTERFACE_MODE_XGMII; 57 58 if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) 59 return PHY_INTERFACE_MODE_XGMII; 60 61 /* handle RGMII first */ 62 if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == 63 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) 64 return PHY_INTERFACE_MODE_RGMII; 65 66 if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 67 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) 68 return PHY_INTERFACE_MODE_RGMII; 69 70 if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == 71 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) 72 return PHY_INTERFACE_MODE_RGMII; 73 74 switch (port) { 75 case FM1_DTSEC1: 76 case FM1_DTSEC2: 77 case FM1_DTSEC3: 78 case FM1_DTSEC4: 79 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 80 return PHY_INTERFACE_MODE_SGMII; 81 break; 82 case FM2_DTSEC1: 83 case FM2_DTSEC2: 84 case FM2_DTSEC3: 85 case FM2_DTSEC4: 86 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) 87 return PHY_INTERFACE_MODE_SGMII; 88 break; 89 default: 90 return PHY_INTERFACE_MODE_NONE; 91 } 92 93 return PHY_INTERFACE_MODE_NONE; 94 } 95