1*9ecb0c41SVikas Manocha struct stm32_flash_regs { 2*9ecb0c41SVikas Manocha u32 acr; 3*9ecb0c41SVikas Manocha u32 key; 4*9ecb0c41SVikas Manocha u32 optkeyr; 5*9ecb0c41SVikas Manocha u32 sr; 6*9ecb0c41SVikas Manocha u32 cr; 7*9ecb0c41SVikas Manocha u32 optcr; 8*9ecb0c41SVikas Manocha u32 optcr1; 9*9ecb0c41SVikas Manocha }; 10*9ecb0c41SVikas Manocha 11*9ecb0c41SVikas Manocha #define STM32_FLASH_KEY1 0x45670123 12*9ecb0c41SVikas Manocha #define STM32_FLASH_KEY2 0xCDEF89AB 13*9ecb0c41SVikas Manocha 14*9ecb0c41SVikas Manocha #define STM32_FLASH_SR_BSY (1 << 16) 15*9ecb0c41SVikas Manocha 16*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_PG (1 << 0) 17*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_SER (1 << 1) 18*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_STRT (1 << 16) 19*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_LOCK (1 << 31) 20*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_SNB_OFFSET 3 21*9ecb0c41SVikas Manocha #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) 22*9ecb0c41SVikas Manocha 23*9ecb0c41SVikas Manocha /* Flash ACR: Access control register */ 24*9ecb0c41SVikas Manocha #define FLASH_ACR_WS(n) n 25*9ecb0c41SVikas Manocha #define FLASH_ACR_PRFTEN (1 << 8) 26*9ecb0c41SVikas Manocha #define FLASH_ACR_ICEN (1 << 9) 27*9ecb0c41SVikas Manocha #define FLASH_ACR_DCEN (1 << 10) 28