1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2016 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <dm/device.h> 13 #include <errno.h> 14 #include <asm/gpio.h> 15 #include <asm/io.h> 16 #ifndef CONFIG_TEGRA186 17 #include <asm/arch/clock.h> 18 #include <asm/arch-tegra/clk_rst.h> 19 #endif 20 #include <asm/arch-tegra/tegra_mmc.h> 21 #include <mmc.h> 22 23 /* 24 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that 25 * should not be present. These are needed because newer Tegra SoCs support 26 * only the standard clock/reset APIs, whereas older Tegra SoCs support only 27 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be 28 * fixed to implement the standard APIs, and all drivers converted to solely 29 * use the new standard APIs, with no ifdefs. 30 */ 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 struct tegra_mmc_priv { 35 struct tegra_mmc *reg; 36 #ifdef CONFIG_TEGRA186 37 struct reset_ctl reset_ctl; 38 struct clk clk; 39 #else 40 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ 41 #endif 42 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 43 struct gpio_desc pwr_gpio; /* Power GPIO */ 44 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 45 unsigned int version; /* SDHCI spec. version */ 46 unsigned int clock; /* Current clock (MHz) */ 47 struct mmc_config cfg; /* mmc configuration */ 48 struct mmc *mmc; 49 }; 50 51 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 52 unsigned short power) 53 { 54 u8 pwr = 0; 55 debug("%s: power = %x\n", __func__, power); 56 57 if (power != (unsigned short)-1) { 58 switch (1 << power) { 59 case MMC_VDD_165_195: 60 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 61 break; 62 case MMC_VDD_29_30: 63 case MMC_VDD_30_31: 64 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 65 break; 66 case MMC_VDD_32_33: 67 case MMC_VDD_33_34: 68 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 69 break; 70 } 71 } 72 debug("%s: pwr = %X\n", __func__, pwr); 73 74 /* Set the bus voltage first (if any) */ 75 writeb(pwr, &priv->reg->pwrcon); 76 if (pwr == 0) 77 return; 78 79 /* Now enable bus power */ 80 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 81 writeb(pwr, &priv->reg->pwrcon); 82 } 83 84 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 85 struct mmc_data *data, 86 struct bounce_buffer *bbstate) 87 { 88 unsigned char ctrl; 89 90 91 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 92 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 93 data->blocksize); 94 95 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 96 /* 97 * DMASEL[4:3] 98 * 00 = Selects SDMA 99 * 01 = Reserved 100 * 10 = Selects 32-bit Address ADMA2 101 * 11 = Selects 64-bit Address ADMA2 102 */ 103 ctrl = readb(&priv->reg->hostctl); 104 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 105 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 106 writeb(ctrl, &priv->reg->hostctl); 107 108 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 109 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 110 writew(data->blocks, &priv->reg->blkcnt); 111 } 112 113 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 114 struct mmc_data *data) 115 { 116 unsigned short mode; 117 debug(" mmc_set_transfer_mode called\n"); 118 /* 119 * TRNMOD 120 * MUL1SIN0[5] : Multi/Single Block Select 121 * RD1WT0[4] : Data Transfer Direction Select 122 * 1 = read 123 * 0 = write 124 * ENACMD12[2] : Auto CMD12 Enable 125 * ENBLKCNT[1] : Block Count Enable 126 * ENDMA[0] : DMA Enable 127 */ 128 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 129 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 130 131 if (data->blocks > 1) 132 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 133 134 if (data->flags & MMC_DATA_READ) 135 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 136 137 writew(mode, &priv->reg->trnmod); 138 } 139 140 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 141 struct mmc_cmd *cmd, 142 struct mmc_data *data, 143 unsigned int timeout) 144 { 145 /* 146 * PRNSTS 147 * CMDINHDAT[1] : Command Inhibit (DAT) 148 * CMDINHCMD[0] : Command Inhibit (CMD) 149 */ 150 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 151 152 /* 153 * We shouldn't wait for data inhibit for stop commands, even 154 * though they might use busy signaling 155 */ 156 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 157 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 158 159 while (readl(&priv->reg->prnsts) & mask) { 160 if (timeout == 0) { 161 printf("%s: timeout error\n", __func__); 162 return -1; 163 } 164 timeout--; 165 udelay(1000); 166 } 167 168 return 0; 169 } 170 171 static int tegra_mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 172 struct mmc_data *data, 173 struct bounce_buffer *bbstate) 174 { 175 struct tegra_mmc_priv *priv = mmc->priv; 176 int flags, i; 177 int result; 178 unsigned int mask = 0; 179 unsigned int retry = 0x100000; 180 debug(" mmc_send_cmd called\n"); 181 182 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 183 184 if (result < 0) 185 return result; 186 187 if (data) 188 tegra_mmc_prepare_data(priv, data, bbstate); 189 190 debug("cmd->arg: %08x\n", cmd->cmdarg); 191 writel(cmd->cmdarg, &priv->reg->argument); 192 193 if (data) 194 tegra_mmc_set_transfer_mode(priv, data); 195 196 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 197 return -1; 198 199 /* 200 * CMDREG 201 * CMDIDX[13:8] : Command index 202 * DATAPRNT[5] : Data Present Select 203 * ENCMDIDX[4] : Command Index Check Enable 204 * ENCMDCRC[3] : Command CRC Check Enable 205 * RSPTYP[1:0] 206 * 00 = No Response 207 * 01 = Length 136 208 * 10 = Length 48 209 * 11 = Length 48 Check busy after response 210 */ 211 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 212 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 213 else if (cmd->resp_type & MMC_RSP_136) 214 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 215 else if (cmd->resp_type & MMC_RSP_BUSY) 216 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 217 else 218 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 219 220 if (cmd->resp_type & MMC_RSP_CRC) 221 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 222 if (cmd->resp_type & MMC_RSP_OPCODE) 223 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 224 if (data) 225 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 226 227 debug("cmd: %d\n", cmd->cmdidx); 228 229 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 230 231 for (i = 0; i < retry; i++) { 232 mask = readl(&priv->reg->norintsts); 233 /* Command Complete */ 234 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 235 if (!data) 236 writel(mask, &priv->reg->norintsts); 237 break; 238 } 239 } 240 241 if (i == retry) { 242 printf("%s: waiting for status update\n", __func__); 243 writel(mask, &priv->reg->norintsts); 244 return -ETIMEDOUT; 245 } 246 247 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 248 /* Timeout Error */ 249 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 250 writel(mask, &priv->reg->norintsts); 251 return -ETIMEDOUT; 252 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 253 /* Error Interrupt */ 254 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 255 writel(mask, &priv->reg->norintsts); 256 return -1; 257 } 258 259 if (cmd->resp_type & MMC_RSP_PRESENT) { 260 if (cmd->resp_type & MMC_RSP_136) { 261 /* CRC is stripped so we need to do some shifting. */ 262 for (i = 0; i < 4; i++) { 263 unsigned long offset = (unsigned long) 264 (&priv->reg->rspreg3 - i); 265 cmd->response[i] = readl(offset) << 8; 266 267 if (i != 3) { 268 cmd->response[i] |= 269 readb(offset - 1); 270 } 271 debug("cmd->resp[%d]: %08x\n", 272 i, cmd->response[i]); 273 } 274 } else if (cmd->resp_type & MMC_RSP_BUSY) { 275 for (i = 0; i < retry; i++) { 276 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 277 if (readl(&priv->reg->prnsts) 278 & (1 << 20)) /* DAT[0] */ 279 break; 280 } 281 282 if (i == retry) { 283 printf("%s: card is still busy\n", __func__); 284 writel(mask, &priv->reg->norintsts); 285 return -ETIMEDOUT; 286 } 287 288 cmd->response[0] = readl(&priv->reg->rspreg0); 289 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 290 } else { 291 cmd->response[0] = readl(&priv->reg->rspreg0); 292 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 293 } 294 } 295 296 if (data) { 297 unsigned long start = get_timer(0); 298 299 while (1) { 300 mask = readl(&priv->reg->norintsts); 301 302 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 303 /* Error Interrupt */ 304 writel(mask, &priv->reg->norintsts); 305 printf("%s: error during transfer: 0x%08x\n", 306 __func__, mask); 307 return -1; 308 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 309 /* 310 * DMA Interrupt, restart the transfer where 311 * it was interrupted. 312 */ 313 unsigned int address = readl(&priv->reg->sysad); 314 315 debug("DMA end\n"); 316 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 317 &priv->reg->norintsts); 318 writel(address, &priv->reg->sysad); 319 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 320 /* Transfer Complete */ 321 debug("r/w is done\n"); 322 break; 323 } else if (get_timer(start) > 8000UL) { 324 writel(mask, &priv->reg->norintsts); 325 printf("%s: MMC Timeout\n" 326 " Interrupt status 0x%08x\n" 327 " Interrupt status enable 0x%08x\n" 328 " Interrupt signal enable 0x%08x\n" 329 " Present status 0x%08x\n", 330 __func__, mask, 331 readl(&priv->reg->norintstsen), 332 readl(&priv->reg->norintsigen), 333 readl(&priv->reg->prnsts)); 334 return -1; 335 } 336 } 337 writel(mask, &priv->reg->norintsts); 338 } 339 340 udelay(1000); 341 return 0; 342 } 343 344 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 345 struct mmc_data *data) 346 { 347 void *buf; 348 unsigned int bbflags; 349 size_t len; 350 struct bounce_buffer bbstate; 351 int ret; 352 353 if (data) { 354 if (data->flags & MMC_DATA_READ) { 355 buf = data->dest; 356 bbflags = GEN_BB_WRITE; 357 } else { 358 buf = (void *)data->src; 359 bbflags = GEN_BB_READ; 360 } 361 len = data->blocks * data->blocksize; 362 363 bounce_buffer_start(&bbstate, buf, len, bbflags); 364 } 365 366 ret = tegra_mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 367 368 if (data) 369 bounce_buffer_stop(&bbstate); 370 371 return ret; 372 } 373 374 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 375 { 376 int div; 377 unsigned short clk; 378 unsigned long timeout; 379 380 debug(" mmc_change_clock called\n"); 381 382 /* 383 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 384 */ 385 if (clock == 0) 386 goto out; 387 #ifdef CONFIG_TEGRA186 388 { 389 ulong rate = clk_set_rate(&priv->clk, clock); 390 div = (rate + clock - 1) / clock; 391 } 392 #else 393 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock, 394 &div); 395 #endif 396 debug("div = %d\n", div); 397 398 writew(0, &priv->reg->clkcon); 399 400 /* 401 * CLKCON 402 * SELFREQ[15:8] : base clock divided by value 403 * ENSDCLK[2] : SD Clock Enable 404 * STBLINTCLK[1] : Internal Clock Stable 405 * ENINTCLK[0] : Internal Clock Enable 406 */ 407 div >>= 1; 408 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 409 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 410 writew(clk, &priv->reg->clkcon); 411 412 /* Wait max 10 ms */ 413 timeout = 10; 414 while (!(readw(&priv->reg->clkcon) & 415 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 416 if (timeout == 0) { 417 printf("%s: timeout error\n", __func__); 418 return; 419 } 420 timeout--; 421 udelay(1000); 422 } 423 424 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 425 writew(clk, &priv->reg->clkcon); 426 427 debug("mmc_change_clock: clkcon = %08X\n", clk); 428 429 out: 430 priv->clock = clock; 431 } 432 433 static void tegra_mmc_set_ios(struct mmc *mmc) 434 { 435 struct tegra_mmc_priv *priv = mmc->priv; 436 unsigned char ctrl; 437 debug(" mmc_set_ios called\n"); 438 439 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 440 441 /* Change clock first */ 442 tegra_mmc_change_clock(priv, mmc->clock); 443 444 ctrl = readb(&priv->reg->hostctl); 445 446 /* 447 * WIDE8[5] 448 * 0 = Depend on WIDE4 449 * 1 = 8-bit mode 450 * WIDE4[1] 451 * 1 = 4-bit mode 452 * 0 = 1-bit mode 453 */ 454 if (mmc->bus_width == 8) 455 ctrl |= (1 << 5); 456 else if (mmc->bus_width == 4) 457 ctrl |= (1 << 1); 458 else 459 ctrl &= ~(1 << 1); 460 461 writeb(ctrl, &priv->reg->hostctl); 462 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 463 } 464 465 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 466 { 467 #if defined(CONFIG_TEGRA30) 468 u32 val; 469 470 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); 471 472 /* Set the pad drive strength for SDMMC1 or 3 only */ 473 if (priv->reg != (void *)0x78000000 && 474 priv->reg != (void *)0x78000400) { 475 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 476 __func__); 477 return; 478 } 479 480 val = readl(&priv->reg->sdmemcmppadctl); 481 val &= 0xFFFFFFF0; 482 val |= MEMCOMP_PADCTRL_VREF; 483 writel(val, &priv->reg->sdmemcmppadctl); 484 485 val = readl(&priv->reg->autocalcfg); 486 val &= 0xFFFF0000; 487 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 488 writel(val, &priv->reg->autocalcfg); 489 #endif 490 } 491 492 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 493 { 494 unsigned int timeout; 495 debug(" mmc_reset called\n"); 496 497 /* 498 * RSTALL[0] : Software reset for all 499 * 1 = reset 500 * 0 = work 501 */ 502 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 503 504 priv->clock = 0; 505 506 /* Wait max 100 ms */ 507 timeout = 100; 508 509 /* hw clears the bit when it's done */ 510 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 511 if (timeout == 0) { 512 printf("%s: timeout error\n", __func__); 513 return; 514 } 515 timeout--; 516 udelay(1000); 517 } 518 519 /* Set SD bus voltage & enable bus power */ 520 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 521 debug("%s: power control = %02X, host control = %02X\n", __func__, 522 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 523 524 /* Make sure SDIO pads are set up */ 525 tegra_mmc_pad_init(priv); 526 } 527 528 static int tegra_mmc_init(struct mmc *mmc) 529 { 530 struct tegra_mmc_priv *priv = mmc->priv; 531 unsigned int mask; 532 debug(" tegra_mmc_init called\n"); 533 534 tegra_mmc_reset(priv, mmc); 535 536 priv->version = readw(&priv->reg->hcver); 537 debug("host version = %x\n", priv->version); 538 539 /* mask all */ 540 writel(0xffffffff, &priv->reg->norintstsen); 541 writel(0xffffffff, &priv->reg->norintsigen); 542 543 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 544 /* 545 * NORMAL Interrupt Status Enable Register init 546 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 547 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 548 * [3] ENSTADMAINT : DMA boundary interrupt 549 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 550 * [0] ENSTACMDCMPLT : Command Complete Status Enable 551 */ 552 mask = readl(&priv->reg->norintstsen); 553 mask &= ~(0xffff); 554 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 555 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 556 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 557 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 558 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 559 writel(mask, &priv->reg->norintstsen); 560 561 /* 562 * NORMAL Interrupt Signal Enable Register init 563 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 564 */ 565 mask = readl(&priv->reg->norintsigen); 566 mask &= ~(0xffff); 567 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 568 writel(mask, &priv->reg->norintsigen); 569 570 return 0; 571 } 572 573 static int tegra_mmc_getcd(struct mmc *mmc) 574 { 575 struct tegra_mmc_priv *priv = mmc->priv; 576 577 debug("tegra_mmc_getcd called\n"); 578 579 if (dm_gpio_is_valid(&priv->cd_gpio)) 580 return dm_gpio_get_value(&priv->cd_gpio); 581 582 return 1; 583 } 584 585 static const struct mmc_ops tegra_mmc_ops = { 586 .send_cmd = tegra_mmc_send_cmd, 587 .set_ios = tegra_mmc_set_ios, 588 .init = tegra_mmc_init, 589 .getcd = tegra_mmc_getcd, 590 }; 591 592 static int tegra_mmc_probe(struct udevice *dev) 593 { 594 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 595 struct tegra_mmc_priv *priv = dev_get_priv(dev); 596 int bus_width; 597 #ifdef CONFIG_TEGRA186 598 int ret; 599 #endif 600 601 priv->cfg.name = "Tegra SD/MMC"; 602 priv->cfg.ops = &tegra_mmc_ops; 603 604 bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 605 1); 606 607 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 608 priv->cfg.host_caps = 0; 609 if (bus_width == 8) 610 priv->cfg.host_caps |= MMC_MODE_8BIT; 611 if (bus_width >= 4) 612 priv->cfg.host_caps |= MMC_MODE_4BIT; 613 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 614 615 /* 616 * min freq is for card identification, and is the highest 617 * low-speed SDIO card frequency (actually 400KHz) 618 * max freq is highest HS eMMC clock as per the SD/MMC spec 619 * (actually 52MHz) 620 */ 621 priv->cfg.f_min = 375000; 622 priv->cfg.f_max = 48000000; 623 624 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 625 626 priv->reg = (void *)dev_get_addr(dev); 627 628 #ifdef CONFIG_TEGRA186 629 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); 630 if (ret) { 631 debug("reset_get_by_name() failed: %d\n", ret); 632 return ret; 633 } 634 ret = clk_get_by_index(dev, 0, &priv->clk); 635 if (ret) { 636 debug("clk_get_by_index() failed: %d\n", ret); 637 return ret; 638 } 639 640 ret = reset_assert(&priv->reset_ctl); 641 if (ret) 642 return ret; 643 ret = clk_enable(&priv->clk); 644 if (ret) 645 return ret; 646 ret = clk_set_rate(&priv->clk, 20000000); 647 if (IS_ERR_VALUE(ret)) 648 return ret; 649 ret = reset_deassert(&priv->reset_ctl); 650 if (ret) 651 return ret; 652 #else 653 priv->mmc_id = clock_decode_periph_id(gd->fdt_blob, dev->of_offset); 654 if (priv->mmc_id == PERIPH_ID_NONE) { 655 debug("%s: could not decode periph id\n", __func__); 656 return -FDT_ERR_NOTFOUND; 657 } 658 659 clock_start_periph_pll(priv->mmc_id, CLOCK_ID_PERIPH, 20000000); 660 #endif 661 662 /* These GPIOs are optional */ 663 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 664 GPIOD_IS_IN); 665 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 666 GPIOD_IS_IN); 667 gpio_request_by_name(dev, "power-gpios", 0, 668 &priv->pwr_gpio, GPIOD_IS_OUT); 669 if (dm_gpio_is_valid(&priv->pwr_gpio)) 670 dm_gpio_set_value(&priv->pwr_gpio, 1); 671 672 priv->mmc = mmc_create(&priv->cfg, priv); 673 if (priv->mmc == NULL) 674 return -1; 675 676 priv->mmc->dev = dev; 677 upriv->mmc = priv->mmc; 678 679 return 0; 680 } 681 682 static const struct udevice_id tegra_mmc_ids[] = { 683 { .compatible = "nvidia,tegra20-sdhci" }, 684 { .compatible = "nvidia,tegra30-sdhci" }, 685 { .compatible = "nvidia,tegra114-sdhci" }, 686 { .compatible = "nvidia,tegra124-sdhci" }, 687 { .compatible = "nvidia,tegra210-sdhci" }, 688 { .compatible = "nvidia,tegra186-sdhci" }, 689 { } 690 }; 691 692 U_BOOT_DRIVER(tegra_mmc_drv) = { 693 .name = "tegra_mmc", 694 .id = UCLASS_MMC, 695 .of_match = tegra_mmc_ids, 696 .probe = tegra_mmc_probe, 697 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv), 698 }; 699