1 /* 2 * Copyright (c) 2017 3 * Patrice Chotard <patrice.chotard@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <mmc.h> 11 #include <sdhci.h> 12 #include <asm/arch/sdhci.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct sti_sdhci_plat { 17 struct mmc_config cfg; 18 struct mmc mmc; 19 int instance; 20 }; 21 22 /* 23 * used to get access to MMC1 reset, 24 * will be removed when STi reset driver will be available 25 */ 26 #define STIH410_SYSCONF5_BASE 0x092b0000 27 28 /** 29 * sti_mmc_core_config: configure the Arasan HC 30 * @dev : udevice 31 * 32 * Description: this function is to configure the Arasan MMC HC. 33 * This should be called when the system starts in case of, on the SoC, 34 * it is needed to configure the host controller. 35 * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS 36 * needs to be configured as MMC 4.5 to have full capabilities. 37 * W/o these settings the SDHCI could configure and use the embedded controller 38 * with limited features. 39 */ 40 static void sti_mmc_core_config(struct udevice *dev) 41 { 42 struct sti_sdhci_plat *plat = dev_get_platdata(dev); 43 struct sdhci_host *host = dev_get_priv(dev); 44 unsigned long *sysconf; 45 46 /* only MMC1 has a reset line */ 47 if (plat->instance) { 48 sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE + 49 ST_MMC_CCONFIG_REG_5); 50 generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf); 51 } 52 53 writel(STI_FLASHSS_MMC_CORE_CONFIG_1, 54 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1); 55 56 if (plat->instance) { 57 writel(STI_FLASHSS_MMC_CORE_CONFIG2, 58 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); 59 writel(STI_FLASHSS_MMC_CORE_CONFIG3, 60 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); 61 } else { 62 writel(STI_FLASHSS_SDCARD_CORE_CONFIG2, 63 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); 64 writel(STI_FLASHSS_SDCARD_CORE_CONFIG3, 65 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); 66 } 67 writel(STI_FLASHSS_MMC_CORE_CONFIG4, 68 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4); 69 } 70 71 static int sti_sdhci_probe(struct udevice *dev) 72 { 73 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 74 struct sti_sdhci_plat *plat = dev_get_platdata(dev); 75 struct sdhci_host *host = dev_get_priv(dev); 76 int ret; 77 78 /* 79 * identify current mmc instance, mmc1 has a reset, not mmc0 80 * MMC0 is wired to the SD slot, 81 * MMC1 is wired on the high speed connector 82 */ 83 84 if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL)) 85 plat->instance = 1; 86 else 87 plat->instance = 0; 88 89 sti_mmc_core_config(dev); 90 91 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | 92 SDHCI_QUIRK_32BIT_DMA_ADDR | 93 SDHCI_QUIRK_NO_HISPD_BIT; 94 95 host->host_caps = MMC_MODE_DDR_52MHz; 96 97 ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000); 98 if (ret) 99 return ret; 100 101 host->mmc = &plat->mmc; 102 host->mmc->priv = host; 103 host->mmc->dev = dev; 104 upriv->mmc = host->mmc; 105 106 return sdhci_probe(dev); 107 } 108 109 static int sti_sdhci_ofdata_to_platdata(struct udevice *dev) 110 { 111 struct sdhci_host *host = dev_get_priv(dev); 112 113 host->name = strdup(dev->name); 114 host->ioaddr = (void *)devfdt_get_addr(dev); 115 116 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 117 "bus-width", 4); 118 119 return 0; 120 } 121 122 static int sti_sdhci_bind(struct udevice *dev) 123 { 124 struct sti_sdhci_plat *plat = dev_get_platdata(dev); 125 126 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 127 } 128 129 static const struct udevice_id sti_sdhci_ids[] = { 130 { .compatible = "st,sdhci" }, 131 { } 132 }; 133 134 U_BOOT_DRIVER(sti_mmc) = { 135 .name = "sti_sdhci", 136 .id = UCLASS_MMC, 137 .of_match = sti_sdhci_ids, 138 .bind = sti_sdhci_bind, 139 .ops = &sdhci_ops, 140 .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata, 141 .probe = sti_sdhci_probe, 142 .priv_auto_alloc_size = sizeof(struct sdhci_host), 143 .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat), 144 }; 145