1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <asm/io.h> 32 #include <asm/arch/mmc_host_def.h> 33 34 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); 35 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); 36 static struct mmc hsmmc_dev[2]; 37 unsigned char mmc_board_init(hsmmc_t *mmc_base) 38 { 39 #if defined(CONFIG_TWL4030_POWER) 40 twl4030_power_mmc_init(); 41 #endif 42 43 #if defined(CONFIG_OMAP34XX) 44 t2_t *t2_base = (t2_t *)T2_BASE; 45 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 46 47 writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | 48 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 49 &t2_base->pbias_lite); 50 51 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 52 &t2_base->devconf0); 53 54 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 55 &t2_base->devconf1); 56 57 writel(readl(&prcm_base->fclken1_core) | 58 EN_MMC1 | EN_MMC2 | EN_MMC3, 59 &prcm_base->fclken1_core); 60 61 writel(readl(&prcm_base->iclken1_core) | 62 EN_MMC1 | EN_MMC2 | EN_MMC3, 63 &prcm_base->iclken1_core); 64 #endif 65 66 /* TODO add appropriate OMAP4 init - none currently necessary */ 67 68 return 0; 69 } 70 71 void mmc_init_stream(hsmmc_t *mmc_base) 72 { 73 74 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 75 76 writel(MMC_CMD0, &mmc_base->cmd); 77 while (!(readl(&mmc_base->stat) & CC_MASK)) 78 ; 79 writel(CC_MASK, &mmc_base->stat) 80 ; 81 writel(MMC_CMD0, &mmc_base->cmd) 82 ; 83 while (!(readl(&mmc_base->stat) & CC_MASK)) 84 ; 85 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 86 } 87 88 89 static int mmc_init_setup(struct mmc *mmc) 90 { 91 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 92 unsigned int reg_val; 93 unsigned int dsor; 94 95 mmc_board_init(mmc_base); 96 97 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 98 &mmc_base->sysconfig); 99 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) 100 ; 101 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 102 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) 103 ; 104 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 105 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 106 &mmc_base->capa); 107 108 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 109 110 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 111 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 112 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 113 114 dsor = 240; 115 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 116 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 117 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 118 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 119 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) 120 ; 121 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 122 123 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 124 125 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 126 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 127 &mmc_base->ie); 128 129 mmc_init_stream(mmc_base); 130 131 return 0; 132 } 133 134 135 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 136 struct mmc_data *data) 137 { 138 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 139 unsigned int flags, mmc_stat; 140 unsigned int retry = 0x100000; 141 142 143 while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) 144 ; 145 writel(0xFFFFFFFF, &mmc_base->stat); 146 while (readl(&mmc_base->stat)) 147 ; 148 /* 149 * CMDREG 150 * CMDIDX[13:8] : Command index 151 * DATAPRNT[5] : Data Present Select 152 * ENCMDIDX[4] : Command Index Check Enable 153 * ENCMDCRC[3] : Command CRC Check Enable 154 * RSPTYP[1:0] 155 * 00 = No Response 156 * 01 = Length 136 157 * 10 = Length 48 158 * 11 = Length 48 Check busy after response 159 */ 160 /* Delay added before checking the status of frq change 161 * retry not supported by mmc.c(core file) 162 */ 163 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 164 udelay(50000); /* wait 50 ms */ 165 166 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 167 flags = 0; 168 else if (cmd->resp_type & MMC_RSP_136) 169 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 170 else if (cmd->resp_type & MMC_RSP_BUSY) 171 flags = RSP_TYPE_LGHT48B; 172 else 173 flags = RSP_TYPE_LGHT48; 174 175 /* enable default flags */ 176 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 177 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 178 179 if (cmd->resp_type & MMC_RSP_CRC) 180 flags |= CCCE_CHECK; 181 if (cmd->resp_type & MMC_RSP_OPCODE) 182 flags |= CICE_CHECK; 183 184 if (data) { 185 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 186 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 187 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 188 data->blocksize = 512; 189 writel(data->blocksize | (data->blocks << 16), 190 &mmc_base->blk); 191 } else 192 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 193 194 if (data->flags & MMC_DATA_READ) 195 flags |= (DP_DATA | DDIR_READ); 196 else 197 flags |= (DP_DATA | DDIR_WRITE); 198 } 199 200 writel(cmd->cmdarg, &mmc_base->arg); 201 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 202 203 do { 204 mmc_stat = readl(&mmc_base->stat); 205 retry--; 206 } while ((mmc_stat == 0) && (retry > 0)); 207 208 if (retry == 0) { 209 printf("%s : timeout: No status update\n", __func__); 210 return TIMEOUT; 211 } 212 213 if ((mmc_stat & IE_CTO) != 0) 214 return TIMEOUT; 215 else if ((mmc_stat & ERRI_MASK) != 0) 216 return -1; 217 218 if (mmc_stat & CC_MASK) { 219 writel(CC_MASK, &mmc_base->stat); 220 if (cmd->resp_type & MMC_RSP_PRESENT) { 221 if (cmd->resp_type & MMC_RSP_136) { 222 /* response type 2 */ 223 cmd->response[3] = readl(&mmc_base->rsp10); 224 cmd->response[2] = readl(&mmc_base->rsp32); 225 cmd->response[1] = readl(&mmc_base->rsp54); 226 cmd->response[0] = readl(&mmc_base->rsp76); 227 } else 228 /* response types 1, 1b, 3, 4, 5, 6 */ 229 cmd->response[0] = readl(&mmc_base->rsp10); 230 } 231 } 232 233 if (data && (data->flags & MMC_DATA_READ)) { 234 mmc_read_data(mmc_base, data->dest, 235 data->blocksize * data->blocks); 236 } else if (data && (data->flags & MMC_DATA_WRITE)) { 237 mmc_write_data(mmc_base, data->src, 238 data->blocksize * data->blocks); 239 } 240 return 0; 241 } 242 243 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size) 244 { 245 unsigned int *output_buf = (unsigned int *)buf; 246 unsigned int mmc_stat; 247 unsigned int count; 248 249 /* 250 * Start Polled Read 251 */ 252 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 253 count /= 4; 254 255 while (size) { 256 do { 257 mmc_stat = readl(&mmc_base->stat); 258 } while (mmc_stat == 0); 259 260 if ((mmc_stat & ERRI_MASK) != 0) 261 return 1; 262 263 if (mmc_stat & BRR_MASK) { 264 unsigned int k; 265 266 writel(readl(&mmc_base->stat) | BRR_MASK, 267 &mmc_base->stat); 268 for (k = 0; k < count; k++) { 269 *output_buf = readl(&mmc_base->data); 270 output_buf++; 271 } 272 size -= (count*4); 273 } 274 275 if (mmc_stat & BWR_MASK) 276 writel(readl(&mmc_base->stat) | BWR_MASK, 277 &mmc_base->stat); 278 279 if (mmc_stat & TC_MASK) { 280 writel(readl(&mmc_base->stat) | TC_MASK, 281 &mmc_base->stat); 282 break; 283 } 284 } 285 return 0; 286 } 287 288 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size) 289 { 290 unsigned int *input_buf = (unsigned int *)buf; 291 unsigned int mmc_stat; 292 unsigned int count; 293 294 /* 295 * Start Polled Read 296 */ 297 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 298 count /= 4; 299 300 while (size) { 301 do { 302 mmc_stat = readl(&mmc_base->stat); 303 } while (mmc_stat == 0); 304 305 if ((mmc_stat & ERRI_MASK) != 0) 306 return 1; 307 308 if (mmc_stat & BWR_MASK) { 309 unsigned int k; 310 311 writel(readl(&mmc_base->stat) | BWR_MASK, 312 &mmc_base->stat); 313 for (k = 0; k < count; k++) { 314 writel(*input_buf, &mmc_base->data); 315 input_buf++; 316 } 317 size -= (count*4); 318 } 319 320 if (mmc_stat & BRR_MASK) 321 writel(readl(&mmc_base->stat) | BRR_MASK, 322 &mmc_base->stat); 323 324 if (mmc_stat & TC_MASK) { 325 writel(readl(&mmc_base->stat) | TC_MASK, 326 &mmc_base->stat); 327 break; 328 } 329 } 330 return 0; 331 } 332 333 static void mmc_set_ios(struct mmc *mmc) 334 { 335 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 336 unsigned int dsor = 0; 337 338 /* configue bus width */ 339 switch (mmc->bus_width) { 340 case 8: 341 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 342 &mmc_base->con); 343 break; 344 345 case 4: 346 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 347 &mmc_base->con); 348 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 349 &mmc_base->hctl); 350 break; 351 352 case 1: 353 default: 354 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 355 &mmc_base->con); 356 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 357 &mmc_base->hctl); 358 break; 359 } 360 361 /* configure clock with 96Mhz system clock. 362 */ 363 if (mmc->clock != 0) { 364 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 365 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 366 dsor++; 367 } 368 369 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 370 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 371 372 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 373 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 374 375 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) 376 ; 377 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 378 } 379 380 int omap_mmc_init(int dev_index) 381 { 382 struct mmc *mmc; 383 384 mmc = &hsmmc_dev[dev_index]; 385 386 sprintf(mmc->name, "OMAP SD/MMC"); 387 mmc->send_cmd = mmc_send_cmd; 388 mmc->set_ios = mmc_set_ios; 389 mmc->init = mmc_init_setup; 390 391 switch (dev_index) { 392 case 0: 393 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 394 break; 395 case 1: 396 mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE; 397 break; 398 case 2: 399 mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE; 400 break; 401 default: 402 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 403 return 1; 404 } 405 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 406 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; 407 408 mmc->f_min = 400000; 409 mmc->f_max = 52000000; 410 411 mmc_register(mmc); 412 413 return 0; 414 } 415