1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <asm/io.h> 32 #include <asm/arch/mmc_host_def.h> 33 34 /* If we fail after 1 second wait, something is really bad */ 35 #define MAX_RETRY_MS 1000 36 37 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); 38 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); 39 static struct mmc hsmmc_dev[2]; 40 unsigned char mmc_board_init(hsmmc_t *mmc_base) 41 { 42 #if defined(CONFIG_TWL4030_POWER) 43 twl4030_power_mmc_init(); 44 #endif 45 46 #if defined(CONFIG_OMAP34XX) 47 t2_t *t2_base = (t2_t *)T2_BASE; 48 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 49 50 writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | 51 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 52 &t2_base->pbias_lite); 53 54 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 55 &t2_base->devconf0); 56 57 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 58 &t2_base->devconf1); 59 60 writel(readl(&prcm_base->fclken1_core) | 61 EN_MMC1 | EN_MMC2 | EN_MMC3, 62 &prcm_base->fclken1_core); 63 64 writel(readl(&prcm_base->iclken1_core) | 65 EN_MMC1 | EN_MMC2 | EN_MMC3, 66 &prcm_base->iclken1_core); 67 #endif 68 69 /* TODO add appropriate OMAP4 init - none currently necessary */ 70 71 return 0; 72 } 73 74 void mmc_init_stream(hsmmc_t *mmc_base) 75 { 76 ulong start; 77 78 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 79 80 writel(MMC_CMD0, &mmc_base->cmd); 81 start = get_timer(0); 82 while (!(readl(&mmc_base->stat) & CC_MASK)) { 83 if (get_timer(0) - start > MAX_RETRY_MS) { 84 printf("%s: timedout waiting for cc!\n", __func__); 85 return; 86 } 87 } 88 writel(CC_MASK, &mmc_base->stat) 89 ; 90 writel(MMC_CMD0, &mmc_base->cmd) 91 ; 92 start = get_timer(0); 93 while (!(readl(&mmc_base->stat) & CC_MASK)) { 94 if (get_timer(0) - start > MAX_RETRY_MS) { 95 printf("%s: timedout waiting for cc2!\n", __func__); 96 return; 97 } 98 } 99 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 100 } 101 102 103 static int mmc_init_setup(struct mmc *mmc) 104 { 105 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 106 unsigned int reg_val; 107 unsigned int dsor; 108 ulong start; 109 110 mmc_board_init(mmc_base); 111 112 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 113 &mmc_base->sysconfig); 114 start = get_timer(0); 115 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 116 if (get_timer(0) - start > MAX_RETRY_MS) { 117 printf("%s: timedout waiting for cc2!\n", __func__); 118 return TIMEOUT; 119 } 120 } 121 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 122 start = get_timer(0); 123 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 124 if (get_timer(0) - start > MAX_RETRY_MS) { 125 printf("%s: timedout waiting for softresetall!\n", 126 __func__); 127 return TIMEOUT; 128 } 129 } 130 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 131 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 132 &mmc_base->capa); 133 134 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 135 136 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 137 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 138 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 139 140 dsor = 240; 141 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 142 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 143 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 144 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 145 start = get_timer(0); 146 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 147 if (get_timer(0) - start > MAX_RETRY_MS) { 148 printf("%s: timedout waiting for ics!\n", __func__); 149 return TIMEOUT; 150 } 151 } 152 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 153 154 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 155 156 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 157 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 158 &mmc_base->ie); 159 160 mmc_init_stream(mmc_base); 161 162 return 0; 163 } 164 165 166 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 167 struct mmc_data *data) 168 { 169 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 170 unsigned int flags, mmc_stat; 171 ulong start; 172 173 start = get_timer(0); 174 while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) { 175 if (get_timer(0) - start > MAX_RETRY_MS) { 176 printf("%s: timedout waiting for cmddis!\n", __func__); 177 return TIMEOUT; 178 } 179 } 180 writel(0xFFFFFFFF, &mmc_base->stat); 181 start = get_timer(0); 182 while (readl(&mmc_base->stat)) { 183 if (get_timer(0) - start > MAX_RETRY_MS) { 184 printf("%s: timedout waiting for stat!\n", __func__); 185 return TIMEOUT; 186 } 187 } 188 /* 189 * CMDREG 190 * CMDIDX[13:8] : Command index 191 * DATAPRNT[5] : Data Present Select 192 * ENCMDIDX[4] : Command Index Check Enable 193 * ENCMDCRC[3] : Command CRC Check Enable 194 * RSPTYP[1:0] 195 * 00 = No Response 196 * 01 = Length 136 197 * 10 = Length 48 198 * 11 = Length 48 Check busy after response 199 */ 200 /* Delay added before checking the status of frq change 201 * retry not supported by mmc.c(core file) 202 */ 203 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 204 udelay(50000); /* wait 50 ms */ 205 206 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 207 flags = 0; 208 else if (cmd->resp_type & MMC_RSP_136) 209 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 210 else if (cmd->resp_type & MMC_RSP_BUSY) 211 flags = RSP_TYPE_LGHT48B; 212 else 213 flags = RSP_TYPE_LGHT48; 214 215 /* enable default flags */ 216 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 217 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 218 219 if (cmd->resp_type & MMC_RSP_CRC) 220 flags |= CCCE_CHECK; 221 if (cmd->resp_type & MMC_RSP_OPCODE) 222 flags |= CICE_CHECK; 223 224 if (data) { 225 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 226 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 227 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 228 data->blocksize = 512; 229 writel(data->blocksize | (data->blocks << 16), 230 &mmc_base->blk); 231 } else 232 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 233 234 if (data->flags & MMC_DATA_READ) 235 flags |= (DP_DATA | DDIR_READ); 236 else 237 flags |= (DP_DATA | DDIR_WRITE); 238 } 239 240 writel(cmd->cmdarg, &mmc_base->arg); 241 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 242 243 start = get_timer(0); 244 do { 245 mmc_stat = readl(&mmc_base->stat); 246 if (get_timer(0) - start > MAX_RETRY_MS) { 247 printf("%s : timeout: No status update\n", __func__); 248 return TIMEOUT; 249 } 250 } while (!mmc_stat); 251 252 if ((mmc_stat & IE_CTO) != 0) 253 return TIMEOUT; 254 else if ((mmc_stat & ERRI_MASK) != 0) 255 return -1; 256 257 if (mmc_stat & CC_MASK) { 258 writel(CC_MASK, &mmc_base->stat); 259 if (cmd->resp_type & MMC_RSP_PRESENT) { 260 if (cmd->resp_type & MMC_RSP_136) { 261 /* response type 2 */ 262 cmd->response[3] = readl(&mmc_base->rsp10); 263 cmd->response[2] = readl(&mmc_base->rsp32); 264 cmd->response[1] = readl(&mmc_base->rsp54); 265 cmd->response[0] = readl(&mmc_base->rsp76); 266 } else 267 /* response types 1, 1b, 3, 4, 5, 6 */ 268 cmd->response[0] = readl(&mmc_base->rsp10); 269 } 270 } 271 272 if (data && (data->flags & MMC_DATA_READ)) { 273 mmc_read_data(mmc_base, data->dest, 274 data->blocksize * data->blocks); 275 } else if (data && (data->flags & MMC_DATA_WRITE)) { 276 mmc_write_data(mmc_base, data->src, 277 data->blocksize * data->blocks); 278 } 279 return 0; 280 } 281 282 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size) 283 { 284 unsigned int *output_buf = (unsigned int *)buf; 285 unsigned int mmc_stat; 286 unsigned int count; 287 288 /* 289 * Start Polled Read 290 */ 291 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 292 count /= 4; 293 294 while (size) { 295 ulong start = get_timer(0); 296 do { 297 mmc_stat = readl(&mmc_base->stat); 298 if (get_timer(0) - start > MAX_RETRY_MS) { 299 printf("%s: timedout waiting for status!\n", 300 __func__); 301 return TIMEOUT; 302 } 303 } while (mmc_stat == 0); 304 305 if ((mmc_stat & ERRI_MASK) != 0) 306 return 1; 307 308 if (mmc_stat & BRR_MASK) { 309 unsigned int k; 310 311 writel(readl(&mmc_base->stat) | BRR_MASK, 312 &mmc_base->stat); 313 for (k = 0; k < count; k++) { 314 *output_buf = readl(&mmc_base->data); 315 output_buf++; 316 } 317 size -= (count*4); 318 } 319 320 if (mmc_stat & BWR_MASK) 321 writel(readl(&mmc_base->stat) | BWR_MASK, 322 &mmc_base->stat); 323 324 if (mmc_stat & TC_MASK) { 325 writel(readl(&mmc_base->stat) | TC_MASK, 326 &mmc_base->stat); 327 break; 328 } 329 } 330 return 0; 331 } 332 333 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size) 334 { 335 unsigned int *input_buf = (unsigned int *)buf; 336 unsigned int mmc_stat; 337 unsigned int count; 338 339 /* 340 * Start Polled Read 341 */ 342 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 343 count /= 4; 344 345 while (size) { 346 ulong start = get_timer(0); 347 do { 348 mmc_stat = readl(&mmc_base->stat); 349 if (get_timer(0) - start > MAX_RETRY_MS) { 350 printf("%s: timedout waiting for status!\n", 351 __func__); 352 return TIMEOUT; 353 } 354 } while (mmc_stat == 0); 355 356 if ((mmc_stat & ERRI_MASK) != 0) 357 return 1; 358 359 if (mmc_stat & BWR_MASK) { 360 unsigned int k; 361 362 writel(readl(&mmc_base->stat) | BWR_MASK, 363 &mmc_base->stat); 364 for (k = 0; k < count; k++) { 365 writel(*input_buf, &mmc_base->data); 366 input_buf++; 367 } 368 size -= (count*4); 369 } 370 371 if (mmc_stat & BRR_MASK) 372 writel(readl(&mmc_base->stat) | BRR_MASK, 373 &mmc_base->stat); 374 375 if (mmc_stat & TC_MASK) { 376 writel(readl(&mmc_base->stat) | TC_MASK, 377 &mmc_base->stat); 378 break; 379 } 380 } 381 return 0; 382 } 383 384 static void mmc_set_ios(struct mmc *mmc) 385 { 386 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 387 unsigned int dsor = 0; 388 ulong start; 389 390 /* configue bus width */ 391 switch (mmc->bus_width) { 392 case 8: 393 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 394 &mmc_base->con); 395 break; 396 397 case 4: 398 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 399 &mmc_base->con); 400 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 401 &mmc_base->hctl); 402 break; 403 404 case 1: 405 default: 406 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 407 &mmc_base->con); 408 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 409 &mmc_base->hctl); 410 break; 411 } 412 413 /* configure clock with 96Mhz system clock. 414 */ 415 if (mmc->clock != 0) { 416 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 417 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 418 dsor++; 419 } 420 421 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 422 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 423 424 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 425 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 426 427 start = get_timer(0); 428 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 429 if (get_timer(0) - start > MAX_RETRY_MS) { 430 printf("%s: timedout waiting for ics!\n", __func__); 431 return; 432 } 433 } 434 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 435 } 436 437 int omap_mmc_init(int dev_index) 438 { 439 struct mmc *mmc; 440 441 mmc = &hsmmc_dev[dev_index]; 442 443 sprintf(mmc->name, "OMAP SD/MMC"); 444 mmc->send_cmd = mmc_send_cmd; 445 mmc->set_ios = mmc_set_ios; 446 mmc->init = mmc_init_setup; 447 448 switch (dev_index) { 449 case 0: 450 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 451 break; 452 case 1: 453 mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE; 454 break; 455 case 2: 456 mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE; 457 break; 458 default: 459 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 460 return 1; 461 } 462 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 463 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; 464 465 mmc->f_min = 400000; 466 mmc->f_max = 52000000; 467 468 mmc_register(mmc); 469 470 return 0; 471 } 472