1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 27 IRQSTATEN_CINT | \ 28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 31 IRQSTATEN_DINT) 32 33 struct fsl_esdhc { 34 uint dsaddr; /* SDMA system address register */ 35 uint blkattr; /* Block attributes register */ 36 uint cmdarg; /* Command argument register */ 37 uint xfertyp; /* Transfer type register */ 38 uint cmdrsp0; /* Command response 0 register */ 39 uint cmdrsp1; /* Command response 1 register */ 40 uint cmdrsp2; /* Command response 2 register */ 41 uint cmdrsp3; /* Command response 3 register */ 42 uint datport; /* Buffer data port register */ 43 uint prsstat; /* Present state register */ 44 uint proctl; /* Protocol control register */ 45 uint sysctl; /* System Control Register */ 46 uint irqstat; /* Interrupt status register */ 47 uint irqstaten; /* Interrupt status enable register */ 48 uint irqsigen; /* Interrupt signal enable register */ 49 uint autoc12err; /* Auto CMD error status register */ 50 uint hostcapblt; /* Host controller capabilities register */ 51 uint wml; /* Watermark level register */ 52 uint mixctrl; /* For USDHC */ 53 char reserved1[4]; /* reserved */ 54 uint fevt; /* Force event register */ 55 uint admaes; /* ADMA error status register */ 56 uint adsaddr; /* ADMA system address register */ 57 char reserved2[160]; /* reserved */ 58 uint hostver; /* Host controller version register */ 59 char reserved3[4]; /* reserved */ 60 uint dmaerraddr; /* DMA error address register */ 61 char reserved4[4]; /* reserved */ 62 uint dmaerrattr; /* DMA error attribute register */ 63 char reserved5[4]; /* reserved */ 64 uint hostcapblt2; /* Host controller capabilities register 2 */ 65 char reserved6[8]; /* reserved */ 66 uint tcr; /* Tuning control register */ 67 char reserved7[28]; /* reserved */ 68 uint sddirctl; /* SD direction control register */ 69 char reserved8[712]; /* reserved */ 70 uint scr; /* eSDHC control register */ 71 }; 72 73 /* Return the XFERTYP flags for a given command and data packet */ 74 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 75 { 76 uint xfertyp = 0; 77 78 if (data) { 79 xfertyp |= XFERTYP_DPSEL; 80 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 81 xfertyp |= XFERTYP_DMAEN; 82 #endif 83 if (data->blocks > 1) { 84 xfertyp |= XFERTYP_MSBSEL; 85 xfertyp |= XFERTYP_BCEN; 86 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 87 xfertyp |= XFERTYP_AC12EN; 88 #endif 89 } 90 91 if (data->flags & MMC_DATA_READ) 92 xfertyp |= XFERTYP_DTDSEL; 93 } 94 95 if (cmd->resp_type & MMC_RSP_CRC) 96 xfertyp |= XFERTYP_CCCEN; 97 if (cmd->resp_type & MMC_RSP_OPCODE) 98 xfertyp |= XFERTYP_CICEN; 99 if (cmd->resp_type & MMC_RSP_136) 100 xfertyp |= XFERTYP_RSPTYP_136; 101 else if (cmd->resp_type & MMC_RSP_BUSY) 102 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 103 else if (cmd->resp_type & MMC_RSP_PRESENT) 104 xfertyp |= XFERTYP_RSPTYP_48; 105 106 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA) 107 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 108 xfertyp |= XFERTYP_CMDTYP_ABORT; 109 #endif 110 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 111 } 112 113 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 114 /* 115 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 116 */ 117 static void 118 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 119 { 120 struct fsl_esdhc_cfg *cfg = mmc->priv; 121 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 122 uint blocks; 123 char *buffer; 124 uint databuf; 125 uint size; 126 uint irqstat; 127 uint timeout; 128 129 if (data->flags & MMC_DATA_READ) { 130 blocks = data->blocks; 131 buffer = data->dest; 132 while (blocks) { 133 timeout = PIO_TIMEOUT; 134 size = data->blocksize; 135 irqstat = esdhc_read32(®s->irqstat); 136 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 137 && --timeout); 138 if (timeout <= 0) { 139 printf("\nData Read Failed in PIO Mode."); 140 return; 141 } 142 while (size && (!(irqstat & IRQSTAT_TC))) { 143 udelay(100); /* Wait before last byte transfer complete */ 144 irqstat = esdhc_read32(®s->irqstat); 145 databuf = in_le32(®s->datport); 146 *((uint *)buffer) = databuf; 147 buffer += 4; 148 size -= 4; 149 } 150 blocks--; 151 } 152 } else { 153 blocks = data->blocks; 154 buffer = (char *)data->src; 155 while (blocks) { 156 timeout = PIO_TIMEOUT; 157 size = data->blocksize; 158 irqstat = esdhc_read32(®s->irqstat); 159 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 160 && --timeout); 161 if (timeout <= 0) { 162 printf("\nData Write Failed in PIO Mode."); 163 return; 164 } 165 while (size && (!(irqstat & IRQSTAT_TC))) { 166 udelay(100); /* Wait before last byte transfer complete */ 167 databuf = *((uint *)buffer); 168 buffer += 4; 169 size -= 4; 170 irqstat = esdhc_read32(®s->irqstat); 171 out_le32(®s->datport, databuf); 172 } 173 blocks--; 174 } 175 } 176 } 177 #endif 178 179 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 180 { 181 int timeout; 182 struct fsl_esdhc_cfg *cfg = mmc->priv; 183 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 184 185 uint wml_value; 186 187 wml_value = data->blocksize/4; 188 189 if (data->flags & MMC_DATA_READ) { 190 if (wml_value > WML_RD_WML_MAX) 191 wml_value = WML_RD_WML_MAX_VAL; 192 193 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 194 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 195 esdhc_write32(®s->dsaddr, (u32)data->dest); 196 #endif 197 } else { 198 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 199 flush_dcache_range((ulong)data->src, 200 (ulong)data->src+data->blocks 201 *data->blocksize); 202 #endif 203 if (wml_value > WML_WR_WML_MAX) 204 wml_value = WML_WR_WML_MAX_VAL; 205 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 206 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 207 return TIMEOUT; 208 } 209 210 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 211 wml_value << 16); 212 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 213 esdhc_write32(®s->dsaddr, (u32)data->src); 214 #endif 215 } 216 217 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 218 219 /* Calculate the timeout period for data transactions */ 220 /* 221 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 222 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 223 * So, Number of SD Clock cycles for 0.25sec should be minimum 224 * (SD Clock/sec * 0.25 sec) SD Clock cycles 225 * = (mmc->clock * 1/4) SD Clock cycles 226 * As 1) >= 2) 227 * => (2^(timeout+13)) >= mmc->clock * 1/4 228 * Taking log2 both the sides 229 * => timeout + 13 >= log2(mmc->clock/4) 230 * Rounding up to next power of 2 231 * => timeout + 13 = log2(mmc->clock/4) + 1 232 * => timeout + 13 = fls(mmc->clock/4) 233 */ 234 timeout = fls(mmc->clock/4); 235 timeout -= 13; 236 237 if (timeout > 14) 238 timeout = 14; 239 240 if (timeout < 0) 241 timeout = 0; 242 243 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 244 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 245 timeout++; 246 #endif 247 248 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 249 timeout = 0xE; 250 #endif 251 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 252 253 return 0; 254 } 255 256 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 257 static void check_and_invalidate_dcache_range 258 (struct mmc_cmd *cmd, 259 struct mmc_data *data) { 260 unsigned start = (unsigned)data->dest ; 261 unsigned size = roundup(ARCH_DMA_MINALIGN, 262 data->blocks*data->blocksize); 263 unsigned end = start+size ; 264 invalidate_dcache_range(start, end); 265 } 266 #endif 267 268 /* 269 * Sends a command out on the bus. Takes the mmc pointer, 270 * a command pointer, and an optional data pointer. 271 */ 272 static int 273 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 274 { 275 int err = 0; 276 uint xfertyp; 277 uint irqstat; 278 struct fsl_esdhc_cfg *cfg = mmc->priv; 279 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 280 281 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 282 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 283 return 0; 284 #endif 285 286 esdhc_write32(®s->irqstat, -1); 287 288 sync(); 289 290 /* Wait for the bus to be idle */ 291 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 292 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 293 ; 294 295 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 296 ; 297 298 /* Wait at least 8 SD clock cycles before the next command */ 299 /* 300 * Note: This is way more than 8 cycles, but 1ms seems to 301 * resolve timing issues with some cards 302 */ 303 udelay(1000); 304 305 /* Set up for a data transfer if we have one */ 306 if (data) { 307 err = esdhc_setup_data(mmc, data); 308 if(err) 309 return err; 310 } 311 312 /* Figure out the transfer arguments */ 313 xfertyp = esdhc_xfertyp(cmd, data); 314 315 /* Mask all irqs */ 316 esdhc_write32(®s->irqsigen, 0); 317 318 /* Send the command */ 319 esdhc_write32(®s->cmdarg, cmd->cmdarg); 320 #if defined(CONFIG_FSL_USDHC) 321 esdhc_write32(®s->mixctrl, 322 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 323 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 324 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 325 #else 326 esdhc_write32(®s->xfertyp, xfertyp); 327 #endif 328 329 /* Wait for the command to complete */ 330 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 331 ; 332 333 irqstat = esdhc_read32(®s->irqstat); 334 335 if (irqstat & CMD_ERR) { 336 err = COMM_ERR; 337 goto out; 338 } 339 340 if (irqstat & IRQSTAT_CTOE) { 341 err = TIMEOUT; 342 goto out; 343 } 344 345 /* Workaround for ESDHC errata ENGcm03648 */ 346 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 347 int timeout = 2500; 348 349 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 350 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 351 PRSSTAT_DAT0)) { 352 udelay(100); 353 timeout--; 354 } 355 356 if (timeout <= 0) { 357 printf("Timeout waiting for DAT0 to go high!\n"); 358 err = TIMEOUT; 359 goto out; 360 } 361 } 362 363 /* Copy the response to the response buffer */ 364 if (cmd->resp_type & MMC_RSP_136) { 365 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 366 367 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 368 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 369 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 370 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 371 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 372 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 373 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 374 cmd->response[3] = (cmdrsp0 << 8); 375 } else 376 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 377 378 /* Wait until all of the blocks are transferred */ 379 if (data) { 380 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 381 esdhc_pio_read_write(mmc, data); 382 #else 383 do { 384 irqstat = esdhc_read32(®s->irqstat); 385 386 if (irqstat & IRQSTAT_DTOE) { 387 err = TIMEOUT; 388 goto out; 389 } 390 391 if (irqstat & DATA_ERR) { 392 err = COMM_ERR; 393 goto out; 394 } 395 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 396 397 if (data->flags & MMC_DATA_READ) 398 check_and_invalidate_dcache_range(cmd, data); 399 #endif 400 } 401 402 out: 403 /* Reset CMD and DATA portions on error */ 404 if (err) { 405 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 406 SYSCTL_RSTC); 407 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 408 ; 409 410 if (data) { 411 esdhc_write32(®s->sysctl, 412 esdhc_read32(®s->sysctl) | 413 SYSCTL_RSTD); 414 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 415 ; 416 } 417 } 418 419 esdhc_write32(®s->irqstat, -1); 420 421 return err; 422 } 423 424 static void set_sysctl(struct mmc *mmc, uint clock) 425 { 426 int div, pre_div; 427 struct fsl_esdhc_cfg *cfg = mmc->priv; 428 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 429 int sdhc_clk = cfg->sdhc_clk; 430 uint clk; 431 432 if (clock < mmc->cfg->f_min) 433 clock = mmc->cfg->f_min; 434 435 if (sdhc_clk / 16 > clock) { 436 for (pre_div = 2; pre_div < 256; pre_div *= 2) 437 if ((sdhc_clk / pre_div) <= (clock * 16)) 438 break; 439 } else 440 pre_div = 2; 441 442 for (div = 1; div <= 16; div++) 443 if ((sdhc_clk / (div * pre_div)) <= clock) 444 break; 445 446 pre_div >>= mmc->ddr_mode ? 2 : 1; 447 div -= 1; 448 449 clk = (pre_div << 8) | (div << 4); 450 451 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 452 453 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 454 455 udelay(10000); 456 457 clk = SYSCTL_PEREN | SYSCTL_CKEN; 458 459 esdhc_setbits32(®s->sysctl, clk); 460 } 461 462 static void esdhc_set_ios(struct mmc *mmc) 463 { 464 struct fsl_esdhc_cfg *cfg = mmc->priv; 465 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 466 467 /* Set the clock speed */ 468 set_sysctl(mmc, mmc->clock); 469 470 /* Set the bus width */ 471 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 472 473 if (mmc->bus_width == 4) 474 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 475 else if (mmc->bus_width == 8) 476 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 477 478 } 479 480 static int esdhc_init(struct mmc *mmc) 481 { 482 struct fsl_esdhc_cfg *cfg = mmc->priv; 483 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 484 int timeout = 1000; 485 486 /* Reset the entire host controller */ 487 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 488 489 /* Wait until the controller is available */ 490 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 491 udelay(1000); 492 493 #ifndef ARCH_MXC 494 /* Enable cache snooping */ 495 esdhc_write32(®s->scr, 0x00000040); 496 #endif 497 498 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 499 500 /* Set the initial clock speed */ 501 mmc_set_clock(mmc, 400000); 502 503 /* Disable the BRR and BWR bits in IRQSTAT */ 504 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 505 506 /* Put the PROCTL reg back to the default */ 507 esdhc_write32(®s->proctl, PROCTL_INIT); 508 509 /* Set timout to the maximum value */ 510 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 511 512 return 0; 513 } 514 515 static int esdhc_getcd(struct mmc *mmc) 516 { 517 struct fsl_esdhc_cfg *cfg = mmc->priv; 518 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 519 int timeout = 1000; 520 521 #ifdef CONFIG_ESDHC_DETECT_QUIRK 522 if (CONFIG_ESDHC_DETECT_QUIRK) 523 return 1; 524 #endif 525 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 526 udelay(1000); 527 528 return timeout > 0; 529 } 530 531 static void esdhc_reset(struct fsl_esdhc *regs) 532 { 533 unsigned long timeout = 100; /* wait max 100 ms */ 534 535 /* reset the controller */ 536 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 537 538 /* hardware clears the bit when it is done */ 539 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 540 udelay(1000); 541 if (!timeout) 542 printf("MMC/SD: Reset never completed.\n"); 543 } 544 545 static const struct mmc_ops esdhc_ops = { 546 .send_cmd = esdhc_send_cmd, 547 .set_ios = esdhc_set_ios, 548 .init = esdhc_init, 549 .getcd = esdhc_getcd, 550 }; 551 552 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 553 { 554 struct fsl_esdhc *regs; 555 struct mmc *mmc; 556 u32 caps, voltage_caps; 557 558 if (!cfg) 559 return -1; 560 561 regs = (struct fsl_esdhc *)cfg->esdhc_base; 562 563 /* First reset the eSDHC controller */ 564 esdhc_reset(regs); 565 566 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 567 | SYSCTL_IPGEN | SYSCTL_CKEN); 568 569 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 570 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 571 572 voltage_caps = 0; 573 caps = esdhc_read32(®s->hostcapblt); 574 575 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 576 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 577 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 578 #endif 579 580 /* T4240 host controller capabilities register should have VS33 bit */ 581 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 582 caps = caps | ESDHC_HOSTCAPBLT_VS33; 583 #endif 584 585 if (caps & ESDHC_HOSTCAPBLT_VS18) 586 voltage_caps |= MMC_VDD_165_195; 587 if (caps & ESDHC_HOSTCAPBLT_VS30) 588 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 589 if (caps & ESDHC_HOSTCAPBLT_VS33) 590 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 591 592 cfg->cfg.name = "FSL_SDHC"; 593 cfg->cfg.ops = &esdhc_ops; 594 #ifdef CONFIG_SYS_SD_VOLTAGE 595 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 596 #else 597 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 598 #endif 599 if ((cfg->cfg.voltages & voltage_caps) == 0) { 600 printf("voltage not supported by controller\n"); 601 return -1; 602 } 603 604 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 605 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 606 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; 607 #endif 608 609 if (cfg->max_bus_width > 0) { 610 if (cfg->max_bus_width < 8) 611 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 612 if (cfg->max_bus_width < 4) 613 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 614 } 615 616 if (caps & ESDHC_HOSTCAPBLT_HSS) 617 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 618 619 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 620 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 621 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 622 #endif 623 624 cfg->cfg.f_min = 400000; 625 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); 626 627 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 628 629 mmc = mmc_create(&cfg->cfg, cfg); 630 if (mmc == NULL) 631 return -1; 632 633 return 0; 634 } 635 636 int fsl_esdhc_mmc_init(bd_t *bis) 637 { 638 struct fsl_esdhc_cfg *cfg; 639 640 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 641 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 642 cfg->sdhc_clk = gd->arch.sdhc_clk; 643 return fsl_esdhc_initialize(bis, cfg); 644 } 645 646 #ifdef CONFIG_OF_LIBFDT 647 void fdt_fixup_esdhc(void *blob, bd_t *bd) 648 { 649 const char *compat = "fsl,esdhc"; 650 651 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 652 if (!hwconfig("esdhc")) { 653 do_fixup_by_compat(blob, compat, "status", "disabled", 654 8 + 1, 1); 655 return; 656 } 657 #endif 658 659 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 660 gd->arch.sdhc_clk, 1); 661 662 do_fixup_by_compat(blob, compat, "status", "okay", 663 4 + 1, 1); 664 } 665 #endif 666