1*7e86242bSMario Six /* SPDX-License-Identifier: GPL-2.0+ */ 2*7e86242bSMario Six /* 3*7e86242bSMario Six * (C) Copyright 2018 4*7e86242bSMario Six * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5*7e86242bSMario Six */ 6*7e86242bSMario Six 7*7e86242bSMario Six #ifndef __GDSYS_IOEP_H_ 8*7e86242bSMario Six #define __GDSYS_IOEP_H_ 9*7e86242bSMario Six 10*7e86242bSMario Six /** 11*7e86242bSMario Six * struct io_generic_packet - header structure for GDSYS IOEP packets 12*7e86242bSMario Six * @target_address: Target protocol address of the packet. 13*7e86242bSMario Six * @source_address: Source protocol address of the packet. 14*7e86242bSMario Six * @packet_type: Packet type. 15*7e86242bSMario Six * @bc: Block counter (filled in by FPGA). 16*7e86242bSMario Six * @packet_length: Length of the packet's payload bytes. 17*7e86242bSMario Six */ 18*7e86242bSMario Six struct io_generic_packet { 19*7e86242bSMario Six u16 target_address; 20*7e86242bSMario Six u16 source_address; 21*7e86242bSMario Six u8 packet_type; 22*7e86242bSMario Six u8 bc; 23*7e86242bSMario Six u16 packet_length; 24*7e86242bSMario Six } __attribute__((__packed__)); 25*7e86242bSMario Six 26*7e86242bSMario Six /** 27*7e86242bSMario Six * struct gdsys_ioep_regs - Registers of a IOEP device 28*7e86242bSMario Six * @transmit_data: Register that receives data to be sent 29*7e86242bSMario Six * @tx_control: TX control register 30*7e86242bSMario Six * @receive_data: Register filled with the received data 31*7e86242bSMario Six * @rx_tx_status: RX/TX status register 32*7e86242bSMario Six * @device_address: Register for setting/reading the device's address 33*7e86242bSMario Six * @target_address: Register for setting/reading the remote endpoint's address 34*7e86242bSMario Six * @int_enable: Interrupt/Interrupt enable register 35*7e86242bSMario Six */ 36*7e86242bSMario Six struct gdsys_ioep_regs { 37*7e86242bSMario Six u16 transmit_data; 38*7e86242bSMario Six u16 tx_control; 39*7e86242bSMario Six u16 receive_data; 40*7e86242bSMario Six u16 rx_tx_status; 41*7e86242bSMario Six u16 device_address; 42*7e86242bSMario Six u16 target_address; 43*7e86242bSMario Six u16 int_enable; 44*7e86242bSMario Six }; 45*7e86242bSMario Six 46*7e86242bSMario Six /** 47*7e86242bSMario Six * gdsys_ioep_set() - Convenience macro to write registers of a IOEP device 48*7e86242bSMario Six * @map: Register map to write the value in 49*7e86242bSMario Six * @member: Name of the member in the gdsys_ioep_regs structure to write 50*7e86242bSMario Six * @val: Value to write to the register 51*7e86242bSMario Six */ 52*7e86242bSMario Six #define gdsys_ioep_set(map, member, val) \ 53*7e86242bSMario Six regmap_set(map, struct gdsys_ioep_regs, member, val) 54*7e86242bSMario Six 55*7e86242bSMario Six /** 56*7e86242bSMario Six * gdsys_ioep_get() - Convenience macro to read registers of a IOEP device 57*7e86242bSMario Six * @map: Register map to read the value from 58*7e86242bSMario Six * @member: Name of the member in the gdsys_ioep_regs structure to read 59*7e86242bSMario Six * @valp: Pointer to buffer to read the register value into 60*7e86242bSMario Six */ 61*7e86242bSMario Six #define gdsys_ioep_get(map, member, valp) \ 62*7e86242bSMario Six regmap_get(map, struct gdsys_ioep_regs, member, valp) 63*7e86242bSMario Six 64*7e86242bSMario Six /** 65*7e86242bSMario Six * enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status 66*7e86242bSMario Six * register 67*7e86242bSMario Six * @STATE_TX_PACKET_BUILDING: The device is currently building a packet 68*7e86242bSMario Six * (and accepting data for it) 69*7e86242bSMario Six * @STATE_TX_TRANSMITTING: A packet is currenly being transmitted 70*7e86242bSMario Six * @STATE_TX_BUFFER_FULL: The TX buffer is full 71*7e86242bSMario Six * @STATE_TX_ERR: A TX error occurred 72*7e86242bSMario Six * @STATE_RECEIVE_TIMEOUT: A receive timeout occurred 73*7e86242bSMario Six * @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet 74*7e86242bSMario Six * occurred 75*7e86242bSMario Six * @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet 76*7e86242bSMario Six * occurred 77*7e86242bSMario Six * @STATE_RX_DIST_ERR: A error occurred in the distribution block 78*7e86242bSMario Six * @STATE_RX_LENGTH_ERR: A length invalid error occurred 79*7e86242bSMario Six * @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two 80*7e86242bSMario Six * non-increasing frame count numbers 81*7e86242bSMario Six * encountered) 82*7e86242bSMario Six * @STATE_RX_FCS_ERR: A CRC error occurred 83*7e86242bSMario Six * @STATE_RX_PACKET_DROPPED: A RX packet has been dropped 84*7e86242bSMario Six * @STATE_RX_DATA_LAST: The data to be read is the final data of the 85*7e86242bSMario Six * current packet 86*7e86242bSMario Six * @STATE_RX_DATA_FIRST: The data to be read is the first data of the 87*7e86242bSMario Six * current packet 88*7e86242bSMario Six * @STATE_RX_DATA_AVAILABLE: RX data is available to be read 89*7e86242bSMario Six */ 90*7e86242bSMario Six enum rx_tx_status_values { 91*7e86242bSMario Six STATE_TX_PACKET_BUILDING = BIT(0), 92*7e86242bSMario Six STATE_TX_TRANSMITTING = BIT(1), 93*7e86242bSMario Six STATE_TX_BUFFER_FULL = BIT(2), 94*7e86242bSMario Six STATE_TX_ERR = BIT(3), 95*7e86242bSMario Six STATE_RECEIVE_TIMEOUT = BIT(4), 96*7e86242bSMario Six STATE_PROC_RX_STORE_TIMEOUT = BIT(5), 97*7e86242bSMario Six STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6), 98*7e86242bSMario Six STATE_RX_DIST_ERR = BIT(7), 99*7e86242bSMario Six STATE_RX_LENGTH_ERR = BIT(8), 100*7e86242bSMario Six STATE_RX_FRAME_CTR_ERR = BIT(9), 101*7e86242bSMario Six STATE_RX_FCS_ERR = BIT(10), 102*7e86242bSMario Six STATE_RX_PACKET_DROPPED = BIT(11), 103*7e86242bSMario Six STATE_RX_DATA_LAST = BIT(12), 104*7e86242bSMario Six STATE_RX_DATA_FIRST = BIT(13), 105*7e86242bSMario Six STATE_RX_DATA_AVAILABLE = BIT(15), 106*7e86242bSMario Six }; 107*7e86242bSMario Six 108*7e86242bSMario Six /** 109*7e86242bSMario Six * enum tx_control_values - Enum to describe the fields of the tx_control 110*7e86242bSMario Six * register 111*7e86242bSMario Six * @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor 112*7e86242bSMario Six * @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data) 113*7e86242bSMario Six */ 114*7e86242bSMario Six enum tx_control_values { 115*7e86242bSMario Six CTRL_PROC_RECEIVE_ENABLE = BIT(12), 116*7e86242bSMario Six CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), 117*7e86242bSMario Six }; 118*7e86242bSMario Six 119*7e86242bSMario Six /** 120*7e86242bSMario Six * enum int_enable_values - Enum to describe the fields of the int_enable 121*7e86242bSMario Six * register 122*7e86242bSMario Six * @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet 123*7e86242bSMario Six * data can be transmitted to the 124*7e86242bSMario Six * device) 125*7e86242bSMario Six * @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted 126*7e86242bSMario Six * @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received 127*7e86242bSMario Six * @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be 128*7e86242bSMario Six * read 129*7e86242bSMario Six */ 130*7e86242bSMario Six enum int_enable_values { 131*7e86242bSMario Six IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), 132*7e86242bSMario Six IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), 133*7e86242bSMario Six IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7), 134*7e86242bSMario Six IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), 135*7e86242bSMario Six }; 136*7e86242bSMario Six 137*7e86242bSMario Six #endif /* __GDSYS_IOEP_H_ */ 138