1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* This code should work for both the S3C2400 and the S3C2410 9 * as they seem to have the same I2C controller inside. 10 * The different address mapping is handled by the s3c24xx.h files below. 11 */ 12 #include <common.h> 13 #include <errno.h> 14 #include <dm.h> 15 #include <fdtdec.h> 16 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 17 #include <asm/arch/clk.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/pinmux.h> 20 #else 21 #include <asm/arch/s3c24x0_cpu.h> 22 #endif 23 #include <asm/io.h> 24 #include <i2c.h> 25 #include "s3c24x0_i2c.h" 26 27 #define I2C_WRITE 0 28 #define I2C_READ 1 29 30 #define I2C_OK 0 31 #define I2C_NOK 1 32 #define I2C_NACK 2 33 #define I2C_NOK_LA 3 /* Lost arbitration */ 34 #define I2C_NOK_TOUT 4 /* time out */ 35 36 /* HSI2C specific register description */ 37 38 /* I2C_CTL Register bits */ 39 #define HSI2C_FUNC_MODE_I2C (1u << 0) 40 #define HSI2C_MASTER (1u << 3) 41 #define HSI2C_RXCHON (1u << 6) /* Write/Send */ 42 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 43 #define HSI2C_SW_RST (1u << 31) 44 45 /* I2C_FIFO_CTL Register bits */ 46 #define HSI2C_RXFIFO_EN (1u << 0) 47 #define HSI2C_TXFIFO_EN (1u << 1) 48 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 49 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 50 51 /* I2C_TRAILING_CTL Register bits */ 52 #define HSI2C_TRAILING_COUNT (0xff) 53 54 /* I2C_INT_EN Register bits */ 55 #define HSI2C_TX_UNDERRUN_EN (1u << 2) 56 #define HSI2C_TX_OVERRUN_EN (1u << 3) 57 #define HSI2C_RX_UNDERRUN_EN (1u << 4) 58 #define HSI2C_RX_OVERRUN_EN (1u << 5) 59 #define HSI2C_INT_TRAILING_EN (1u << 6) 60 #define HSI2C_INT_I2C_EN (1u << 9) 61 62 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 63 HSI2C_TX_OVERRUN_EN |\ 64 HSI2C_RX_UNDERRUN_EN |\ 65 HSI2C_RX_OVERRUN_EN |\ 66 HSI2C_INT_TRAILING_EN) 67 68 /* I2C_CONF Register bits */ 69 #define HSI2C_AUTO_MODE (1u << 31) 70 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 71 #define HSI2C_HS_MODE (1u << 29) 72 73 /* I2C_AUTO_CONF Register bits */ 74 #define HSI2C_READ_WRITE (1u << 16) 75 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 76 #define HSI2C_MASTER_RUN (1u << 31) 77 78 /* I2C_TIMEOUT Register bits */ 79 #define HSI2C_TIMEOUT_EN (1u << 31) 80 81 /* I2C_TRANS_STATUS register bits */ 82 #define HSI2C_MASTER_BUSY (1u << 17) 83 #define HSI2C_SLAVE_BUSY (1u << 16) 84 #define HSI2C_TIMEOUT_AUTO (1u << 4) 85 #define HSI2C_NO_DEV (1u << 3) 86 #define HSI2C_NO_DEV_ACK (1u << 2) 87 #define HSI2C_TRANS_ABORT (1u << 1) 88 #define HSI2C_TRANS_SUCCESS (1u << 0) 89 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 90 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 91 HSI2C_TRANS_ABORT) 92 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 93 94 95 /* I2C_FIFO_STAT Register bits */ 96 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 97 #define HSI2C_RX_FIFO_FULL (1u << 23) 98 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 99 #define HSI2C_TX_FIFO_FULL (1u << 7) 100 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 101 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 102 103 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 104 105 /* S3C I2C Controller bits */ 106 #define I2CSTAT_BSY 0x20 /* Busy bit */ 107 #define I2CSTAT_NACK 0x01 /* Nack bit */ 108 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 109 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 110 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 111 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 112 #define I2C_START_STOP 0x20 /* START / STOP */ 113 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 114 115 #define I2C_TIMEOUT_MS 10 /* 10 ms */ 116 117 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ 118 119 DECLARE_GLOBAL_DATA_PTR; 120 121 enum exynos_i2c_type { 122 EXYNOS_I2C_STD, 123 EXYNOS_I2C_HS, 124 }; 125 126 /* 127 * Wait til the byte transfer is completed. 128 * 129 * @param i2c- pointer to the appropriate i2c register bank. 130 * @return I2C_OK, if transmission was ACKED 131 * I2C_NACK, if transmission was NACKED 132 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS 133 */ 134 135 static int WaitForXfer(struct s3c24x0_i2c *i2c) 136 { 137 ulong start_time = get_timer(0); 138 139 do { 140 if (readl(&i2c->iiccon) & I2CCON_IRPND) 141 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ? 142 I2C_NACK : I2C_OK; 143 } while (get_timer(start_time) < I2C_TIMEOUT_MS); 144 145 return I2C_NOK_TOUT; 146 } 147 148 /* 149 * Wait for transfer completion. 150 * 151 * This function reads the interrupt status register waiting for the INT_I2C 152 * bit to be set, which indicates copletion of a transaction. 153 * 154 * @param i2c: pointer to the appropriate register bank 155 * 156 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 157 * the status bits do not get set in time, or an approrpiate error 158 * value in case of transfer errors. 159 */ 160 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 161 { 162 int i = HSI2C_TIMEOUT_US; 163 164 while (i-- > 0) { 165 u32 int_status = readl(&i2c->usi_int_stat); 166 167 if (int_status & HSI2C_INT_I2C_EN) { 168 u32 trans_status = readl(&i2c->usi_trans_status); 169 170 /* Deassert pending interrupt. */ 171 writel(int_status, &i2c->usi_int_stat); 172 173 if (trans_status & HSI2C_NO_DEV_ACK) { 174 debug("%s: no ACK from device\n", __func__); 175 return I2C_NACK; 176 } 177 if (trans_status & HSI2C_NO_DEV) { 178 debug("%s: no device\n", __func__); 179 return I2C_NOK; 180 } 181 if (trans_status & HSI2C_TRANS_ABORT) { 182 debug("%s: arbitration lost\n", __func__); 183 return I2C_NOK_LA; 184 } 185 if (trans_status & HSI2C_TIMEOUT_AUTO) { 186 debug("%s: device timed out\n", __func__); 187 return I2C_NOK_TOUT; 188 } 189 return I2C_OK; 190 } 191 udelay(1); 192 } 193 debug("%s: transaction timeout!\n", __func__); 194 return I2C_NOK_TOUT; 195 } 196 197 static void read_write_byte(struct s3c24x0_i2c *i2c) 198 { 199 clrbits_le32(&i2c->iiccon, I2CCON_IRPND); 200 } 201 202 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) 203 { 204 ulong freq, pres = 16, div; 205 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 206 freq = get_i2c_clk(); 207 #else 208 freq = get_PCLK(); 209 #endif 210 /* calculate prescaler and divisor values */ 211 if ((freq / pres / (16 + 1)) > speed) 212 /* set prescaler to 512 */ 213 pres = 512; 214 215 div = 0; 216 while ((freq / pres / (div + 1)) > speed) 217 div++; 218 219 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ 220 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); 221 222 /* init to SLAVE REVEIVE and set slaveaddr */ 223 writel(0, &i2c->iicstat); 224 writel(slaveadd, &i2c->iicadd); 225 /* program Master Transmit (and implicit STOP) */ 226 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 227 } 228 229 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 230 { 231 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 232 ulong clkin; 233 unsigned int op_clk = i2c_bus->clock_frequency; 234 unsigned int i = 0, utemp0 = 0, utemp1 = 0; 235 unsigned int t_ftl_cycle; 236 237 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 238 clkin = get_i2c_clk(); 239 #else 240 clkin = get_PCLK(); 241 #endif 242 /* FPCLK / FI2C = 243 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 244 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 245 * uTemp1 = (TSCLK_L + TSCLK_H + 2) 246 * uTemp2 = TSCLK_L + TSCLK_H 247 */ 248 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 249 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 250 251 /* CLK_DIV max is 256 */ 252 for (i = 0; i < 256; i++) { 253 utemp1 = utemp0 / (i + 1); 254 if ((utemp1 < 512) && (utemp1 > 4)) { 255 i2c_bus->clk_cycle = utemp1 - 2; 256 i2c_bus->clk_div = i; 257 return 0; 258 } 259 } 260 return -EINVAL; 261 } 262 263 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 264 { 265 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 266 unsigned int t_sr_release; 267 unsigned int n_clkdiv; 268 unsigned int t_start_su, t_start_hd; 269 unsigned int t_stop_su; 270 unsigned int t_data_su, t_data_hd; 271 unsigned int t_scl_l, t_scl_h; 272 u32 i2c_timing_s1; 273 u32 i2c_timing_s2; 274 u32 i2c_timing_s3; 275 u32 i2c_timing_sla; 276 277 n_clkdiv = i2c_bus->clk_div; 278 t_scl_l = i2c_bus->clk_cycle / 2; 279 t_scl_h = i2c_bus->clk_cycle / 2; 280 t_start_su = t_scl_l; 281 t_start_hd = t_scl_l; 282 t_stop_su = t_scl_l; 283 t_data_su = t_scl_l / 2; 284 t_data_hd = t_scl_l / 2; 285 t_sr_release = i2c_bus->clk_cycle; 286 287 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 288 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 289 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 290 i2c_timing_sla = t_data_hd << 0; 291 292 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 293 294 /* Clear to enable Timeout */ 295 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 296 297 /* set AUTO mode */ 298 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 299 300 /* Enable completion conditions' reporting. */ 301 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 302 303 /* Enable FIFOs */ 304 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 305 306 /* Currently operating in Fast speed mode. */ 307 writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 308 writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 309 writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 310 writel(i2c_timing_sla, &hsregs->usi_timing_sla); 311 } 312 313 /* SW reset for the high speed bus */ 314 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 315 { 316 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 317 u32 i2c_ctl; 318 319 /* Set and clear the bit for reset */ 320 i2c_ctl = readl(&i2c->usi_ctl); 321 i2c_ctl |= HSI2C_SW_RST; 322 writel(i2c_ctl, &i2c->usi_ctl); 323 324 i2c_ctl = readl(&i2c->usi_ctl); 325 i2c_ctl &= ~HSI2C_SW_RST; 326 writel(i2c_ctl, &i2c->usi_ctl); 327 328 /* Initialize the configure registers */ 329 hsi2c_ch_init(i2c_bus); 330 } 331 332 /* 333 * Poll the appropriate bit of the fifo status register until the interface is 334 * ready to process the next byte or timeout expires. 335 * 336 * In addition to the FIFO status register this function also polls the 337 * interrupt status register to be able to detect unexpected transaction 338 * completion. 339 * 340 * When FIFO is ready to process the next byte, this function returns I2C_OK. 341 * If in course of polling the INT_I2C assertion is detected, the function 342 * returns I2C_NOK. If timeout happens before any of the above conditions is 343 * met - the function returns I2C_NOK_TOUT; 344 345 * @param i2c: pointer to the appropriate i2c register bank. 346 * @param rx_transfer: set to True if the receive transaction is in progress. 347 * @return: as described above. 348 */ 349 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 350 { 351 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 352 int i = HSI2C_TIMEOUT_US; 353 354 while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 355 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 356 /* 357 * There is a chance that assertion of 358 * HSI2C_INT_I2C_EN and deassertion of 359 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 360 * give FIFO status priority and check it one more 361 * time before reporting interrupt. The interrupt will 362 * be reported next time this function is called. 363 */ 364 if (rx_transfer && 365 !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 366 break; 367 return I2C_NOK; 368 } 369 if (!i--) { 370 debug("%s: FIFO polling timeout!\n", __func__); 371 return I2C_NOK_TOUT; 372 } 373 udelay(1); 374 } 375 return I2C_OK; 376 } 377 378 /* 379 * Preapre hsi2c transaction, either read or write. 380 * 381 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 382 * the 5420 UM. 383 * 384 * @param i2c: pointer to the appropriate i2c register bank. 385 * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 386 * @param len: number of bytes expected to be sent or received 387 * @param rx_transfer: set to true for receive transactions 388 * @param: issue_stop: set to true if i2c stop condition should be generated 389 * after this transaction. 390 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 391 * I2C_OK otherwise. 392 */ 393 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 394 u8 chip, 395 u16 len, 396 bool rx_transfer, 397 bool issue_stop) 398 { 399 u32 conf; 400 401 conf = len | HSI2C_MASTER_RUN; 402 403 if (issue_stop) 404 conf |= HSI2C_STOP_AFTER_TRANS; 405 406 /* Clear to enable Timeout */ 407 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 408 409 /* Set slave address */ 410 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 411 412 if (rx_transfer) { 413 /* i2c master, read transaction */ 414 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 415 &i2c->usi_ctl); 416 417 /* read up to len bytes, stop after transaction is finished */ 418 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 419 } else { 420 /* i2c master, write transaction */ 421 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 422 &i2c->usi_ctl); 423 424 /* write up to len bytes, stop after transaction is finished */ 425 writel(conf, &i2c->usi_auto_conf); 426 } 427 428 /* Reset all pending interrupt status bits we care about, if any */ 429 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 430 431 return I2C_OK; 432 } 433 434 /* 435 * Wait while i2c bus is settling down (mostly stop gets completed). 436 */ 437 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 438 { 439 int i = HSI2C_TIMEOUT_US; 440 441 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 442 if (!i--) { 443 debug("%s: bus busy\n", __func__); 444 return I2C_NOK_TOUT; 445 } 446 udelay(1); 447 } 448 return I2C_OK; 449 } 450 451 static int hsi2c_write(struct exynos5_hsi2c *i2c, 452 unsigned char chip, 453 unsigned char addr[], 454 unsigned char alen, 455 unsigned char data[], 456 unsigned short len, 457 bool issue_stop) 458 { 459 int i, rv = 0; 460 461 if (!(len + alen)) { 462 /* Writes of zero length not supported in auto mode. */ 463 debug("%s: zero length writes not supported\n", __func__); 464 return I2C_NOK; 465 } 466 467 rv = hsi2c_prepare_transaction 468 (i2c, chip, len + alen, false, issue_stop); 469 if (rv != I2C_OK) 470 return rv; 471 472 /* Move address, if any, and the data, if any, into the FIFO. */ 473 for (i = 0; i < alen; i++) { 474 rv = hsi2c_poll_fifo(i2c, false); 475 if (rv != I2C_OK) { 476 debug("%s: address write failed\n", __func__); 477 goto write_error; 478 } 479 writel(addr[i], &i2c->usi_txdata); 480 } 481 482 for (i = 0; i < len; i++) { 483 rv = hsi2c_poll_fifo(i2c, false); 484 if (rv != I2C_OK) { 485 debug("%s: data write failed\n", __func__); 486 goto write_error; 487 } 488 writel(data[i], &i2c->usi_txdata); 489 } 490 491 rv = hsi2c_wait_for_trx(i2c); 492 493 write_error: 494 if (issue_stop) { 495 int tmp_ret = hsi2c_wait_while_busy(i2c); 496 if (rv == I2C_OK) 497 rv = tmp_ret; 498 } 499 500 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 501 return rv; 502 } 503 504 static int hsi2c_read(struct exynos5_hsi2c *i2c, 505 unsigned char chip, 506 unsigned char addr[], 507 unsigned char alen, 508 unsigned char data[], 509 unsigned short len) 510 { 511 int i, rv, tmp_ret; 512 bool drop_data = false; 513 514 if (!len) { 515 /* Reads of zero length not supported in auto mode. */ 516 debug("%s: zero length read adjusted\n", __func__); 517 drop_data = true; 518 len = 1; 519 } 520 521 if (alen) { 522 /* Internal register adress needs to be written first. */ 523 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 524 if (rv != I2C_OK) 525 return rv; 526 } 527 528 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 529 530 if (rv != I2C_OK) 531 return rv; 532 533 for (i = 0; i < len; i++) { 534 rv = hsi2c_poll_fifo(i2c, true); 535 if (rv != I2C_OK) 536 goto read_err; 537 if (drop_data) 538 continue; 539 data[i] = readl(&i2c->usi_rxdata); 540 } 541 542 rv = hsi2c_wait_for_trx(i2c); 543 544 read_err: 545 tmp_ret = hsi2c_wait_while_busy(i2c); 546 if (rv == I2C_OK) 547 rv = tmp_ret; 548 549 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 550 return rv; 551 } 552 553 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 554 { 555 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 556 557 i2c_bus->clock_frequency = speed; 558 559 if (i2c_bus->is_highspeed) { 560 if (hsi2c_get_clk_details(i2c_bus)) 561 return -EFAULT; 562 hsi2c_ch_init(i2c_bus); 563 } else { 564 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, 565 CONFIG_SYS_I2C_S3C24X0_SLAVE); 566 } 567 568 return 0; 569 } 570 571 /* 572 * cmd_type is 0 for write, 1 for read. 573 * 574 * addr_len can take any value from 0-255, it is only limited 575 * by the char, we could make it larger if needed. If it is 576 * 0 we skip the address write cycle. 577 */ 578 static int i2c_transfer(struct s3c24x0_i2c *i2c, 579 unsigned char cmd_type, 580 unsigned char chip, 581 unsigned char addr[], 582 unsigned char addr_len, 583 unsigned char data[], 584 unsigned short data_len) 585 { 586 int i = 0, result; 587 ulong start_time = get_timer(0); 588 589 if (data == 0 || data_len == 0) { 590 /*Don't support data transfer of no length or to address 0 */ 591 debug("i2c_transfer: bad call\n"); 592 return I2C_NOK; 593 } 594 595 while (readl(&i2c->iicstat) & I2CSTAT_BSY) { 596 if (get_timer(start_time) > I2C_TIMEOUT_MS) 597 return I2C_NOK_TOUT; 598 } 599 600 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); 601 602 /* Get the slave chip address going */ 603 writel(chip, &i2c->iicds); 604 if ((cmd_type == I2C_WRITE) || (addr && addr_len)) 605 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 606 &i2c->iicstat); 607 else 608 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 609 &i2c->iicstat); 610 611 /* Wait for chip address to transmit. */ 612 result = WaitForXfer(i2c); 613 if (result != I2C_OK) 614 goto bailout; 615 616 /* If register address needs to be transmitted - do it now. */ 617 if (addr && addr_len) { 618 while ((i < addr_len) && (result == I2C_OK)) { 619 writel(addr[i++], &i2c->iicds); 620 read_write_byte(i2c); 621 result = WaitForXfer(i2c); 622 } 623 i = 0; 624 if (result != I2C_OK) 625 goto bailout; 626 } 627 628 switch (cmd_type) { 629 case I2C_WRITE: 630 while ((i < data_len) && (result == I2C_OK)) { 631 writel(data[i++], &i2c->iicds); 632 read_write_byte(i2c); 633 result = WaitForXfer(i2c); 634 } 635 break; 636 637 case I2C_READ: 638 if (addr && addr_len) { 639 /* 640 * Register address has been sent, now send slave chip 641 * address again to start the actual read transaction. 642 */ 643 writel(chip, &i2c->iicds); 644 645 /* Generate a re-START. */ 646 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 647 &i2c->iicstat); 648 read_write_byte(i2c); 649 result = WaitForXfer(i2c); 650 651 if (result != I2C_OK) 652 goto bailout; 653 } 654 655 while ((i < data_len) && (result == I2C_OK)) { 656 /* disable ACK for final READ */ 657 if (i == data_len - 1) 658 writel(readl(&i2c->iiccon) 659 & ~I2CCON_ACKGEN, 660 &i2c->iiccon); 661 read_write_byte(i2c); 662 result = WaitForXfer(i2c); 663 data[i++] = readl(&i2c->iicds); 664 } 665 if (result == I2C_NACK) 666 result = I2C_OK; /* Normal terminated read. */ 667 break; 668 669 default: 670 debug("i2c_transfer: bad call\n"); 671 result = I2C_NOK; 672 break; 673 } 674 675 bailout: 676 /* Send STOP. */ 677 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 678 read_write_byte(i2c); 679 680 return result; 681 } 682 683 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) 684 { 685 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 686 uchar buf[1]; 687 int ret; 688 689 buf[0] = 0; 690 691 /* 692 * What is needed is to send the chip address and verify that the 693 * address was <ACK>ed (i.e. there was a chip at that address which 694 * drove the data line low). 695 */ 696 if (i2c_bus->is_highspeed) { 697 ret = hsi2c_read(i2c_bus->hsregs, 698 chip, 0, 0, buf, 1); 699 } else { 700 ret = i2c_transfer(i2c_bus->regs, 701 I2C_READ, chip << 1, 0, 0, buf, 1); 702 } 703 704 return ret != I2C_OK; 705 } 706 707 static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 708 int nmsgs) 709 { 710 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 711 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 712 int ret; 713 714 for (; nmsgs > 0; nmsgs--, msg++) { 715 if (msg->flags & I2C_M_RD) { 716 ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, 717 msg->len); 718 } else { 719 ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, 720 msg->len, true); 721 } 722 if (ret) { 723 exynos5_i2c_reset(i2c_bus); 724 return -EREMOTEIO; 725 } 726 } 727 728 return 0; 729 } 730 731 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg, 732 int seq) 733 { 734 struct s3c24x0_i2c *i2c = i2c_bus->regs; 735 bool is_read = msg->flags & I2C_M_RD; 736 uint status; 737 uint addr; 738 int ret, i; 739 740 if (!seq) 741 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN); 742 743 /* Get the slave chip address going */ 744 addr = msg->addr << 1; 745 writel(addr, &i2c->iicds); 746 status = I2C_TXRX_ENA | I2C_START_STOP; 747 if (is_read) 748 status |= I2C_MODE_MR; 749 else 750 status |= I2C_MODE_MT; 751 writel(status, &i2c->iicstat); 752 if (seq) 753 read_write_byte(i2c); 754 755 /* Wait for chip address to transmit */ 756 ret = WaitForXfer(i2c); 757 if (ret) 758 goto err; 759 760 if (is_read) { 761 for (i = 0; !ret && i < msg->len; i++) { 762 /* disable ACK for final READ */ 763 if (i == msg->len - 1) 764 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN); 765 read_write_byte(i2c); 766 ret = WaitForXfer(i2c); 767 msg->buf[i] = readl(&i2c->iicds); 768 } 769 if (ret == I2C_NACK) 770 ret = I2C_OK; /* Normal terminated read */ 771 } else { 772 for (i = 0; !ret && i < msg->len; i++) { 773 writel(msg->buf[i], &i2c->iicds); 774 read_write_byte(i2c); 775 ret = WaitForXfer(i2c); 776 } 777 } 778 779 err: 780 return ret; 781 } 782 783 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 784 int nmsgs) 785 { 786 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 787 struct s3c24x0_i2c *i2c = i2c_bus->regs; 788 ulong start_time; 789 int ret, i; 790 791 start_time = get_timer(0); 792 while (readl(&i2c->iicstat) & I2CSTAT_BSY) { 793 if (get_timer(start_time) > I2C_TIMEOUT_MS) { 794 debug("Timeout\n"); 795 return -ETIMEDOUT; 796 } 797 } 798 799 for (ret = 0, i = 0; !ret && i < nmsgs; i++) 800 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i); 801 802 /* Send STOP */ 803 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 804 read_write_byte(i2c); 805 806 return ret ? -EREMOTEIO : 0; 807 } 808 809 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) 810 { 811 const void *blob = gd->fdt_blob; 812 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 813 int node, flags; 814 815 i2c_bus->is_highspeed = dev_get_driver_data(dev); 816 node = dev->of_offset; 817 818 if (i2c_bus->is_highspeed) { 819 flags = PINMUX_FLAG_HS_MODE; 820 i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev); 821 } else { 822 flags = 0; 823 i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev); 824 } 825 826 i2c_bus->id = pinmux_decode_periph_id(blob, node); 827 828 i2c_bus->clock_frequency = fdtdec_get_int(blob, node, 829 "clock-frequency", 100000); 830 i2c_bus->node = node; 831 i2c_bus->bus_num = dev->seq; 832 833 exynos_pinmux_config(i2c_bus->id, flags); 834 835 i2c_bus->active = true; 836 837 return 0; 838 } 839 840 static const struct dm_i2c_ops s3c_i2c_ops = { 841 .xfer = s3c24x0_i2c_xfer, 842 .probe_chip = s3c24x0_i2c_probe, 843 .set_bus_speed = s3c24x0_i2c_set_bus_speed, 844 }; 845 846 static const struct udevice_id s3c_i2c_ids[] = { 847 { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD }, 848 { } 849 }; 850 851 U_BOOT_DRIVER(i2c_s3c) = { 852 .name = "i2c_s3c", 853 .id = UCLASS_I2C, 854 .of_match = s3c_i2c_ids, 855 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, 856 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), 857 .ops = &s3c_i2c_ops, 858 }; 859 860 /* 861 * TODO(sjg@chromium.org): Move this to a separate file when everything uses 862 * driver model 863 */ 864 static const struct dm_i2c_ops exynos_hs_i2c_ops = { 865 .xfer = exynos_hs_i2c_xfer, 866 .probe_chip = s3c24x0_i2c_probe, 867 .set_bus_speed = s3c24x0_i2c_set_bus_speed, 868 }; 869 870 static const struct udevice_id exynos_hs_i2c_ids[] = { 871 { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS }, 872 { } 873 }; 874 875 U_BOOT_DRIVER(hs_i2c) = { 876 .name = "i2c_s3c_hs", 877 .id = UCLASS_I2C, 878 .of_match = exynos_hs_i2c_ids, 879 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, 880 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), 881 .ops = &exynos_hs_i2c_ops, 882 }; 883