1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2074a1fddSStephen Warren /* 3074a1fddSStephen Warren * Copyright (c) 2016, NVIDIA CORPORATION. 4074a1fddSStephen Warren */ 5074a1fddSStephen Warren 6074a1fddSStephen Warren #ifndef _TEGRA186_GPIO_PRIV_H_ 7074a1fddSStephen Warren #define _TEGRA186_GPIO_PRIV_H_ 8074a1fddSStephen Warren 9074a1fddSStephen Warren /* 10074a1fddSStephen Warren * For each GPIO, there are a set of registers than affect it, all packed 11074a1fddSStephen Warren * back-to-back. 12074a1fddSStephen Warren */ 13074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 14074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 15074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 16074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2 17074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3 18074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0 19074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1 20074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2 21074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3 22074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4) 23074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5) 24074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6) 25074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7) 26074a1fddSStephen Warren 27074a1fddSStephen Warren #define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04 28074a1fddSStephen Warren 29074a1fddSStephen Warren #define TEGRA186_GPIO_INPUT 0x08 30074a1fddSStephen Warren 31074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 32074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 33074a1fddSStephen Warren 34074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 35074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1 36074a1fddSStephen Warren 37074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 38074a1fddSStephen Warren 39074a1fddSStephen Warren /* 40074a1fddSStephen Warren * 8 GPIOs are packed into a port. Their registers appear back-to-back in the 41074a1fddSStephen Warren * port's address space. 42074a1fddSStephen Warren */ 43074a1fddSStephen Warren #define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20 44074a1fddSStephen Warren #define TEGRA186_GPIO_PER_GPIO_COUNT 8 45074a1fddSStephen Warren 46074a1fddSStephen Warren /* 47074a1fddSStephen Warren * Per-port registers are packed immediately following all of a port's 48074a1fddSStephen Warren * per-GPIO registers. 49074a1fddSStephen Warren */ 50074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100 51074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4 52074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8 53074a1fddSStephen Warren 54074a1fddSStephen Warren /* 55074a1fddSStephen Warren * The registers for multiple ports are packed together back-to-back to form 56074a1fddSStephen Warren * the overall controller. 57074a1fddSStephen Warren */ 58074a1fddSStephen Warren #define TEGRA186_GPIO_PER_PORT_STRIDE 0x200 59074a1fddSStephen Warren 60074a1fddSStephen Warren #endif 61