1 /* 2 * (C) Copyright 2009 Samsung Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/gpio.h> 11 12 #define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK) 13 14 #define CON_MASK(x) (0xf << ((x) << 2)) 15 #define CON_SFR(x, v) ((v) << ((x) << 2)) 16 17 #define DAT_MASK(x) (0x1 << (x)) 18 #define DAT_SET(x) (0x1 << (x)) 19 20 #define PULL_MASK(x) (0x3 << ((x) << 1)) 21 #define PULL_MODE(x, v) ((v) << ((x) << 1)) 22 23 #define DRV_MASK(x) (0x3 << ((x) << 1)) 24 #define DRV_SET(x, m) ((m) << ((x) << 1)) 25 #define RATE_MASK(x) (0x1 << (x + 16)) 26 #define RATE_SET(x) (0x1 << (x + 16)) 27 28 #define name_to_gpio(n) s5p_name_to_gpio(n) 29 static inline int s5p_name_to_gpio(const char *name) 30 { 31 unsigned num, irregular_set_number, irregular_bank_base; 32 const struct gpio_name_num_table *tabp; 33 char this_bank, bank_name, irregular_bank_name; 34 char *endp; 35 36 /* 37 * The gpio name starts with either 'g' or 'gp' followed by the bank 38 * name character. Skip one or two characters depending on the prefix. 39 */ 40 if (name[0] == 'g' && name[1] == 'p') 41 name += 2; 42 else if (name[0] == 'g') 43 name++; 44 else 45 return -1; /* Name must start with 'g' */ 46 47 bank_name = *name++; 48 if (!*name) 49 return -1; /* At least one digit is required/expected. */ 50 51 /* 52 * On both exynos5 and exynos5420 architectures there is a bank of 53 * GPIOs which does not fall into the regular address pattern. Those 54 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below 55 * assignments help to handle these irregularities. 56 */ 57 #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) 58 if (cpu_is_exynos5()) { 59 if (proid_is_exynos5420()) { 60 tabp = exynos5420_gpio_table; 61 irregular_bank_name = 'y'; 62 irregular_set_number = '7'; 63 irregular_bank_base = EXYNOS5420_GPIO_Y70; 64 } else { 65 tabp = exynos5_gpio_table; 66 irregular_bank_name = 'c'; 67 irregular_set_number = '4'; 68 irregular_bank_base = EXYNOS5_GPIO_C40; 69 } 70 } else { 71 if (proid_is_exynos4412()) 72 tabp = exynos4x12_gpio_table; 73 else 74 tabp = exynos4_gpio_table; 75 irregular_bank_name = 0; 76 irregular_set_number = 0; 77 irregular_bank_base = 0; 78 } 79 #else 80 if (cpu_is_s5pc110()) 81 tabp = s5pc110_gpio_table; 82 else 83 tabp = s5pc100_gpio_table; 84 irregular_bank_name = 0; 85 irregular_set_number = 0; 86 irregular_bank_base = 0; 87 #endif 88 89 this_bank = tabp->bank; 90 do { 91 if (bank_name == this_bank) { 92 unsigned pin_index; /* pin number within the bank */ 93 if ((bank_name == irregular_bank_name) && 94 (name[0] == irregular_set_number)) { 95 pin_index = name[1] - '0'; 96 /* Irregular sets have 8 pins. */ 97 if (pin_index >= GPIO_PER_BANK) 98 return -1; 99 num = irregular_bank_base + pin_index; 100 } else { 101 pin_index = simple_strtoul(name, &endp, 8); 102 pin_index -= tabp->bank_offset; 103 /* 104 * Sanity check: bunk 'z' has no set number, 105 * for all other banks there must be exactly 106 * two octal digits, and the resulting number 107 * should not exceed the number of pins in the 108 * bank. 109 */ 110 if (((bank_name != 'z') && !name[1]) || 111 *endp || 112 (pin_index >= tabp->bank_size)) 113 return -1; 114 num = tabp->base + pin_index; 115 } 116 return num; 117 } 118 this_bank = (++tabp)->bank; 119 } while (this_bank); 120 121 return -1; 122 } 123 124 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) 125 { 126 unsigned int value; 127 128 value = readl(&bank->con); 129 value &= ~CON_MASK(gpio); 130 value |= CON_SFR(gpio, cfg); 131 writel(value, &bank->con); 132 } 133 134 static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) 135 { 136 unsigned int value; 137 138 value = readl(&bank->dat); 139 value &= ~DAT_MASK(gpio); 140 if (en) 141 value |= DAT_SET(gpio); 142 writel(value, &bank->dat); 143 } 144 145 static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, 146 int gpio, int en) 147 { 148 s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT); 149 s5p_gpio_set_value(bank, gpio, en); 150 } 151 152 static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) 153 { 154 s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT); 155 } 156 157 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) 158 { 159 unsigned int value; 160 161 value = readl(&bank->dat); 162 return !!(value & DAT_MASK(gpio)); 163 } 164 165 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) 166 { 167 unsigned int value; 168 169 value = readl(&bank->pull); 170 value &= ~PULL_MASK(gpio); 171 172 switch (mode) { 173 case S5P_GPIO_PULL_DOWN: 174 case S5P_GPIO_PULL_UP: 175 value |= PULL_MODE(gpio, mode); 176 break; 177 default: 178 break; 179 } 180 181 writel(value, &bank->pull); 182 } 183 184 static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) 185 { 186 unsigned int value; 187 188 value = readl(&bank->drv); 189 value &= ~DRV_MASK(gpio); 190 191 switch (mode) { 192 case S5P_GPIO_DRV_1X: 193 case S5P_GPIO_DRV_2X: 194 case S5P_GPIO_DRV_3X: 195 case S5P_GPIO_DRV_4X: 196 value |= DRV_SET(gpio, mode); 197 break; 198 default: 199 return; 200 } 201 202 writel(value, &bank->drv); 203 } 204 205 static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) 206 { 207 unsigned int value; 208 209 value = readl(&bank->drv); 210 value &= ~RATE_MASK(gpio); 211 212 switch (mode) { 213 case S5P_GPIO_DRV_FAST: 214 case S5P_GPIO_DRV_SLOW: 215 value |= RATE_SET(gpio); 216 break; 217 default: 218 return; 219 } 220 221 writel(value, &bank->drv); 222 } 223 224 static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio) 225 { 226 const struct gpio_info *data; 227 unsigned int upto; 228 int i, count; 229 230 data = get_gpio_data(); 231 count = get_bank_num(); 232 upto = 0; 233 234 for (i = 0; i < count; i++) { 235 debug("i=%d, upto=%d\n", i, upto); 236 if (gpio < data->max_gpio) { 237 struct s5p_gpio_bank *bank; 238 bank = (struct s5p_gpio_bank *)data->reg_addr; 239 bank += (gpio - upto) / GPIO_PER_BANK; 240 debug("gpio=%d, bank=%p\n", gpio, bank); 241 return bank; 242 } 243 244 upto = data->max_gpio; 245 data++; 246 } 247 248 return NULL; 249 } 250 251 int s5p_gpio_get_pin(unsigned gpio) 252 { 253 return S5P_GPIO_GET_PIN(gpio); 254 } 255 256 /* Common GPIO API */ 257 258 int gpio_request(unsigned gpio, const char *label) 259 { 260 return 0; 261 } 262 263 int gpio_free(unsigned gpio) 264 { 265 return 0; 266 } 267 268 int gpio_direction_input(unsigned gpio) 269 { 270 s5p_gpio_direction_input(s5p_gpio_get_bank(gpio), 271 s5p_gpio_get_pin(gpio)); 272 return 0; 273 } 274 275 int gpio_direction_output(unsigned gpio, int value) 276 { 277 s5p_gpio_direction_output(s5p_gpio_get_bank(gpio), 278 s5p_gpio_get_pin(gpio), value); 279 return 0; 280 } 281 282 int gpio_get_value(unsigned gpio) 283 { 284 return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio), 285 s5p_gpio_get_pin(gpio)); 286 } 287 288 int gpio_set_value(unsigned gpio, int value) 289 { 290 s5p_gpio_set_value(s5p_gpio_get_bank(gpio), 291 s5p_gpio_get_pin(gpio), value); 292 293 return 0; 294 } 295 296 void gpio_set_pull(int gpio, int mode) 297 { 298 s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), 299 s5p_gpio_get_pin(gpio), mode); 300 } 301 302 void gpio_set_drv(int gpio, int mode) 303 { 304 s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), 305 s5p_gpio_get_pin(gpio), mode); 306 } 307 308 void gpio_cfg_pin(int gpio, int cfg) 309 { 310 s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), 311 s5p_gpio_get_pin(gpio), cfg); 312 } 313 314 void gpio_set_rate(int gpio, int mode) 315 { 316 s5p_gpio_set_rate(s5p_gpio_get_bank(gpio), 317 s5p_gpio_get_pin(gpio), mode); 318 } 319