1*0f3cf2b3SKeerthy /* SPDX-License-Identifier: GPL-2.0+ */ 2*0f3cf2b3SKeerthy 3*0f3cf2b3SKeerthy #ifndef _GPIO_DA8XX_DEFS_H_ 4*0f3cf2b3SKeerthy #define _GPIO_DA8XX_DEFS_H_ 5*0f3cf2b3SKeerthy 6*0f3cf2b3SKeerthy struct davinci_gpio { 7*0f3cf2b3SKeerthy unsigned int dir; 8*0f3cf2b3SKeerthy unsigned int out_data; 9*0f3cf2b3SKeerthy unsigned int set_data; 10*0f3cf2b3SKeerthy unsigned int clr_data; 11*0f3cf2b3SKeerthy unsigned int in_data; 12*0f3cf2b3SKeerthy unsigned int set_rising; 13*0f3cf2b3SKeerthy unsigned int clr_rising; 14*0f3cf2b3SKeerthy unsigned int set_falling; 15*0f3cf2b3SKeerthy unsigned int clr_falling; 16*0f3cf2b3SKeerthy unsigned int intstat; 17*0f3cf2b3SKeerthy }; 18*0f3cf2b3SKeerthy 19*0f3cf2b3SKeerthy struct davinci_gpio_bank { 20*0f3cf2b3SKeerthy int num_gpio; 21*0f3cf2b3SKeerthy unsigned int irq_num; 22*0f3cf2b3SKeerthy unsigned int irq_mask; 23*0f3cf2b3SKeerthy unsigned long *in_use; 24*0f3cf2b3SKeerthy struct davinci_gpio *base; 25*0f3cf2b3SKeerthy }; 26*0f3cf2b3SKeerthy 27*0f3cf2b3SKeerthy #define GPIO_NAME_SIZE 20 28*0f3cf2b3SKeerthy #define MAX_NUM_GPIOS 144 29*0f3cf2b3SKeerthy #define GPIO_BIT(gp) ((gp) & 0x1F) 30*0f3cf2b3SKeerthy 31*0f3cf2b3SKeerthy #ifdef CONFIG_DM_GPIO 32*0f3cf2b3SKeerthy 33*0f3cf2b3SKeerthy /* Information about a GPIO bank */ 34*0f3cf2b3SKeerthy struct davinci_gpio_platdata { 35*0f3cf2b3SKeerthy int bank_index; 36*0f3cf2b3SKeerthy ulong base; /* address of registers in physical memory */ 37*0f3cf2b3SKeerthy const char *port_name; 38*0f3cf2b3SKeerthy }; 39*0f3cf2b3SKeerthy #endif 40*0f3cf2b3SKeerthy 41*0f3cf2b3SKeerthy #endif 42