183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002
4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
7f6555d90SMichal Simek /* Generic FPGA support */
8c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h> /* core U-Boot definitions */
9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <xilinx.h> /* xilinx specific definitions */
10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <altera.h> /* altera specific definitions */
113b8ac464SStefano Babic #include <lattice.h>
12c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local definitions */
14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_MAX_FPGA_DEVICES
15c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_MAX_FPGA_DEVICES 5
16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
18c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local static data */
19c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int next_desc = FPGA_INVALID_DEVICE;
20c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
22f6555d90SMichal Simek /*
23f6555d90SMichal Simek * fpga_no_sup
24c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 'no support' message function
25c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_no_sup(char * fn,char * msg)26c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static void fpga_no_sup(char *fn, char *msg)
27c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
28f6555d90SMichal Simek if (fn && msg)
29c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: No support for %s.\n", fn, msg);
30f6555d90SMichal Simek else if (msg)
31c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("No support for %s.\n", msg);
32f6555d90SMichal Simek else
3362a3b7ddSRobert P. J. Day printf("No FPGA support!\n");
34c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
35c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
36c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
37c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* fpga_get_desc
38c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * map a device number to a descriptor
39c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_get_desc(int devnum)40ebd322deSMichal Simek const fpga_desc *const fpga_get_desc(int devnum)
41c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
42c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_desc *desc = (fpga_desc *)NULL;
43c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
44c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((devnum >= 0) && (devnum < next_desc)) {
45c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc = &desc_table[devnum];
46f6555d90SMichal Simek debug("%s: found fpga descriptor #%d @ 0x%p\n",
47f6555d90SMichal Simek __func__, devnum, desc);
48c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
49c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
50c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc;
51c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
52c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
53f6555d90SMichal Simek /*
54f6555d90SMichal Simek * fpga_validate
55c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic parameter checking code
56c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_validate(int devnum,const void * buf,size_t bsize,char * fn)576631db47SMichal Simek const fpga_desc *const fpga_validate(int devnum, const void *buf,
58c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD size_t bsize, char *fn)
59c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
60f6555d90SMichal Simek const fpga_desc *desc = fpga_get_desc(devnum);
61c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
62f6555d90SMichal Simek if (!desc)
63c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid device number %d\n", fn, devnum);
64c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
65c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!buf) {
66c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Null buffer.\n", fn);
67c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return (fpga_desc * const)NULL;
68c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
69c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc;
70c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
71c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
72f6555d90SMichal Simek /*
73f6555d90SMichal Simek * fpga_dev_info
74c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code
75c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_dev_info(int devnum)76c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int fpga_dev_info(int devnum)
77c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
78c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */
79c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD const fpga_desc * const desc = fpga_get_desc(devnum);
80c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
81c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) {
82f6555d90SMichal Simek debug("%s: Device Descriptor @ 0x%p\n",
83f6555d90SMichal Simek __func__, desc->devdesc);
84c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
85c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) {
86c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx:
87c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX)
88c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Xilinx Device\nDescriptor @ 0x%p\n", desc);
89c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_info(desc->devdesc);
90c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
91f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices");
92c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
93c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
94c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera:
95c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA)
96c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Altera Device\nDescriptor @ 0x%p\n", desc);
97c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_info(desc->devdesc);
98c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
99f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices");
100c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
101c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
1023b8ac464SStefano Babic case fpga_lattice:
103439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE)
1043b8ac464SStefano Babic printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
1053b8ac464SStefano Babic ret_val = lattice_info(desc->devdesc);
106439f6f7eSWolfgang Denk #else
107f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices");
108439f6f7eSWolfgang Denk #endif
1093b8ac464SStefano Babic break;
110c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default:
111c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n",
112f6555d90SMichal Simek __func__, desc->devtype);
113c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
114c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else {
115f6555d90SMichal Simek printf("%s: Invalid device number %d\n", __func__, devnum);
116c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
117c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
118c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val;
119c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
120c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
121f6555d90SMichal Simek /*
122905bca6cSMichal Simek * fpga_init is usually called from misc_init_r() and MUST be called
123c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * before any of the other fpga functions are used.
124c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_init(void)1256385b281SPeter Tyser void fpga_init(void)
126c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
127c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD next_desc = 0;
128c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD memset(desc_table, 0, sizeof(desc_table));
129c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
130ee976c1bSMichal Simek debug("%s\n", __func__);
131c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
132c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
133f6555d90SMichal Simek /*
134f6555d90SMichal Simek * fpga_count
135c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Basic interface function to get the current number of devices available.
136c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_count(void)137c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_count(void)
138c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
139c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return next_desc;
140c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
141c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
142f6555d90SMichal Simek /*
143f6555d90SMichal Simek * fpga_add
1446385b281SPeter Tyser * Add the device descriptor to the device table.
145c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_add(fpga_type devtype,void * desc)146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_add(fpga_type devtype, void *desc)
147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
148c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int devnum = FPGA_INVALID_DEVICE;
149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
150cda1e3fbSMichal Simek if (!desc) {
151cda1e3fbSMichal Simek printf("%s: NULL device descriptor\n", __func__);
152cda1e3fbSMichal Simek return devnum;
153cda1e3fbSMichal Simek }
154cda1e3fbSMichal Simek
155c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < 0) {
156f6555d90SMichal Simek printf("%s: FPGA support not initialized!\n", __func__);
157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD devnum = next_desc;
160c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc].devtype = devtype;
161c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc++].devdesc = desc;
162c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else {
163f6555d90SMichal Simek printf("%s: Exceeded Max FPGA device count\n",
164f6555d90SMichal Simek __func__);
165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
166c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else {
167f6555d90SMichal Simek printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
169c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return devnum;
171c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
172c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
1748b93a92fSGoldschmidt Simon * Return 1 if the fpga data is partial.
1758b93a92fSGoldschmidt Simon * This is only required for fpga drivers that support bitstream_type.
1768b93a92fSGoldschmidt Simon */
fpga_is_partial_data(int devnum,size_t img_len)1778b93a92fSGoldschmidt Simon int __weak fpga_is_partial_data(int devnum, size_t img_len)
1788b93a92fSGoldschmidt Simon {
1798b93a92fSGoldschmidt Simon return 0;
1808b93a92fSGoldschmidt Simon }
1818b93a92fSGoldschmidt Simon
1828b93a92fSGoldschmidt Simon /*
18352c20644SMichal Simek * Convert bitstream data and load into the fpga
18452c20644SMichal Simek */
fpga_loadbitstream(int devnum,char * fpgadata,size_t size,bitstream_type bstype)1857a78bd26SMichal Simek int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
1867a78bd26SMichal Simek bitstream_type bstype)
18752c20644SMichal Simek {
18852c20644SMichal Simek printf("Bitstream support not implemented for this FPGA device\n");
18952c20644SMichal Simek return FPGA_FAIL;
19052c20644SMichal Simek }
19152c20644SMichal Simek
1921a897668SSiva Durga Prasad Paladugu #if defined(CONFIG_CMD_FPGA_LOADFS)
fpga_fsload(int devnum,const void * buf,size_t size,fpga_fs_info * fpga_fsinfo)1931a897668SSiva Durga Prasad Paladugu int fpga_fsload(int devnum, const void *buf, size_t size,
1941a897668SSiva Durga Prasad Paladugu fpga_fs_info *fpga_fsinfo)
1951a897668SSiva Durga Prasad Paladugu {
1961a897668SSiva Durga Prasad Paladugu int ret_val = FPGA_FAIL; /* assume failure */
1971a897668SSiva Durga Prasad Paladugu const fpga_desc *desc = fpga_validate(devnum, buf, size,
1981a897668SSiva Durga Prasad Paladugu (char *)__func__);
1991a897668SSiva Durga Prasad Paladugu
2001a897668SSiva Durga Prasad Paladugu if (desc) {
2011a897668SSiva Durga Prasad Paladugu switch (desc->devtype) {
2021a897668SSiva Durga Prasad Paladugu case fpga_xilinx:
2031a897668SSiva Durga Prasad Paladugu #if defined(CONFIG_FPGA_XILINX)
2041a897668SSiva Durga Prasad Paladugu ret_val = xilinx_loadfs(desc->devdesc, buf, size,
2051a897668SSiva Durga Prasad Paladugu fpga_fsinfo);
2061a897668SSiva Durga Prasad Paladugu #else
2071a897668SSiva Durga Prasad Paladugu fpga_no_sup((char *)__func__, "Xilinx devices");
2081a897668SSiva Durga Prasad Paladugu #endif
2091a897668SSiva Durga Prasad Paladugu break;
2101a897668SSiva Durga Prasad Paladugu default:
2111a897668SSiva Durga Prasad Paladugu printf("%s: Invalid or unsupported device type %d\n",
2121a897668SSiva Durga Prasad Paladugu __func__, desc->devtype);
2131a897668SSiva Durga Prasad Paladugu }
2141a897668SSiva Durga Prasad Paladugu }
2151a897668SSiva Durga Prasad Paladugu
2161a897668SSiva Durga Prasad Paladugu return ret_val;
2171a897668SSiva Durga Prasad Paladugu }
2181a897668SSiva Durga Prasad Paladugu #endif
2191a897668SSiva Durga Prasad Paladugu
220*cedd48e2SSiva Durga Prasad Paladugu #if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
fpga_loads(int devnum,const void * buf,size_t size,struct fpga_secure_info * fpga_sec_info)221*cedd48e2SSiva Durga Prasad Paladugu int fpga_loads(int devnum, const void *buf, size_t size,
222*cedd48e2SSiva Durga Prasad Paladugu struct fpga_secure_info *fpga_sec_info)
223*cedd48e2SSiva Durga Prasad Paladugu {
224*cedd48e2SSiva Durga Prasad Paladugu int ret_val = FPGA_FAIL;
225*cedd48e2SSiva Durga Prasad Paladugu
226*cedd48e2SSiva Durga Prasad Paladugu const fpga_desc *desc = fpga_validate(devnum, buf, size,
227*cedd48e2SSiva Durga Prasad Paladugu (char *)__func__);
228*cedd48e2SSiva Durga Prasad Paladugu
229*cedd48e2SSiva Durga Prasad Paladugu if (desc) {
230*cedd48e2SSiva Durga Prasad Paladugu switch (desc->devtype) {
231*cedd48e2SSiva Durga Prasad Paladugu case fpga_xilinx:
232*cedd48e2SSiva Durga Prasad Paladugu #if defined(CONFIG_FPGA_XILINX)
233*cedd48e2SSiva Durga Prasad Paladugu ret_val = xilinx_loads(desc->devdesc, buf, size,
234*cedd48e2SSiva Durga Prasad Paladugu fpga_sec_info);
235*cedd48e2SSiva Durga Prasad Paladugu #else
236*cedd48e2SSiva Durga Prasad Paladugu fpga_no_sup((char *)__func__, "Xilinx devices");
237*cedd48e2SSiva Durga Prasad Paladugu #endif
238*cedd48e2SSiva Durga Prasad Paladugu break;
239*cedd48e2SSiva Durga Prasad Paladugu default:
240*cedd48e2SSiva Durga Prasad Paladugu printf("%s: Invalid or unsupported device type %d\n",
241*cedd48e2SSiva Durga Prasad Paladugu __func__, desc->devtype);
242*cedd48e2SSiva Durga Prasad Paladugu }
243*cedd48e2SSiva Durga Prasad Paladugu }
244*cedd48e2SSiva Durga Prasad Paladugu
245*cedd48e2SSiva Durga Prasad Paladugu return ret_val;
246*cedd48e2SSiva Durga Prasad Paladugu }
247*cedd48e2SSiva Durga Prasad Paladugu #endif
248*cedd48e2SSiva Durga Prasad Paladugu
24952c20644SMichal Simek /*
250c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Generic multiplexing code
251c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_load(int devnum,const void * buf,size_t bsize,bitstream_type bstype)2527a78bd26SMichal Simek int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
253c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
254c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */
255f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
256f6555d90SMichal Simek (char *)__func__);
257c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
258c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) {
259c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) {
260c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx:
261c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX)
2627a78bd26SMichal Simek ret_val = xilinx_load(desc->devdesc, buf, bsize,
2637a78bd26SMichal Simek bstype);
264c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
265f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices");
266c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
267c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
268c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera:
269c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA)
270c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_load(desc->devdesc, buf, bsize);
271c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
272f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices");
273c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
274c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
2753b8ac464SStefano Babic case fpga_lattice:
276439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE)
2773b8ac464SStefano Babic ret_val = lattice_load(desc->devdesc, buf, bsize);
278439f6f7eSWolfgang Denk #else
279f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices");
280439f6f7eSWolfgang Denk #endif
2813b8ac464SStefano Babic break;
282c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default:
283c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n",
284f6555d90SMichal Simek __func__, desc->devtype);
285c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
286c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
287c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
288c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val;
289c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
290c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
291f6555d90SMichal Simek /*
292f6555d90SMichal Simek * fpga_dump
293c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code
294c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_dump(int devnum,const void * buf,size_t bsize)295e6a857daSWolfgang Denk int fpga_dump(int devnum, const void *buf, size_t bsize)
296c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
297c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */
298f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
299f6555d90SMichal Simek (char *)__func__);
300c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
301c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) {
302c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) {
303c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx:
304c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX)
305c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_dump(desc->devdesc, buf, bsize);
306c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
307f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices");
308c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
309c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
310c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera:
311c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA)
312c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_dump(desc->devdesc, buf, bsize);
313c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
314f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices");
315c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
316c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break;
3173b8ac464SStefano Babic case fpga_lattice:
318439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE)
3193b8ac464SStefano Babic ret_val = lattice_dump(desc->devdesc, buf, bsize);
320439f6f7eSWolfgang Denk #else
321f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices");
322439f6f7eSWolfgang Denk #endif
3233b8ac464SStefano Babic break;
324c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default:
325c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n",
326f6555d90SMichal Simek __func__, desc->devtype);
327c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
328c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
329c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
330c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val;
331c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
332c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
333f6555d90SMichal Simek /*
334f6555d90SMichal Simek * fpga_info
335c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * front end to fpga_dev_info. If devnum is invalid, report on all
336c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * available devices.
337c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */
fpga_info(int devnum)338c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_info(int devnum)
339c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
340c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (devnum == FPGA_INVALID_DEVICE) {
341c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc > 0) {
342c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int dev;
343c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
344f6555d90SMichal Simek for (dev = 0; dev < next_desc; dev++)
345c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_dev_info(dev);
346f6555d90SMichal Simek
347c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_SUCCESS;
348c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else {
349f6555d90SMichal Simek printf("%s: No FPGA devices available.\n", __func__);
350c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_FAIL;
351c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
352c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
353c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD
354f6555d90SMichal Simek return fpga_dev_info(devnum);
355f6555d90SMichal Simek }
356