1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2ff9112dfSStefan Roese /* 3ff9112dfSStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4ff9112dfSStefan Roese */ 5ff9112dfSStefan Roese 6ff9112dfSStefan Roese #ifndef __XOR_H 7ff9112dfSStefan Roese #define __XOR_H 8ff9112dfSStefan Roese 9ff9112dfSStefan Roese #include "ddr3_hw_training.h" 10ff9112dfSStefan Roese 11ff9112dfSStefan Roese #define MV_XOR_MAX_CHAN 4 /* total channels for all units together */ 12ff9112dfSStefan Roese 13ff9112dfSStefan Roese /* 14ff9112dfSStefan Roese * This enumerator describes the type of functionality the XOR channel 15ff9112dfSStefan Roese * can have while using the same data structures. 16ff9112dfSStefan Roese */ 17ff9112dfSStefan Roese enum xor_type { 18ff9112dfSStefan Roese MV_XOR, /* XOR channel functions as XOR accelerator */ 19ff9112dfSStefan Roese MV_DMA, /* XOR channel functions as IDMA channel */ 20ff9112dfSStefan Roese MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 21ff9112dfSStefan Roese }; 22ff9112dfSStefan Roese 23ff9112dfSStefan Roese /* 24ff9112dfSStefan Roese * This enumerator describes the set of commands that can be applied on 25ff9112dfSStefan Roese * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 26ff9112dfSStefan Roese * status (see MV_STATE enumerator) 27ff9112dfSStefan Roese * Start can be applied only when status is IDLE 28ff9112dfSStefan Roese * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 29ff9112dfSStefan Roese * Pause can be applied only when status is ACTIVE 30ff9112dfSStefan Roese * Restart can be applied only when status is PAUSED 31ff9112dfSStefan Roese */ 32ff9112dfSStefan Roese enum mv_command { 33ff9112dfSStefan Roese MV_START, /* Start */ 34ff9112dfSStefan Roese MV_STOP, /* Stop */ 35ff9112dfSStefan Roese MV_PAUSE, /* Pause */ 36ff9112dfSStefan Roese MV_RESTART /* Restart */ 37ff9112dfSStefan Roese }; 38ff9112dfSStefan Roese 39ff9112dfSStefan Roese /* 40ff9112dfSStefan Roese * This enumerator describes the set of state conditions. 41ff9112dfSStefan Roese * Moving from one state to other is stricted. 42ff9112dfSStefan Roese */ 43ff9112dfSStefan Roese enum mv_state { 44ff9112dfSStefan Roese MV_IDLE, 45ff9112dfSStefan Roese MV_ACTIVE, 46ff9112dfSStefan Roese MV_PAUSED, 47ff9112dfSStefan Roese MV_UNDEFINED_STATE 48ff9112dfSStefan Roese }; 49ff9112dfSStefan Roese 50ff9112dfSStefan Roese /* XOR descriptor structure for CRC and DMA descriptor */ 51ff9112dfSStefan Roese struct crc_dma_desc { 52ff9112dfSStefan Roese u32 status; /* Successful descriptor execution indication */ 53ff9112dfSStefan Roese u32 crc32_result; /* Result of CRC-32 calculation */ 54ff9112dfSStefan Roese u32 desc_cmd; /* type of operation to be carried out on the data */ 55ff9112dfSStefan Roese u32 next_desc_ptr; /* Next descriptor address pointer */ 56ff9112dfSStefan Roese u32 byte_cnt; /* Size of source block part represented by the descriptor */ 57ff9112dfSStefan Roese u32 dst_addr; /* Destination Block address pointer (not used in CRC32 */ 58ff9112dfSStefan Roese u32 src_addr0; /* Mode: Source Block address pointer */ 59ff9112dfSStefan Roese u32 src_addr1; /* Mode: Source Block address pointer */ 60ff9112dfSStefan Roese } __packed; 61ff9112dfSStefan Roese 620ceb2daeSStefan Roese void mv_xor_hal_init(u32 chan_num); 63ff9112dfSStefan Roese int mv_xor_state_get(u32 chan); 64ff9112dfSStefan Roese void mv_sys_xor_init(MV_DRAM_INFO *dram_info); 65ff9112dfSStefan Roese void mv_sys_xor_finish(void); 66ff9112dfSStefan Roese int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr); 67ff9112dfSStefan Roese int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, 68ff9112dfSStefan Roese u32 init_val_low); 69ff9112dfSStefan Roese 70ff9112dfSStefan Roese #endif /* __XOR_H */ 71