xref: /openbmc/u-boot/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046) 
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */
2ff9112dfSStefan Roese /*
3ff9112dfSStefan Roese  * Copyright (C) Marvell International Ltd. and its affiliates
4ff9112dfSStefan Roese  */
5ff9112dfSStefan Roese 
6ff9112dfSStefan Roese #ifndef __AXP_MC_STATIC_H
7ff9112dfSStefan Roese #define __AXP_MC_STATIC_H
8ff9112dfSStefan Roese 
9ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
104444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
11ff9112dfSStefan Roese 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
124444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
13ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
14ff9112dfSStefan Roese #endif
15ff9112dfSStefan Roese 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
16ff9112dfSStefan Roese 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
17ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18ff9112dfSStefan Roese 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
19ff9112dfSStefan Roese 
20ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
21ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
22ff9112dfSStefan Roese #else
23ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
24ff9112dfSStefan Roese #endif
25ff9112dfSStefan Roese 
26ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
27ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
28ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
29ff9112dfSStefan Roese 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
30ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
31ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
32ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
33ff9112dfSStefan Roese 
34ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
35ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
36ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
37ff9112dfSStefan Roese 
38ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
39ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
40ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
41ff9112dfSStefan Roese 
42ff9112dfSStefan Roese 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
43ff9112dfSStefan Roese 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
44ff9112dfSStefan Roese 
45ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
46ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
47ff9112dfSStefan Roese 
48ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
49ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
50ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
51ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
52ff9112dfSStefan Roese 
53ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
54ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
55ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
56ff9112dfSStefan Roese 
57ff9112dfSStefan Roese 	{0x000015D0, 0x00000640},	/*MR0 */
58ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
59ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
60ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
61ff9112dfSStefan Roese 
62ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
63ff9112dfSStefan Roese 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
64ff9112dfSStefan Roese 	{0x0, 0x0}
65ff9112dfSStefan Roese };
66ff9112dfSStefan Roese 
67ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
684444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
69ff9112dfSStefan Roese 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
704444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
71ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
72ff9112dfSStefan Roese #endif
73ff9112dfSStefan Roese 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
74ff9112dfSStefan Roese 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
75ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
76ff9112dfSStefan Roese 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
77ff9112dfSStefan Roese 
78ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
79ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
80ff9112dfSStefan Roese #else
81ff9112dfSStefan Roese 	{0x00001410, 0x040F000C},	/*DDR SDRAM Open Pages Control Register */
82ff9112dfSStefan Roese #endif
83ff9112dfSStefan Roese 
84ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
85ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
86ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
87ff9112dfSStefan Roese 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
88ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
89ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
90ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
91ff9112dfSStefan Roese 
92ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
93ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
94ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
95ff9112dfSStefan Roese 
96ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
97ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
98ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
99ff9112dfSStefan Roese 
100ff9112dfSStefan Roese 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
101ff9112dfSStefan Roese 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
102ff9112dfSStefan Roese 
103ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
104ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
105ff9112dfSStefan Roese 
106ff9112dfSStefan Roese 	{0x0001504, 0x3FFFFFF1},	/* CS0 Size */
107ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
108ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
109ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
110ff9112dfSStefan Roese 
111ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
112ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
113ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
114ff9112dfSStefan Roese 
115ff9112dfSStefan Roese 	{0x000015D0, 0x00000640},	/*MR0 */
116ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
117ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
118ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
119ff9112dfSStefan Roese 
120ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
121ff9112dfSStefan Roese 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
122ff9112dfSStefan Roese 	{0x0, 0x0}
123ff9112dfSStefan Roese };
124ff9112dfSStefan Roese 
125ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
1264444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
127ff9112dfSStefan Roese 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
1284444d230SPhil Sutter #else /* CONFIG_DDR_64BIT */
129ff9112dfSStefan Roese 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
130ff9112dfSStefan Roese #endif
131ff9112dfSStefan Roese 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
132ff9112dfSStefan Roese 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
133ff9112dfSStefan Roese 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
134ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
135ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
136ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
137ff9112dfSStefan Roese 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
138ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
139ff9112dfSStefan Roese 	{0x00001424, 0x0100D3FF},	/*Dunit Control High Register */
140ff9112dfSStefan Roese 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
141ff9112dfSStefan Roese 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
142ff9112dfSStefan Roese 	{0x0000147C, 0x00006571},
143ff9112dfSStefan Roese 
144ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
145ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
146ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
147ff9112dfSStefan Roese 
148ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
149ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
150ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
151ff9112dfSStefan Roese 
152ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
153ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
154ff9112dfSStefan Roese 
155ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
156ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
157ff9112dfSStefan Roese 
158ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
159ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
160ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
161ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
162ff9112dfSStefan Roese 
163ff9112dfSStefan Roese 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
164ff9112dfSStefan Roese 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
165ff9112dfSStefan Roese 
166ff9112dfSStefan Roese 	{0x000015D0, 0x00000630},	/*MR0 */
167ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
168ff9112dfSStefan Roese 	{0x000015D8, 0x00000008},	/*MR2 */
169ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
170ff9112dfSStefan Roese 
171ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
172ff9112dfSStefan Roese 	/* {0x000015EC, 0xDE000025}, *//*DDR PHY */
173ff9112dfSStefan Roese 	{0x000015EC, 0xF800AA25},	/*DDR PHY */
174ff9112dfSStefan Roese 	{0x0, 0x0}
175ff9112dfSStefan Roese };
176ff9112dfSStefan Roese 
177ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
1784444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
179ff9112dfSStefan Roese 	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
1804444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
181ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
182ff9112dfSStefan Roese #endif
183ff9112dfSStefan Roese 	{0x00001404, 0x3630B040},	/*Dunit Control Low Register */
184ff9112dfSStefan Roese 	{0x00001408, 0x44149887},	/*DDR SDRAM Timing (Low) Register */
185ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
186ff9112dfSStefan Roese 	{0x0000140C, 0x38D83FE0},	/*DDR SDRAM Timing (High) Register */
187ff9112dfSStefan Roese 
188ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
189ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
190ff9112dfSStefan Roese #else
191ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
192ff9112dfSStefan Roese #endif
193ff9112dfSStefan Roese 
194ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
195ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
196ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
197ff9112dfSStefan Roese 	{0x00001424, 0x0100D1FF},	/*Dunit Control High Register */
198ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
199ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
200ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
201ff9112dfSStefan Roese 
202ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
203ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
204ff9112dfSStefan Roese 
205ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
206ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
207ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
208ff9112dfSStefan Roese 
209ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
210ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
211ff9112dfSStefan Roese 
212ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
213ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
214ff9112dfSStefan Roese 
215ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
216ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
217ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
218ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
219ff9112dfSStefan Roese 
220ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
221ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
222ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
223ff9112dfSStefan Roese 
224ff9112dfSStefan Roese 	{0x000015D0, 0x00000650},	/*MR0 */
225ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
226ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
227ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
228ff9112dfSStefan Roese 
229ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
230ff9112dfSStefan Roese 	{0x000015EC, 0xDE000025},	/*DDR PHY */
231ff9112dfSStefan Roese 	{0x0, 0x0}
232ff9112dfSStefan Roese };
233ff9112dfSStefan Roese 
234ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
2354444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
236ff9112dfSStefan Roese 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
2374444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
238ff9112dfSStefan Roese 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
239ff9112dfSStefan Roese 	/*{0x00001400, 0x7304CC30},  *//*DDR SDRAM Configuration Register */
240ff9112dfSStefan Roese #endif
241ff9112dfSStefan Roese 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
242ff9112dfSStefan Roese 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
243ff9112dfSStefan Roese 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
244ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
245ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
246ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
247ff9112dfSStefan Roese 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
248ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
249ff9112dfSStefan Roese 	{0x00001424, 0x0100F1FF},	/*Dunit Control High Register */
250ff9112dfSStefan Roese 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
251ff9112dfSStefan Roese 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
252ff9112dfSStefan Roese 	{0x0000147C, 0x00006571},
253ff9112dfSStefan Roese 
254ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
255ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
256ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
257ff9112dfSStefan Roese 
258ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
259ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
260ff9112dfSStefan Roese 
261ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
262ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
263ff9112dfSStefan Roese 
264ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
265ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
266ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
267ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
268ff9112dfSStefan Roese 
269ff9112dfSStefan Roese 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
270ff9112dfSStefan Roese 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
271ff9112dfSStefan Roese 
272ff9112dfSStefan Roese 	{0x000015D0, 0x00000630},	/*MR0 */
273ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
274ff9112dfSStefan Roese 	{0x000015D8, 0x00000008},	/*MR2 */
275ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
276ff9112dfSStefan Roese 
277ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
278ff9112dfSStefan Roese 	{0x000015EC, 0xDE000025},	/*DDR PHY */
279ff9112dfSStefan Roese 
280ff9112dfSStefan Roese 	{0x0, 0x0}
281ff9112dfSStefan Roese };
282ff9112dfSStefan Roese 
283ff9112dfSStefan Roese #endif /* __AXP_MC_STATIC_H */
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