1 2 #include "ddr3_init.h" 3 #include "mv_ddr_training_db.h" 4 #include "mv_ddr_regs.h" 5 #include "mv_ddr_sys_env_lib.h" 6 7 #define DDR_INTERFACES_NUM 1 8 #define DDR_INTERFACE_OCTETS_NUM 5 9 10 /* 11 * 1. L2 filter should be set at binary header to 0xD000000, 12 * to avoid conflict with internal register IO. 13 * 2. U-Boot modifies internal registers base to 0xf100000, 14 * and than should update L2 filter accordingly to 0xf000000 (3.75 GB) 15 */ 16 #define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xC0000000 /* temporary limit l2 filter to 3gb (LSP issue) */ 17 #define ADDRESS_FILTERING_END_REGISTER 0x8c04 18 19 #define DYNAMIC_CS_SIZE_CONFIG 20 #define DISABLE_L2_FILTERING_DURING_DDR_TRAINING 21 22 /* Termal Sensor Registers */ 23 #define TSEN_CONTROL_LSB_REG 0xE4070 24 #define TSEN_CONTROL_LSB_TC_TRIM_OFFSET 0 25 #define TSEN_CONTROL_LSB_TC_TRIM_MASK (0x7 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET) 26 #define TSEN_CONTROL_MSB_REG 0xE4074 27 #define TSEN_CONTROL_MSB_RST_OFFSET 8 28 #define TSEN_CONTROL_MSB_RST_MASK (0x1 << TSEN_CONTROL_MSB_RST_OFFSET) 29 #define TSEN_STATUS_REG 0xe4078 30 #define TSEN_STATUS_READOUT_VALID_OFFSET 10 31 #define TSEN_STATUS_READOUT_VALID_MASK (0x1 << \ 32 TSEN_STATUS_READOUT_VALID_OFFSET) 33 #define TSEN_STATUS_TEMP_OUT_OFFSET 0 34 #define TSEN_STATUS_TEMP_OUT_MASK (0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET) 35 36 static struct dlb_config ddr3_dlb_config_table[] = { 37 {DLB_CTRL_REG, 0x2000005c}, 38 {DLB_BUS_OPT_WT_REG, 0x00880000}, 39 {DLB_AGING_REG, 0x0f7f007f}, 40 {DLB_EVICTION_CTRL_REG, 0x0000129f}, 41 {DLB_EVICTION_TIMERS_REG, 0x00ff0000}, 42 {DLB_WTS_DIFF_CS_REG, 0x04030802}, 43 {DLB_WTS_DIFF_BG_REG, 0x00000a02}, 44 {DLB_WTS_SAME_BG_REG, 0x09000a01}, 45 {DLB_WTS_CMDS_REG, 0x00020005}, 46 {DLB_WTS_ATTR_PRIO_REG, 0x00060f10}, 47 {DLB_QUEUE_MAP_REG, 0x00000543}, 48 {DLB_SPLIT_REG, 0x00000000}, 49 {DLB_USER_CMD_REG, 0x00000000}, 50 {0x0, 0x0} 51 }; 52 53 static struct dlb_config *sys_env_dlb_config_ptr_get(void) 54 { 55 return &ddr3_dlb_config_table[0]; 56 } 57 58 static u8 a38x_bw_per_freq[MV_DDR_FREQ_LAST] = { 59 0x3, /* MV_DDR_FREQ_100 */ 60 0x4, /* MV_DDR_FREQ_400 */ 61 0x4, /* MV_DDR_FREQ_533 */ 62 0x5, /* MV_DDR_FREQ_667 */ 63 0x5, /* MV_DDR_FREQ_800 */ 64 0x5, /* MV_DDR_FREQ_933 */ 65 0x5, /* MV_DDR_FREQ_1066 */ 66 0x3, /* MV_DDR_FREQ_311 */ 67 0x3, /* MV_DDR_FREQ_333 */ 68 0x4, /* MV_DDR_FREQ_467 */ 69 0x5, /* MV_DDR_FREQ_850 */ 70 0x5, /* MV_DDR_FREQ_600 */ 71 0x3, /* MV_DDR_FREQ_300 */ 72 0x5, /* MV_DDR_FREQ_900 */ 73 0x3, /* MV_DDR_FREQ_360 */ 74 0x5 /* MV_DDR_FREQ_1000 */ 75 }; 76 77 static u8 a38x_rate_per_freq[MV_DDR_FREQ_LAST] = { 78 0x1, /* MV_DDR_FREQ_100 */ 79 0x2, /* MV_DDR_FREQ_400 */ 80 0x2, /* MV_DDR_FREQ_533 */ 81 0x2, /* MV_DDR_FREQ_667 */ 82 0x2, /* MV_DDR_FREQ_800 */ 83 0x3, /* MV_DDR_FREQ_933 */ 84 0x3, /* MV_DDR_FREQ_1066 */ 85 0x1, /* MV_DDR_FREQ_311 */ 86 0x1, /* MV_DDR_FREQ_333 */ 87 0x2, /* MV_DDR_FREQ_467 */ 88 0x2, /* MV_DDR_FREQ_850 */ 89 0x2, /* MV_DDR_FREQ_600 */ 90 0x1, /* MV_DDR_FREQ_300 */ 91 0x2, /* MV_DDR_FREQ_900 */ 92 0x1, /* MV_DDR_FREQ_360 */ 93 0x2 /* MV_DDR_FREQ_1000 */ 94 }; 95 96 static u16 a38x_vco_freq_per_sar_ref_clk_25_mhz[] = { 97 666, /* 0 */ 98 1332, 99 800, 100 1600, 101 1066, 102 2132, 103 1200, 104 2400, 105 1332, 106 1332, 107 1500, 108 1500, 109 1600, /* 12 */ 110 1600, 111 1700, 112 1700, 113 1866, 114 1866, 115 1800, /* 18 */ 116 2000, 117 2000, 118 4000, 119 2132, 120 2132, 121 2300, 122 2300, 123 2400, 124 2400, 125 2500, 126 2500, 127 800 128 }; 129 130 static u16 a38x_vco_freq_per_sar_ref_clk_40_mhz[] = { 131 666, /* 0 */ 132 1332, 133 800, 134 800, /* 0x3 */ 135 1066, 136 1066, /* 0x5 */ 137 1200, 138 2400, 139 1332, 140 1332, 141 1500, /* 10 */ 142 1600, /* 0xB */ 143 1600, 144 1600, 145 1700, 146 1560, /* 0xF */ 147 1866, 148 1866, 149 1800, 150 2000, 151 2000, /* 20 */ 152 4000, 153 2132, 154 2132, 155 2300, 156 2300, 157 2400, 158 2400, 159 2500, 160 2500, 161 1800 /* 30 - 0x1E */ 162 }; 163 164 165 static u32 async_mode_at_tf; 166 167 static u32 dq_bit_map_2_phy_pin[] = { 168 1, 0, 2, 6, 9, 8, 3, 7, /* 0 */ 169 8, 9, 1, 7, 2, 6, 3, 0, /* 1 */ 170 3, 9, 7, 8, 1, 0, 2, 6, /* 2 */ 171 1, 0, 6, 2, 8, 3, 7, 9, /* 3 */ 172 0, 1, 2, 9, 7, 8, 3, 6, /* 4 */ 173 }; 174 175 void mv_ddr_mem_scrubbing(void) 176 { 177 ddr3_new_tip_ecc_scrub(); 178 } 179 180 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 181 enum mv_ddr_freq freq); 182 183 /* 184 * Read temperature TJ value 185 */ 186 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) 187 { 188 int reg = 0; 189 190 /* Initiates TSEN hardware reset once */ 191 if ((reg_read(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) { 192 reg_bit_set(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK); 193 /* set Tsen Tc Trim to correct default value (errata #132698) */ 194 reg = reg_read(TSEN_CONTROL_LSB_REG); 195 reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK; 196 reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET; 197 reg_write(TSEN_CONTROL_LSB_REG, reg); 198 } 199 mdelay(10); 200 201 /* Check if the readout field is valid */ 202 if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) { 203 printf("%s: TSEN not ready\n", __func__); 204 return 0; 205 } 206 207 reg = reg_read(TSEN_STATUS_REG); 208 reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET; 209 210 return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000; 211 } 212 213 /* 214 * Name: ddr3_tip_a38x_get_freq_config. 215 * Desc: 216 * Args: 217 * Notes: 218 * Returns: MV_OK if success, other error code if fail. 219 */ 220 static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq, 221 struct hws_tip_freq_config_info 222 *freq_config_info) 223 { 224 if (a38x_bw_per_freq[freq] == 0xff) 225 return MV_NOT_SUPPORTED; 226 227 if (freq_config_info == NULL) 228 return MV_BAD_PARAM; 229 230 freq_config_info->bw_per_freq = a38x_bw_per_freq[freq]; 231 freq_config_info->rate_per_freq = a38x_rate_per_freq[freq]; 232 freq_config_info->is_supported = 1; 233 234 return MV_OK; 235 } 236 237 static void dunit_read(u32 addr, u32 mask, u32 *data) 238 { 239 *data = reg_read(addr) & mask; 240 } 241 242 static void dunit_write(u32 addr, u32 mask, u32 data) 243 { 244 u32 reg_val = data; 245 246 if (mask != MASK_ALL_BITS) { 247 dunit_read(addr, MASK_ALL_BITS, ®_val); 248 reg_val &= (~mask); 249 reg_val |= (data & mask); 250 } 251 252 reg_write(addr, reg_val); 253 } 254 255 #define ODPG_ENABLE_REG 0x186d4 256 #define ODPG_EN_OFFS 0 257 #define ODPG_EN_MASK 0x1 258 #define ODPG_EN_ENA 1 259 #define ODPG_EN_DONE 0 260 #define ODPG_DIS_OFFS 8 261 #define ODPG_DIS_MASK 0x1 262 #define ODPG_DIS_DIS 1 263 void mv_ddr_odpg_enable(void) 264 { 265 dunit_write(ODPG_ENABLE_REG, 266 ODPG_EN_MASK << ODPG_EN_OFFS, 267 ODPG_EN_ENA << ODPG_EN_OFFS); 268 } 269 270 void mv_ddr_odpg_disable(void) 271 { 272 dunit_write(ODPG_ENABLE_REG, 273 ODPG_DIS_MASK << ODPG_DIS_OFFS, 274 ODPG_DIS_DIS << ODPG_DIS_OFFS); 275 } 276 277 void mv_ddr_odpg_done_clr(void) 278 { 279 return; 280 } 281 282 int mv_ddr_is_odpg_done(u32 count) 283 { 284 u32 i, data; 285 286 for (i = 0; i < count; i++) { 287 dunit_read(ODPG_ENABLE_REG, MASK_ALL_BITS, &data); 288 if (((data >> ODPG_EN_OFFS) & ODPG_EN_MASK) == 289 ODPG_EN_DONE) 290 break; 291 } 292 293 if (i >= count) { 294 printf("%s: timeout\n", __func__); 295 return MV_FAIL; 296 } 297 298 return MV_OK; 299 } 300 301 void mv_ddr_training_enable(void) 302 { 303 dunit_write(GLOB_CTRL_STATUS_REG, 304 TRAINING_TRIGGER_MASK << TRAINING_TRIGGER_OFFS, 305 TRAINING_TRIGGER_ENA << TRAINING_TRIGGER_OFFS); 306 } 307 308 #define DRAM_INIT_CTRL_STATUS_REG 0x18488 309 #define TRAINING_TRIGGER_OFFS 0 310 #define TRAINING_TRIGGER_MASK 0x1 311 #define TRAINING_TRIGGER_ENA 1 312 #define TRAINING_DONE_OFFS 1 313 #define TRAINING_DONE_MASK 0x1 314 #define TRAINING_DONE_DONE 1 315 #define TRAINING_DONE_NOT_DONE 0 316 #define TRAINING_RESULT_OFFS 2 317 #define TRAINING_RESULT_MASK 0x1 318 #define TRAINING_RESULT_PASS 0 319 #define TRAINING_RESULT_FAIL 1 320 int mv_ddr_is_training_done(u32 count, u32 *result) 321 { 322 u32 i, data; 323 324 if (result == NULL) { 325 printf("%s: NULL result pointer found\n", __func__); 326 return MV_FAIL; 327 } 328 329 for (i = 0; i < count; i++) { 330 dunit_read(DRAM_INIT_CTRL_STATUS_REG, MASK_ALL_BITS, &data); 331 if (((data >> TRAINING_DONE_OFFS) & TRAINING_DONE_MASK) == 332 TRAINING_DONE_DONE) 333 break; 334 } 335 336 if (i >= count) { 337 printf("%s: timeout\n", __func__); 338 return MV_FAIL; 339 } 340 341 *result = (data >> TRAINING_RESULT_OFFS) & TRAINING_RESULT_MASK; 342 343 return MV_OK; 344 } 345 346 #define DM_PAD 10 347 u32 mv_ddr_dm_pad_get(void) 348 { 349 return DM_PAD; 350 } 351 352 /* 353 * Name: ddr3_tip_a38x_select_ddr_controller. 354 * Desc: Enable/Disable access to Marvell's server. 355 * Args: dev_num - device number 356 * enable - whether to enable or disable the server 357 * Notes: 358 * Returns: MV_OK if success, other error code if fail. 359 */ 360 static int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) 361 { 362 u32 reg; 363 364 reg = reg_read(DUAL_DUNIT_CFG_REG); 365 366 if (enable) 367 reg |= (1 << 6); 368 else 369 reg &= ~(1 << 6); 370 371 reg_write(DUAL_DUNIT_CFG_REG, reg); 372 373 return MV_OK; 374 } 375 376 static u8 ddr3_tip_clock_mode(u32 frequency) 377 { 378 if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400)) 379 return 1; 380 381 return 2; 382 } 383 384 static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq) 385 { 386 u32 reg, ref_clk_satr; 387 388 /* Read sample at reset setting */ 389 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> 390 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & 391 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK; 392 393 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); 394 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == 395 DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) { 396 switch (reg) { 397 case 0x1: 398 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 399 ("Warning: Unsupported freq mode for 333Mhz configured(%d)\n", 400 reg)); 401 /* fallthrough */ 402 case 0x0: 403 *freq = MV_DDR_FREQ_333; 404 break; 405 case 0x3: 406 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 407 ("Warning: Unsupported freq mode for 400Mhz configured(%d)\n", 408 reg)); 409 /* fallthrough */ 410 case 0x2: 411 *freq = MV_DDR_FREQ_400; 412 break; 413 case 0xd: 414 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 415 ("Warning: Unsupported freq mode for 533Mhz configured(%d)\n", 416 reg)); 417 /* fallthrough */ 418 case 0x4: 419 *freq = MV_DDR_FREQ_533; 420 break; 421 case 0x6: 422 *freq = MV_DDR_FREQ_600; 423 break; 424 case 0x11: 425 case 0x14: 426 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 427 ("Warning: Unsupported freq mode for 667Mhz configured(%d)\n", 428 reg)); 429 /* fallthrough */ 430 case 0x8: 431 *freq = MV_DDR_FREQ_667; 432 break; 433 case 0x15: 434 case 0x1b: 435 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 436 ("Warning: Unsupported freq mode for 800Mhz configured(%d)\n", 437 reg)); 438 /* fallthrough */ 439 case 0xc: 440 *freq = MV_DDR_FREQ_800; 441 break; 442 case 0x10: 443 *freq = MV_DDR_FREQ_933; 444 break; 445 case 0x12: 446 *freq = MV_DDR_FREQ_900; 447 break; 448 case 0x13: 449 *freq = MV_DDR_FREQ_933; 450 break; 451 default: 452 *freq = 0; 453 return MV_NOT_SUPPORTED; 454 } 455 } else { /* REFCLK 40MHz case */ 456 switch (reg) { 457 case 0x3: 458 *freq = MV_DDR_FREQ_400; 459 break; 460 case 0x5: 461 *freq = MV_DDR_FREQ_533; 462 break; 463 case 0xb: 464 *freq = MV_DDR_FREQ_800; 465 break; 466 case 0x1e: 467 *freq = MV_DDR_FREQ_900; 468 break; 469 default: 470 *freq = 0; 471 return MV_NOT_SUPPORTED; 472 } 473 } 474 475 return MV_OK; 476 } 477 478 static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) 479 { 480 u32 reg, ref_clk_satr; 481 482 /* Read sample at reset setting */ 483 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> 484 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & 485 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK; 486 487 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); 488 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == 489 DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) { 490 switch (reg) { 491 case 0x0: 492 case 0x1: 493 /* Medium is same as TF to run PBS in this freq */ 494 *freq = MV_DDR_FREQ_333; 495 break; 496 case 0x2: 497 case 0x3: 498 /* Medium is same as TF to run PBS in this freq */ 499 *freq = MV_DDR_FREQ_400; 500 break; 501 case 0x4: 502 case 0xd: 503 /* Medium is same as TF to run PBS in this freq */ 504 *freq = MV_DDR_FREQ_533; 505 break; 506 case 0x8: 507 case 0x10: 508 case 0x11: 509 case 0x14: 510 *freq = MV_DDR_FREQ_333; 511 break; 512 case 0xc: 513 case 0x15: 514 case 0x1b: 515 *freq = MV_DDR_FREQ_400; 516 break; 517 case 0x6: 518 *freq = MV_DDR_FREQ_300; 519 break; 520 case 0x12: 521 *freq = MV_DDR_FREQ_360; 522 break; 523 case 0x13: 524 *freq = MV_DDR_FREQ_400; 525 break; 526 default: 527 *freq = 0; 528 return MV_NOT_SUPPORTED; 529 } 530 } else { /* REFCLK 40MHz case */ 531 switch (reg) { 532 case 0x3: 533 /* Medium is same as TF to run PBS in this freq */ 534 *freq = MV_DDR_FREQ_400; 535 break; 536 case 0x5: 537 /* Medium is same as TF to run PBS in this freq */ 538 *freq = MV_DDR_FREQ_533; 539 break; 540 case 0xb: 541 *freq = MV_DDR_FREQ_400; 542 break; 543 case 0x1e: 544 *freq = MV_DDR_FREQ_360; 545 break; 546 default: 547 *freq = 0; 548 return MV_NOT_SUPPORTED; 549 } 550 } 551 552 return MV_OK; 553 } 554 555 static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) 556 { 557 #if defined(CONFIG_ARMADA_39X) 558 info_ptr->device_id = 0x6900; 559 #else 560 info_ptr->device_id = 0x6800; 561 #endif 562 info_ptr->ck_delay = ck_delay; 563 564 return MV_OK; 565 } 566 567 /* check indirect access to phy register file completed */ 568 static int is_prfa_done(void) 569 { 570 u32 reg_val; 571 u32 iter = 0; 572 573 do { 574 if (iter++ > MAX_POLLING_ITERATIONS) { 575 printf("error: %s: polling timeout\n", __func__); 576 return MV_FAIL; 577 } 578 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val); 579 reg_val >>= PRFA_REQ_OFFS; 580 reg_val &= PRFA_REQ_MASK; 581 } while (reg_val == PRFA_REQ_ENA); /* request pending */ 582 583 return MV_OK; 584 } 585 586 /* write to phy register thru indirect access */ 587 static int prfa_write(enum hws_access_type phy_access, u32 phy, 588 enum hws_ddr_phy phy_type, u32 addr, 589 u32 data, enum hws_operation op_type) 590 { 591 u32 reg_val = ((data & PRFA_DATA_MASK) << PRFA_DATA_OFFS) | 592 ((addr & PRFA_REG_NUM_MASK) << PRFA_REG_NUM_OFFS) | 593 ((phy & PRFA_PUP_NUM_MASK) << PRFA_PUP_NUM_OFFS) | 594 ((phy_type & PRFA_PUP_CTRL_DATA_MASK) << PRFA_PUP_CTRL_DATA_OFFS) | 595 ((phy_access & PRFA_PUP_BCAST_WR_ENA_MASK) << PRFA_PUP_BCAST_WR_ENA_OFFS) | 596 (((addr >> 6) & PRFA_REG_NUM_HI_MASK) << PRFA_REG_NUM_HI_OFFS) | 597 ((op_type & PRFA_TYPE_MASK) << PRFA_TYPE_OFFS); 598 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); 599 reg_val |= (PRFA_REQ_ENA << PRFA_REQ_OFFS); 600 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val); 601 602 /* polling for prfa request completion */ 603 if (is_prfa_done() != MV_OK) 604 return MV_FAIL; 605 606 return MV_OK; 607 } 608 609 /* read from phy register thru indirect access */ 610 static int prfa_read(enum hws_access_type phy_access, u32 phy, 611 enum hws_ddr_phy phy_type, u32 addr, u32 *data) 612 { 613 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 614 u32 max_phy = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); 615 u32 i, reg_val; 616 617 if (phy_access == ACCESS_TYPE_MULTICAST) { 618 for (i = 0; i < max_phy; i++) { 619 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); 620 if (prfa_write(ACCESS_TYPE_UNICAST, i, phy_type, addr, 0, OPERATION_READ) != MV_OK) 621 return MV_FAIL; 622 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val); 623 data[i] = (reg_val >> PRFA_DATA_OFFS) & PRFA_DATA_MASK; 624 } 625 } else { 626 if (prfa_write(phy_access, phy, phy_type, addr, 0, OPERATION_READ) != MV_OK) 627 return MV_FAIL; 628 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val); 629 *data = (reg_val >> PRFA_DATA_OFFS) & PRFA_DATA_MASK; 630 } 631 632 return MV_OK; 633 } 634 635 static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) 636 { 637 struct hws_tip_config_func_db config_func; 638 639 /* new read leveling version */ 640 config_func.mv_ddr_dunit_read = dunit_read; 641 config_func.mv_ddr_dunit_write = dunit_write; 642 config_func.tip_dunit_mux_select_func = 643 ddr3_tip_a38x_select_ddr_controller; 644 config_func.tip_get_freq_config_info_func = 645 ddr3_tip_a38x_get_freq_config; 646 config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider; 647 config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info; 648 config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp; 649 config_func.tip_get_clock_ratio = ddr3_tip_clock_mode; 650 config_func.tip_external_read = ddr3_tip_ext_read; 651 config_func.tip_external_write = ddr3_tip_ext_write; 652 config_func.mv_ddr_phy_read = prfa_read; 653 config_func.mv_ddr_phy_write = prfa_write; 654 655 ddr3_tip_init_config_func(dev_num, &config_func); 656 657 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); 658 659 /* set device attributes*/ 660 ddr3_tip_dev_attr_init(dev_num); 661 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_TIP_REV, MV_TIP_REV_4); 662 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE); 663 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_OCTET_PER_INTERFACE, DDR_INTERFACE_OCTETS_NUM); 664 #ifdef CONFIG_ARMADA_39X 665 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 1); 666 #else 667 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 0); 668 #endif 669 670 ca_delay = 0; 671 delay_enable = 1; 672 dfs_low_freq = DFS_LOW_FREQ_VALUE; 673 calibration_update_control = 1; 674 675 ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq); 676 677 return MV_OK; 678 } 679 680 static int mv_ddr_training_mask_set(void) 681 { 682 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 683 enum mv_ddr_freq ddr_freq = tm->interface_params[0].memory_freq; 684 685 mask_tune_func = (SET_LOW_FREQ_MASK_BIT | 686 LOAD_PATTERN_MASK_BIT | 687 SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT | 688 WRITE_LEVELING_SUPP_MASK_BIT | 689 READ_LEVELING_MASK_BIT | 690 PBS_RX_MASK_BIT | 691 PBS_TX_MASK_BIT | 692 SET_TARGET_FREQ_MASK_BIT | 693 WRITE_LEVELING_TF_MASK_BIT | 694 WRITE_LEVELING_SUPP_TF_MASK_BIT | 695 READ_LEVELING_TF_MASK_BIT | 696 CENTRALIZATION_RX_MASK_BIT | 697 CENTRALIZATION_TX_MASK_BIT); 698 rl_mid_freq_wa = 1; 699 700 if ((ddr_freq == MV_DDR_FREQ_333) || (ddr_freq == MV_DDR_FREQ_400)) { 701 mask_tune_func = (WRITE_LEVELING_MASK_BIT | 702 LOAD_PATTERN_2_MASK_BIT | 703 WRITE_LEVELING_SUPP_MASK_BIT | 704 READ_LEVELING_MASK_BIT | 705 PBS_RX_MASK_BIT | 706 PBS_TX_MASK_BIT | 707 CENTRALIZATION_RX_MASK_BIT | 708 CENTRALIZATION_TX_MASK_BIT); 709 rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */ 710 } 711 712 /* Supplementary not supported for ECC modes */ 713 if (mv_ddr_is_ecc_ena()) { 714 mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT; 715 mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT; 716 mask_tune_func &= ~PBS_TX_MASK_BIT; 717 mask_tune_func &= ~PBS_RX_MASK_BIT; 718 } 719 720 return MV_OK; 721 } 722 723 /* function: mv_ddr_set_calib_controller 724 * this function sets the controller which will control 725 * the calibration cycle in the end of the training. 726 * 1 - internal controller 727 * 2 - external controller 728 */ 729 void mv_ddr_set_calib_controller(void) 730 { 731 calibration_update_control = CAL_UPDATE_CTRL_INT; 732 } 733 734 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 735 enum mv_ddr_freq frequency) 736 { 737 u32 divider = 0; 738 u32 sar_val, ref_clk_satr; 739 u32 async_val; 740 u32 freq = mv_ddr_freq_get(frequency); 741 742 if (if_id != 0) { 743 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, 744 ("A38x does not support interface 0x%x\n", 745 if_id)); 746 return MV_BAD_PARAM; 747 } 748 749 /* get VCO freq index */ 750 sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >> 751 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & 752 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK; 753 754 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); 755 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == 756 DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) 757 divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq; 758 else 759 divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq; 760 761 if ((async_mode_at_tf == 1) && (freq > 400)) { 762 /* Set async mode */ 763 dunit_write(0x20220, 0x1000, 0x1000); 764 dunit_write(0xe42f4, 0x200, 0x200); 765 766 /* Wait for async mode setup */ 767 mdelay(5); 768 769 /* Set KNL values */ 770 switch (frequency) { 771 case MV_DDR_FREQ_467: 772 async_val = 0x806f012; 773 break; 774 case MV_DDR_FREQ_533: 775 async_val = 0x807f012; 776 break; 777 case MV_DDR_FREQ_600: 778 async_val = 0x805f00a; 779 break; 780 case MV_DDR_FREQ_667: 781 async_val = 0x809f012; 782 break; 783 case MV_DDR_FREQ_800: 784 async_val = 0x807f00a; 785 break; 786 case MV_DDR_FREQ_850: 787 async_val = 0x80cb012; 788 break; 789 case MV_DDR_FREQ_900: 790 async_val = 0x80d7012; 791 break; 792 case MV_DDR_FREQ_933: 793 async_val = 0x80df012; 794 break; 795 case MV_DDR_FREQ_1000: 796 async_val = 0x80ef012; 797 break; 798 case MV_DDR_FREQ_1066: 799 async_val = 0x80ff012; 800 break; 801 default: 802 /* set MV_DDR_FREQ_667 as default */ 803 async_val = 0x809f012; 804 } 805 dunit_write(0xe42f0, 0xffffffff, async_val); 806 } else { 807 /* Set sync mode */ 808 dunit_write(0x20220, 0x1000, 0x0); 809 dunit_write(0xe42f4, 0x200, 0x0); 810 811 /* cpupll_clkdiv_reset_mask */ 812 dunit_write(0xe4264, 0xff, 0x1f); 813 814 /* cpupll_clkdiv_reload_smooth */ 815 dunit_write(0xe4260, (0xff << 8), (0x2 << 8)); 816 817 /* cpupll_clkdiv_relax_en */ 818 dunit_write(0xe4260, (0xff << 24), (0x2 << 24)); 819 820 /* write the divider */ 821 dunit_write(0xe4268, (0x3f << 8), (divider << 8)); 822 823 /* set cpupll_clkdiv_reload_ratio */ 824 dunit_write(0xe4264, (1 << 8), (1 << 8)); 825 826 /* undet cpupll_clkdiv_reload_ratio */ 827 dunit_write(0xe4264, (1 << 8), 0x0); 828 829 /* clear cpupll_clkdiv_reload_force */ 830 dunit_write(0xe4260, (0xff << 8), 0x0); 831 832 /* clear cpupll_clkdiv_relax_en */ 833 dunit_write(0xe4260, (0xff << 24), 0x0); 834 835 /* clear cpupll_clkdiv_reset_mask */ 836 dunit_write(0xe4264, 0xff, 0x0); 837 } 838 839 /* Dunit training clock + 1:1/2:1 mode */ 840 dunit_write(0x18488, (1 << 16), ((ddr3_tip_clock_mode(frequency) & 0x1) << 16)); 841 dunit_write(0x1524, (1 << 15), ((ddr3_tip_clock_mode(frequency) - 1) << 15)); 842 843 return MV_OK; 844 } 845 846 /* 847 * external read from memory 848 */ 849 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, 850 u32 num_of_bursts, u32 *data) 851 { 852 u32 burst_num; 853 854 for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++) 855 data[burst_num] = readl(reg_addr + 4 * burst_num); 856 857 return MV_OK; 858 } 859 860 /* 861 * external write to memory 862 */ 863 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, 864 u32 num_of_bursts, u32 *data) { 865 u32 burst_num; 866 867 for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++) 868 writel(data[burst_num], reg_addr + 4 * burst_num); 869 870 return MV_OK; 871 } 872 873 int mv_ddr_early_init(void) 874 { 875 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 876 877 /* FIXME: change this configuration per ddr type 878 * configure a380 and a390 to work with receiver odt timing 879 * the odt_config is defined: 880 * '1' in ddr4 881 * '0' in ddr3 882 * here the parameter is run over in ddr4 and ddr3 to '1' (in ddr4 the default is '1') 883 * to configure the odt to work with timing restrictions 884 */ 885 886 mv_ddr_sw_db_init(0, 0); 887 888 if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR) 889 async_mode_at_tf = 1; 890 891 return MV_OK; 892 } 893 894 int mv_ddr_early_init2(void) 895 { 896 mv_ddr_training_mask_set(); 897 898 return MV_OK; 899 } 900 901 int mv_ddr_pre_training_fixup(void) 902 { 903 return 0; 904 } 905 906 int mv_ddr_post_training_fixup(void) 907 { 908 return 0; 909 } 910 911 int ddr3_post_run_alg(void) 912 { 913 return MV_OK; 914 } 915 916 int ddr3_silicon_post_init(void) 917 { 918 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 919 920 /* Set half bus width */ 921 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) { 922 CHECK_STATUS(ddr3_tip_if_write 923 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, 924 SDRAM_CFG_REG, 0x0, 0x8000)); 925 } 926 927 return MV_OK; 928 } 929 930 u32 mv_ddr_init_freq_get(void) 931 { 932 enum mv_ddr_freq freq; 933 934 mv_ddr_sar_freq_get(0, &freq); 935 936 return freq; 937 } 938 939 static u32 ddr3_get_bus_width(void) 940 { 941 u32 bus_width; 942 943 bus_width = (reg_read(SDRAM_CFG_REG) & 0x8000) >> 944 BUS_IN_USE_OFFS; 945 946 return (bus_width == 0) ? 16 : 32; 947 } 948 949 static u32 ddr3_get_device_width(u32 cs) 950 { 951 u32 device_width; 952 953 device_width = (reg_read(SDRAM_ADDR_CTRL_REG) & 954 (CS_STRUCT_MASK << CS_STRUCT_OFFS(cs))) >> 955 CS_STRUCT_OFFS(cs); 956 957 return (device_width == 0) ? 8 : 16; 958 } 959 960 static u32 ddr3_get_device_size(u32 cs) 961 { 962 u32 device_size_low, device_size_high, device_size; 963 u32 data, cs_low_offset, cs_high_offset; 964 965 cs_low_offset = CS_SIZE_OFFS(cs); 966 cs_high_offset = CS_SIZE_HIGH_OFFS(cs); 967 968 data = reg_read(SDRAM_ADDR_CTRL_REG); 969 device_size_low = (data >> cs_low_offset) & 0x3; 970 device_size_high = (data >> cs_high_offset) & 0x1; 971 972 device_size = device_size_low | (device_size_high << 2); 973 974 switch (device_size) { 975 case 0: 976 return 2048; 977 case 2: 978 return 512; 979 case 3: 980 return 1024; 981 case 4: 982 return 4096; 983 case 5: 984 return 8192; 985 case 1: 986 default: 987 DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1); 988 /* zeroes mem size in ddr3_calc_mem_cs_size */ 989 return 0; 990 } 991 } 992 993 int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size) 994 { 995 u32 cs_mem_size; 996 997 /* Calculate in MiB */ 998 cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) * 999 ddr3_get_device_size(cs)) / 8; 1000 1001 /* 1002 * Multiple controller bus width, 2x for 64 bit 1003 * (SoC controller may be 32 or 64 bit, 1004 * so bit 15 in 0x1400, that means if whole bus used or only half, 1005 * have a differnt meaning 1006 */ 1007 cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER; 1008 1009 if ((cs_mem_size < 128) || (cs_mem_size > 4096)) { 1010 DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1); 1011 return MV_BAD_VALUE; 1012 } 1013 1014 *cs_size = cs_mem_size << 20; /* write cs size in bytes */ 1015 1016 return MV_OK; 1017 } 1018 1019 static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) 1020 { 1021 u32 reg, cs; 1022 uint64_t mem_total_size = 0; 1023 uint64_t cs_mem_size = 0; 1024 uint64_t mem_total_size_c, cs_mem_size_c; 1025 1026 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE 1027 u32 physical_mem_size; 1028 u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE; 1029 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 1030 #endif 1031 1032 /* Open fast path windows */ 1033 for (cs = 0; cs < MAX_CS_NUM; cs++) { 1034 if (cs_ena & (1 << cs)) { 1035 /* get CS size */ 1036 if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) 1037 return MV_FAIL; 1038 1039 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE 1040 /* 1041 * if number of address pins doesn't allow to use max 1042 * mem size that is defined in topology 1043 * mem size is defined by DEVICE_MAX_DRAM_ADDRESS_SIZE 1044 */ 1045 physical_mem_size = mem_size 1046 [tm->interface_params[0].memory_size]; 1047 1048 if (ddr3_get_device_width(cs) == 16) { 1049 /* 1050 * 16bit mem device can be twice more - no need 1051 * in less significant pin 1052 */ 1053 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2; 1054 } 1055 1056 if (physical_mem_size > max_mem_size) { 1057 cs_mem_size = max_mem_size * 1058 (ddr3_get_bus_width() / 1059 ddr3_get_device_width(cs)); 1060 printf("Updated Physical Mem size is from 0x%x to %x\n", 1061 physical_mem_size, 1062 DEVICE_MAX_DRAM_ADDRESS_SIZE); 1063 } 1064 #endif 1065 1066 /* set fast path window control for the cs */ 1067 reg = 0xffffe1; 1068 reg |= (cs << 2); 1069 reg |= (cs_mem_size - 1) & 0xffff0000; 1070 /*Open fast path Window */ 1071 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); 1072 1073 /* Set fast path window base address for the cs */ 1074 reg = ((cs_mem_size) * cs) & 0xffff0000; 1075 /* Set base address */ 1076 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); 1077 1078 /* 1079 * Since memory size may be bigger than 4G the summ may 1080 * be more than 32 bit word, 1081 * so to estimate the result divide mem_total_size and 1082 * cs_mem_size by 0x10000 (it is equal to >> 16) 1083 */ 1084 mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff; 1085 cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff; 1086 /* if the sum less than 2 G - calculate the value */ 1087 if (mem_total_size_c + cs_mem_size_c < 0x10000) 1088 mem_total_size += cs_mem_size; 1089 else /* put max possible size */ 1090 mem_total_size = L2_FILTER_FOR_MAX_MEMORY_SIZE; 1091 } 1092 } 1093 1094 /* Set L2 filtering to Max Memory size */ 1095 reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size); 1096 1097 return MV_OK; 1098 } 1099 1100 static int ddr3_restore_and_set_final_windows(u32 *win, const char *ddr_type) 1101 { 1102 u32 win_ctrl_reg, num_of_win_regs; 1103 u32 cs_ena = mv_ddr_sys_env_get_cs_ena_from_reg(); 1104 u32 ui; 1105 1106 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; 1107 num_of_win_regs = 16; 1108 1109 /* Return XBAR windows 4-7 or 16-19 init configuration */ 1110 for (ui = 0; ui < num_of_win_regs; ui++) 1111 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); 1112 1113 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n", 1114 ddr_type); 1115 1116 #if defined DYNAMIC_CS_SIZE_CONFIG 1117 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) 1118 printf("ddr3_fast_path_dynamic_cs_size_config FAILED\n"); 1119 #else 1120 u32 reg, cs; 1121 reg = 0x1fffffe1; 1122 for (cs = 0; cs < MAX_CS_NUM; cs++) { 1123 if (cs_ena & (1 << cs)) { 1124 reg |= (cs << 2); 1125 break; 1126 } 1127 } 1128 /* Open fast path Window to - 0.5G */ 1129 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(0), reg); 1130 #endif 1131 1132 return MV_OK; 1133 } 1134 1135 static int ddr3_save_and_set_training_windows(u32 *win) 1136 { 1137 u32 cs_ena; 1138 u32 reg, tmp_count, cs, ui; 1139 u32 win_ctrl_reg, win_base_reg, win_remap_reg; 1140 u32 num_of_win_regs, win_jump_index; 1141 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; 1142 win_base_reg = REG_XBAR_WIN_4_BASE_ADDR; 1143 win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR; 1144 win_jump_index = 0x10; 1145 num_of_win_regs = 16; 1146 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 1147 1148 #ifdef DISABLE_L2_FILTERING_DURING_DDR_TRAINING 1149 /* 1150 * Disable L2 filtering during DDR training 1151 * (when Cross Bar window is open) 1152 */ 1153 reg_write(ADDRESS_FILTERING_END_REGISTER, 0); 1154 #endif 1155 1156 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; 1157 1158 /* Close XBAR Window 19 - Not needed */ 1159 /* {0x000200e8} - Open Mbus Window - 2G */ 1160 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); 1161 1162 /* Save XBAR Windows 4-19 init configurations */ 1163 for (ui = 0; ui < num_of_win_regs; ui++) 1164 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); 1165 1166 /* Open XBAR Windows 4-7 or 16-19 for other CS */ 1167 reg = 0; 1168 tmp_count = 0; 1169 for (cs = 0; cs < MAX_CS_NUM; cs++) { 1170 if (cs_ena & (1 << cs)) { 1171 switch (cs) { 1172 case 0: 1173 reg = 0x0e00; 1174 break; 1175 case 1: 1176 reg = 0x0d00; 1177 break; 1178 case 2: 1179 reg = 0x0b00; 1180 break; 1181 case 3: 1182 reg = 0x0700; 1183 break; 1184 } 1185 reg |= (1 << 0); 1186 reg |= (SDRAM_CS_SIZE & 0xffff0000); 1187 1188 reg_write(win_ctrl_reg + win_jump_index * tmp_count, 1189 reg); 1190 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & 1191 0xffff0000); 1192 reg_write(win_base_reg + win_jump_index * tmp_count, 1193 reg); 1194 1195 if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) 1196 reg_write(win_remap_reg + 1197 win_jump_index * tmp_count, 0); 1198 1199 tmp_count++; 1200 } 1201 } 1202 1203 return MV_OK; 1204 } 1205 1206 static u32 win[16]; 1207 1208 int mv_ddr_pre_training_soc_config(const char *ddr_type) 1209 { 1210 u32 soc_num; 1211 u32 reg_val; 1212 1213 /* Switching CPU to MRVL ID */ 1214 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> 1215 SAR1_CPU_CORE_OFFSET; 1216 switch (soc_num) { 1217 case 0x3: 1218 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); 1219 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); 1220 /* fallthrough */ 1221 case 0x1: 1222 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); 1223 /* fallthrough */ 1224 case 0x0: 1225 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); 1226 /* fallthrough */ 1227 default: 1228 break; 1229 } 1230 1231 /* 1232 * Set DRAM Reset Mask in case detected GPIO indication of wakeup from 1233 * suspend i.e the DRAM values will not be overwritten / reset when 1234 * waking from suspend 1235 */ 1236 if (mv_ddr_sys_env_suspend_wakeup_check() == 1237 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED) { 1238 reg_bit_set(SDRAM_INIT_CTRL_REG, 1239 DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); 1240 } 1241 1242 /* Check if DRAM is already initialized */ 1243 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & 1244 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { 1245 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); 1246 return MV_OK; 1247 } 1248 1249 /* Fix read ready phases for all SOC in reg 0x15c8 */ 1250 reg_val = reg_read(TRAINING_DBG_3_REG); 1251 1252 reg_val &= ~(TRN_DBG_RDY_INC_PH_2TO1_MASK << TRN_DBG_RDY_INC_PH_2TO1_OFFS(0)); 1253 reg_val |= (0x4 << TRN_DBG_RDY_INC_PH_2TO1_OFFS(0)); /* phase 0 */ 1254 1255 reg_val &= ~(TRN_DBG_RDY_INC_PH_2TO1_MASK << TRN_DBG_RDY_INC_PH_2TO1_OFFS(1)); 1256 reg_val |= (0x4 << TRN_DBG_RDY_INC_PH_2TO1_OFFS(1)); /* phase 1 */ 1257 1258 reg_val &= ~(TRN_DBG_RDY_INC_PH_2TO1_MASK << TRN_DBG_RDY_INC_PH_2TO1_OFFS(3)); 1259 reg_val |= (0x6 << TRN_DBG_RDY_INC_PH_2TO1_OFFS(3)); /* phase 3 */ 1260 1261 reg_val &= ~(TRN_DBG_RDY_INC_PH_2TO1_MASK << TRN_DBG_RDY_INC_PH_2TO1_OFFS(4)); 1262 reg_val |= (0x6 << TRN_DBG_RDY_INC_PH_2TO1_OFFS(4)); /* phase 4 */ 1263 1264 reg_val &= ~(TRN_DBG_RDY_INC_PH_2TO1_MASK << TRN_DBG_RDY_INC_PH_2TO1_OFFS(5)); 1265 reg_val |= (0x6 << TRN_DBG_RDY_INC_PH_2TO1_OFFS(5)); /* phase 5 */ 1266 1267 reg_write(TRAINING_DBG_3_REG, reg_val); 1268 1269 /* 1270 * Axi_bresp_mode[8] = Compliant, 1271 * Axi_addr_decode_cntrl[11] = Internal, 1272 * Axi_data_bus_width[0] = 128bit 1273 * */ 1274 /* 0x14a8 - AXI Control Register */ 1275 reg_write(AXI_CTRL_REG, 0); 1276 1277 /* 1278 * Stage 2 - Training Values Setup 1279 */ 1280 /* Set X-BAR windows for the training sequence */ 1281 ddr3_save_and_set_training_windows(win); 1282 1283 return MV_OK; 1284 } 1285 1286 static int ddr3_new_tip_dlb_config(void) 1287 { 1288 u32 reg, i = 0; 1289 struct dlb_config *config_table_ptr = sys_env_dlb_config_ptr_get(); 1290 1291 /* Write the configuration */ 1292 while (config_table_ptr[i].reg_addr != 0) { 1293 reg_write(config_table_ptr[i].reg_addr, 1294 config_table_ptr[i].reg_data); 1295 i++; 1296 } 1297 1298 1299 /* Enable DLB */ 1300 reg = reg_read(DLB_CTRL_REG); 1301 reg &= ~(DLB_EN_MASK << DLB_EN_OFFS) & 1302 ~(WR_COALESCE_EN_MASK << WR_COALESCE_EN_OFFS) & 1303 ~(AXI_PREFETCH_EN_MASK << AXI_PREFETCH_EN_OFFS) & 1304 ~(MBUS_PREFETCH_EN_MASK << MBUS_PREFETCH_EN_OFFS) & 1305 ~(PREFETCH_NXT_LN_SZ_TRIG_MASK << PREFETCH_NXT_LN_SZ_TRIG_OFFS); 1306 1307 reg |= (DLB_EN_ENA << DLB_EN_OFFS) | 1308 (WR_COALESCE_EN_ENA << WR_COALESCE_EN_OFFS) | 1309 (AXI_PREFETCH_EN_ENA << AXI_PREFETCH_EN_OFFS) | 1310 (MBUS_PREFETCH_EN_ENA << MBUS_PREFETCH_EN_OFFS) | 1311 (PREFETCH_NXT_LN_SZ_TRIG_ENA << PREFETCH_NXT_LN_SZ_TRIG_OFFS); 1312 1313 reg_write(DLB_CTRL_REG, reg); 1314 1315 return MV_OK; 1316 } 1317 1318 int mv_ddr_post_training_soc_config(const char *ddr_type) 1319 { 1320 u32 reg_val; 1321 1322 /* Restore and set windows */ 1323 ddr3_restore_and_set_final_windows(win, ddr_type); 1324 1325 /* Update DRAM init indication in bootROM register */ 1326 reg_val = reg_read(REG_BOOTROM_ROUTINE_ADDR); 1327 reg_write(REG_BOOTROM_ROUTINE_ADDR, 1328 reg_val | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)); 1329 1330 /* DLB config */ 1331 ddr3_new_tip_dlb_config(); 1332 1333 return MV_OK; 1334 } 1335 1336 void mv_ddr_mc_config(void) 1337 { 1338 /* Memory controller initializations */ 1339 struct init_cntr_param init_param; 1340 int status; 1341 1342 init_param.do_mrs_phy = 1; 1343 init_param.is_ctrl64_bit = 0; 1344 init_param.init_phy = 1; 1345 init_param.msys_init = 1; 1346 status = hws_ddr3_tip_init_controller(0, &init_param); 1347 if (status != MV_OK) 1348 printf("DDR3 init controller - FAILED 0x%x\n", status); 1349 1350 status = mv_ddr_mc_init(); 1351 if (status != MV_OK) 1352 printf("DDR3 init_sequence - FAILED 0x%x\n", status); 1353 } 1354 /* function: mv_ddr_mc_init 1355 * this function enables the dunit after init controller configuration 1356 */ 1357 int mv_ddr_mc_init(void) 1358 { 1359 CHECK_STATUS(ddr3_tip_enable_init_sequence(0)); 1360 1361 return MV_OK; 1362 } 1363 1364 /* function: ddr3_tip_configure_phy 1365 * configures phy and electrical parameters 1366 */ 1367 int ddr3_tip_configure_phy(u32 dev_num) 1368 { 1369 u32 if_id, phy_id; 1370 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); 1371 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 1372 1373 CHECK_STATUS(ddr3_tip_bus_write 1374 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1375 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 1376 PAD_ZRI_CAL_PHY_REG, 1377 ((0x7f & g_zpri_data) << 7 | (0x7f & g_znri_data)))); 1378 CHECK_STATUS(ddr3_tip_bus_write 1379 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1380 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL, 1381 PAD_ZRI_CAL_PHY_REG, 1382 ((0x7f & g_zpri_ctrl) << 7 | (0x7f & g_znri_ctrl)))); 1383 CHECK_STATUS(ddr3_tip_bus_write 1384 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1385 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 1386 PAD_ODT_CAL_PHY_REG, 1387 ((0x3f & g_zpodt_data) << 6 | (0x3f & g_znodt_data)))); 1388 CHECK_STATUS(ddr3_tip_bus_write 1389 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1390 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL, 1391 PAD_ODT_CAL_PHY_REG, 1392 ((0x3f & g_zpodt_ctrl) << 6 | (0x3f & g_znodt_ctrl)))); 1393 1394 CHECK_STATUS(ddr3_tip_bus_write 1395 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1396 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 1397 PAD_PRE_DISABLE_PHY_REG, 0)); 1398 CHECK_STATUS(ddr3_tip_bus_write 1399 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1400 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 1401 CMOS_CONFIG_PHY_REG, 0)); 1402 CHECK_STATUS(ddr3_tip_bus_write 1403 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1404 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL, 1405 CMOS_CONFIG_PHY_REG, 0)); 1406 1407 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 1408 /* check if the interface is enabled */ 1409 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 1410 1411 for (phy_id = 0; 1412 phy_id < octets_per_if_num; 1413 phy_id++) { 1414 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); 1415 /* Vref & clamp */ 1416 CHECK_STATUS(ddr3_tip_bus_read_modify_write 1417 (dev_num, ACCESS_TYPE_UNICAST, 1418 if_id, phy_id, DDR_PHY_DATA, 1419 PAD_CFG_PHY_REG, 1420 ((clamp_tbl[if_id] << 4) | vref_init_val), 1421 ((0x7 << 4) | 0x7))); 1422 /* clamp not relevant for control */ 1423 CHECK_STATUS(ddr3_tip_bus_read_modify_write 1424 (dev_num, ACCESS_TYPE_UNICAST, 1425 if_id, phy_id, DDR_PHY_CONTROL, 1426 PAD_CFG_PHY_REG, 0x4, 0x7)); 1427 } 1428 } 1429 1430 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_PHY_EDGE) == 1431 MV_DDR_PHY_EDGE_POSITIVE) 1432 CHECK_STATUS(ddr3_tip_bus_write 1433 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1434 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 1435 DDR_PHY_DATA, 0x90, 0x6002)); 1436 1437 1438 return MV_OK; 1439 } 1440 1441 1442 int mv_ddr_manual_cal_do(void) 1443 { 1444 return 0; 1445 } 1446