1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <asm/fsl_law.h> 11 #include <div64.h> 12 13 #include <fsl_ddr.h> 14 #include <fsl_immap.h> 15 #include <asm/io.h> 16 17 /* To avoid 64-bit full-divides, we factor this here */ 18 #define ULL_2E12 2000000000000ULL 19 #define UL_5POW12 244140625UL 20 #define UL_2POW13 (1UL << 13) 21 22 #define ULL_8FS 0xFFFFFFFFULL 23 24 /* 25 * Round up mclk_ps to nearest 1 ps in memory controller code 26 * if the error is 0.5ps or more. 27 * 28 * If an imprecise data rate is too high due to rounding error 29 * propagation, compute a suitably rounded mclk_ps to compute 30 * a working memory controller configuration. 31 */ 32 unsigned int get_memory_clk_period_ps(void) 33 { 34 unsigned int data_rate = get_ddr_freq(0); 35 unsigned int result; 36 37 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 38 unsigned long long rem, mclk_ps = ULL_2E12; 39 40 /* Now perform the big divide, the result fits in 32-bits */ 41 rem = do_div(mclk_ps, data_rate); 42 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 43 44 return result; 45 } 46 47 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 48 unsigned int picos_to_mclk(unsigned int picos) 49 { 50 unsigned long long clks, clks_rem; 51 unsigned long data_rate = get_ddr_freq(0); 52 53 /* Short circuit for zero picos */ 54 if (!picos) 55 return 0; 56 57 /* First multiply the time by the data rate (32x32 => 64) */ 58 clks = picos * (unsigned long long)data_rate; 59 /* 60 * Now divide by 5^12 and track the 32-bit remainder, then divide 61 * by 2*(2^12) using shifts (and updating the remainder). 62 */ 63 clks_rem = do_div(clks, UL_5POW12); 64 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 65 clks >>= 13; 66 67 /* If we had a remainder greater than the 1ps error, then round up */ 68 if (clks_rem > data_rate) 69 clks++; 70 71 /* Clamp to the maximum representable value */ 72 if (clks > ULL_8FS) 73 clks = ULL_8FS; 74 return (unsigned int) clks; 75 } 76 77 unsigned int mclk_to_picos(unsigned int mclk) 78 { 79 return get_memory_clk_period_ps() * mclk; 80 } 81 82 void 83 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 84 unsigned int law_memctl, 85 unsigned int ctrl_num) 86 { 87 unsigned long long base = memctl_common_params->base_address; 88 unsigned long long size = memctl_common_params->total_mem; 89 90 /* 91 * If no DIMMs on this controller, do not proceed any further. 92 */ 93 if (!memctl_common_params->ndimms_present) { 94 return; 95 } 96 97 #if !defined(CONFIG_PHYS_64BIT) 98 if (base >= CONFIG_MAX_MEM_MAPPED) 99 return; 100 if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 101 size = CONFIG_MAX_MEM_MAPPED - base; 102 #endif 103 if (set_ddr_laws(base, size, law_memctl) < 0) { 104 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 105 law_memctl); 106 return ; 107 } 108 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 109 base, size, law_memctl); 110 } 111 112 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 113 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 114 unsigned int memctl_interleaved, 115 unsigned int ctrl_num); 116 117 void fsl_ddr_set_intl3r(const unsigned int granule_size) 118 { 119 #ifdef CONFIG_E6500 120 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 121 *mcintl3r = 0x80000000 | (granule_size & 0x1f); 122 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 123 #endif 124 } 125 126 u32 fsl_ddr_get_intl3r(void) 127 { 128 u32 val = 0; 129 #ifdef CONFIG_E6500 130 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 131 val = *mcintl3r; 132 #endif 133 return val; 134 } 135 136 void board_add_ram_info(int use_default) 137 { 138 struct ccsr_ddr __iomem *ddr = 139 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 140 141 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 142 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 143 #endif 144 #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 145 uint32_t cs0_config = in_be32(&ddr->cs0_config); 146 #endif 147 uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); 148 int cas_lat; 149 150 #if CONFIG_NUM_DDR_CONTROLLERS >= 2 151 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 152 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 153 sdram_cfg = in_be32(&ddr->sdram_cfg); 154 } 155 #endif 156 #if CONFIG_NUM_DDR_CONTROLLERS >= 3 157 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 158 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 159 sdram_cfg = in_be32(&ddr->sdram_cfg); 160 } 161 #endif 162 puts(" (DDR"); 163 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 164 SDRAM_CFG_SDRAM_TYPE_SHIFT) { 165 case SDRAM_TYPE_DDR1: 166 puts("1"); 167 break; 168 case SDRAM_TYPE_DDR2: 169 puts("2"); 170 break; 171 case SDRAM_TYPE_DDR3: 172 puts("3"); 173 break; 174 default: 175 puts("?"); 176 break; 177 } 178 179 if (sdram_cfg & SDRAM_CFG_32_BE) 180 puts(", 32-bit"); 181 else if (sdram_cfg & SDRAM_CFG_16_BE) 182 puts(", 16-bit"); 183 else 184 puts(", 64-bit"); 185 186 /* Calculate CAS latency based on timing cfg values */ 187 cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; 188 if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) 189 cas_lat += (8 << 1); 190 printf(", CL=%d", cas_lat >> 1); 191 if (cas_lat & 0x1) 192 puts(".5"); 193 194 if (sdram_cfg & SDRAM_CFG_ECC_EN) 195 puts(", ECC on)"); 196 else 197 puts(", ECC off)"); 198 199 #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 200 #ifdef CONFIG_E6500 201 if (*mcintl3r & 0x80000000) { 202 puts("\n"); 203 puts(" DDR Controller Interleaving Mode: "); 204 switch (*mcintl3r & 0x1f) { 205 case FSL_DDR_3WAY_1KB_INTERLEAVING: 206 puts("3-way 1KB"); 207 break; 208 case FSL_DDR_3WAY_4KB_INTERLEAVING: 209 puts("3-way 4KB"); 210 break; 211 case FSL_DDR_3WAY_8KB_INTERLEAVING: 212 puts("3-way 8KB"); 213 break; 214 default: 215 puts("3-way UNKNOWN"); 216 break; 217 } 218 } 219 #endif 220 #endif 221 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 222 if (cs0_config & 0x20000000) { 223 puts("\n"); 224 puts(" DDR Controller Interleaving Mode: "); 225 226 switch ((cs0_config >> 24) & 0xf) { 227 case FSL_DDR_CACHE_LINE_INTERLEAVING: 228 puts("cache line"); 229 break; 230 case FSL_DDR_PAGE_INTERLEAVING: 231 puts("page"); 232 break; 233 case FSL_DDR_BANK_INTERLEAVING: 234 puts("bank"); 235 break; 236 case FSL_DDR_SUPERBANK_INTERLEAVING: 237 puts("super-bank"); 238 break; 239 default: 240 puts("invalid"); 241 break; 242 } 243 } 244 #endif 245 246 if ((sdram_cfg >> 8) & 0x7f) { 247 puts("\n"); 248 puts(" DDR Chip-Select Interleaving Mode: "); 249 switch(sdram_cfg >> 8 & 0x7f) { 250 case FSL_DDR_CS0_CS1_CS2_CS3: 251 puts("CS0+CS1+CS2+CS3"); 252 break; 253 case FSL_DDR_CS0_CS1: 254 puts("CS0+CS1"); 255 break; 256 case FSL_DDR_CS2_CS3: 257 puts("CS2+CS3"); 258 break; 259 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 260 puts("CS0+CS1 and CS2+CS3"); 261 break; 262 default: 263 puts("invalid"); 264 break; 265 } 266 } 267 } 268