1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <stm32_rcc.h> 12 13 #include <asm/io.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/stm32_pwr.h> 16 17 #include <dt-bindings/mfd/stm32f7-rcc.h> 18 19 #define RCC_CR_HSION BIT(0) 20 #define RCC_CR_HSEON BIT(16) 21 #define RCC_CR_HSERDY BIT(17) 22 #define RCC_CR_HSEBYP BIT(18) 23 #define RCC_CR_CSSON BIT(19) 24 #define RCC_CR_PLLON BIT(24) 25 #define RCC_CR_PLLRDY BIT(25) 26 #define RCC_CR_PLLSAION BIT(28) 27 #define RCC_CR_PLLSAIRDY BIT(29) 28 29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) 30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) 31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) 32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) 33 #define RCC_PLLCFGR_PLLSRC BIT(22) 34 #define RCC_PLLCFGR_PLLM_SHIFT 0 35 #define RCC_PLLCFGR_PLLN_SHIFT 6 36 #define RCC_PLLCFGR_PLLP_SHIFT 16 37 #define RCC_PLLCFGR_PLLQ_SHIFT 24 38 39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) 40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) 41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) 42 #define RCC_CFGR_SW0 BIT(0) 43 #define RCC_CFGR_SW1 BIT(1) 44 #define RCC_CFGR_SW_MASK GENMASK(1, 0) 45 #define RCC_CFGR_SW_HSI 0 46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 48 #define RCC_CFGR_SWS0 BIT(2) 49 #define RCC_CFGR_SWS1 BIT(3) 50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2) 51 #define RCC_CFGR_SWS_HSI 0 52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 54 #define RCC_CFGR_HPRE_SHIFT 4 55 #define RCC_CFGR_PPRE1_SHIFT 10 56 #define RCC_CFGR_PPRE2_SHIFT 13 57 58 #define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) 59 #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) 60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 62 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) 63 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) 64 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) 65 66 #define RCC_DCKCFGRX_CK48MSEL BIT(27) 67 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) 68 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) 69 70 #define RCC_APB2ENR_SAI1EN BIT(22) 71 72 /* 73 * RCC AHB1ENR specific definitions 74 */ 75 #define RCC_AHB1ENR_ETHMAC_EN BIT(25) 76 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) 77 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) 78 79 /* 80 * RCC APB1ENR specific definitions 81 */ 82 #define RCC_APB1ENR_TIM2EN BIT(0) 83 #define RCC_APB1ENR_PWREN BIT(28) 84 85 /* 86 * RCC APB2ENR specific definitions 87 */ 88 #define RCC_APB2ENR_SYSCFGEN BIT(14) 89 90 enum periph_clock { 91 SYSCFG_CLOCK_CFG, 92 TIMER2_CLOCK_CFG, 93 }; 94 95 static const struct stm32_clk_info stm32f4_clk_info = { 96 /* 180 MHz */ 97 .sys_pll_psc = { 98 .pll_n = 360, 99 .pll_p = 2, 100 .pll_q = 8, 101 .ahb_psc = AHB_PSC_1, 102 .apb1_psc = APB_PSC_4, 103 .apb2_psc = APB_PSC_2, 104 }, 105 .has_overdrive = false, 106 .v2 = false, 107 }; 108 109 static const struct stm32_clk_info stm32f7_clk_info = { 110 /* 200 MHz */ 111 .sys_pll_psc = { 112 .pll_n = 400, 113 .pll_p = 2, 114 .pll_q = 8, 115 .ahb_psc = AHB_PSC_1, 116 .apb1_psc = APB_PSC_4, 117 .apb2_psc = APB_PSC_2, 118 }, 119 .has_overdrive = true, 120 .v2 = true, 121 }; 122 123 struct stm32_clk { 124 struct stm32_rcc_regs *base; 125 struct stm32_pwr_regs *pwr_regs; 126 struct stm32_clk_info info; 127 unsigned long hse_rate; 128 }; 129 130 static int configure_clocks(struct udevice *dev) 131 { 132 struct stm32_clk *priv = dev_get_priv(dev); 133 struct stm32_rcc_regs *regs = priv->base; 134 struct stm32_pwr_regs *pwr = priv->pwr_regs; 135 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; 136 u32 pllsaicfgr = 0; 137 138 /* Reset RCC configuration */ 139 setbits_le32(®s->cr, RCC_CR_HSION); 140 writel(0, ®s->cfgr); /* Reset CFGR */ 141 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON 142 | RCC_CR_PLLON | RCC_CR_PLLSAION)); 143 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ 144 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 145 writel(0, ®s->cir); /* Disable all interrupts */ 146 147 /* Configure for HSE+PLL operation */ 148 setbits_le32(®s->cr, RCC_CR_HSEON); 149 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 150 ; 151 152 setbits_le32(®s->cfgr, (( 153 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) 154 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) 155 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT))); 156 157 /* Configure the main PLL */ 158 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ 159 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, 160 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); 161 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, 162 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); 163 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, 164 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); 165 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, 166 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); 167 168 /* Configure the SAI PLL to get a 48 MHz source */ 169 pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | 170 RCC_PLLSAICFGR_PLLSAIP_4; 171 pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; 172 writel(pllsaicfgr, ®s->pllsaicfgr); 173 174 /* Enable the main PLL */ 175 setbits_le32(®s->cr, RCC_CR_PLLON); 176 while (!(readl(®s->cr) & RCC_CR_PLLRDY)) 177 ; 178 179 if (priv->info.v2) { /*stm32f7 case */ 180 /* select PLLSAI as 48MHz clock source */ 181 setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); 182 183 /* select 48MHz as SDMMC1 clock source */ 184 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); 185 186 /* select 48MHz as SDMMC2 clock source */ 187 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); 188 } else { /* stm32f4 case */ 189 /* select PLLSAI as 48MHz clock source */ 190 setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); 191 192 /* select 48MHz as SDMMC1 clock source */ 193 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); 194 } 195 196 /* Enable the SAI PLL */ 197 setbits_le32(®s->cr, RCC_CR_PLLSAION); 198 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) 199 ; 200 201 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); 202 203 if (priv->info.has_overdrive) { 204 /* 205 * Enable high performance mode 206 * System frequency up to 200 MHz 207 */ 208 setbits_le32(&pwr->cr1, PWR_CR1_ODEN); 209 /* Infinite wait! */ 210 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) 211 ; 212 /* Enable the Over-drive switch */ 213 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); 214 /* Infinite wait! */ 215 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) 216 ; 217 } 218 219 stm32_flash_latency_cfg(5); 220 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); 221 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); 222 223 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != 224 RCC_CFGR_SWS_PLL) 225 ; 226 /* gate the SAI clock, needed for MMC 1&2 clocks */ 227 setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); 228 229 return 0; 230 } 231 232 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, 233 u32 sysclk) 234 { 235 struct stm32_rcc_regs *regs = priv->base; 236 u16 pllq, pllm, pllsain, pllsaip; 237 bool pllsai; 238 239 pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) 240 >> RCC_PLLCFGR_PLLQ_SHIFT; 241 242 if (priv->info.v2) /*stm32f7 case */ 243 pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; 244 else 245 pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; 246 247 if (pllsai) { 248 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ 249 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 250 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) 251 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); 252 pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) 253 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); 254 return ((priv->hse_rate / pllm) * pllsain) / pllsaip; 255 } 256 /* PLL48CLK is selected from PLLQ */ 257 return sysclk / pllq; 258 } 259 260 static unsigned long stm32_clk_get_rate(struct clk *clk) 261 { 262 struct stm32_clk *priv = dev_get_priv(clk->dev); 263 struct stm32_rcc_regs *regs = priv->base; 264 u32 sysclk = 0; 265 u32 shift = 0; 266 u16 pllm, plln, pllp; 267 /* Prescaler table lookups for clock computation */ 268 u8 ahb_psc_table[16] = { 269 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 270 }; 271 u8 apb_psc_table[8] = { 272 0, 0, 0, 0, 1, 2, 3, 4 273 }; 274 275 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == 276 RCC_CFGR_SWS_PLL) { 277 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 278 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) 279 >> RCC_PLLCFGR_PLLN_SHIFT); 280 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) 281 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); 282 sysclk = ((priv->hse_rate / pllm) * plln) / pllp; 283 } else { 284 return -EINVAL; 285 } 286 287 switch (clk->id) { 288 /* 289 * AHB CLOCK: 3 x 32 bits consecutive registers are used : 290 * AHB1, AHB2 and AHB3 291 */ 292 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): 293 shift = ahb_psc_table[( 294 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) 295 >> RCC_CFGR_HPRE_SHIFT)]; 296 return sysclk >>= shift; 297 /* APB1 CLOCK */ 298 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): 299 shift = apb_psc_table[( 300 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) 301 >> RCC_CFGR_PPRE1_SHIFT)]; 302 return sysclk >>= shift; 303 /* APB2 CLOCK */ 304 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): 305 /* 306 * particular case for SDMMC1 and SDMMC2 : 307 * 48Mhz source clock can be from main PLL or from 308 * SAI PLL 309 */ 310 switch (clk->id) { 311 case STM32F7_APB2_CLOCK(SDMMC1): 312 if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) 313 /* System clock is selected as SDMMC1 clock */ 314 return sysclk; 315 else 316 return stm32_clk_pll48clk_rate(priv, sysclk); 317 break; 318 case STM32F7_APB2_CLOCK(SDMMC2): 319 if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) 320 /* System clock is selected as SDMMC2 clock */ 321 return sysclk; 322 else 323 return stm32_clk_pll48clk_rate(priv, sysclk); 324 break; 325 } 326 327 shift = apb_psc_table[( 328 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) 329 >> RCC_CFGR_PPRE2_SHIFT)]; 330 return sysclk >>= shift; 331 default: 332 pr_err("clock index %ld out of range\n", clk->id); 333 return -EINVAL; 334 } 335 } 336 337 static int stm32_clk_enable(struct clk *clk) 338 { 339 struct stm32_clk *priv = dev_get_priv(clk->dev); 340 struct stm32_rcc_regs *regs = priv->base; 341 u32 offset = clk->id / 32; 342 u32 bit_index = clk->id % 32; 343 344 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", 345 __func__, clk->id, offset, bit_index); 346 setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); 347 348 return 0; 349 } 350 351 void clock_setup(int peripheral) 352 { 353 switch (peripheral) { 354 case SYSCFG_CLOCK_CFG: 355 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); 356 break; 357 case TIMER2_CLOCK_CFG: 358 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); 359 break; 360 default: 361 break; 362 } 363 } 364 365 static int stm32_clk_probe(struct udevice *dev) 366 { 367 struct ofnode_phandle_args args; 368 struct udevice *fixed_clock_dev = NULL; 369 struct clk clk; 370 int err; 371 372 debug("%s\n", __func__); 373 374 struct stm32_clk *priv = dev_get_priv(dev); 375 fdt_addr_t addr; 376 377 addr = dev_read_addr(dev); 378 if (addr == FDT_ADDR_T_NONE) 379 return -EINVAL; 380 381 priv->base = (struct stm32_rcc_regs *)addr; 382 383 switch (dev_get_driver_data(dev)) { 384 case STM32F4: 385 memcpy(&priv->info, &stm32f4_clk_info, 386 sizeof(struct stm32_clk_info)); 387 break; 388 case STM32F7: 389 memcpy(&priv->info, &stm32f7_clk_info, 390 sizeof(struct stm32_clk_info)); 391 break; 392 default: 393 return -EINVAL; 394 } 395 396 /* retrieve HSE frequency (external oscillator) */ 397 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse", 398 &fixed_clock_dev); 399 400 if (err) { 401 pr_err("Can't find fixed clock (%d)", err); 402 return err; 403 } 404 405 err = clk_request(fixed_clock_dev, &clk); 406 if (err) { 407 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name, 408 err); 409 return err; 410 } 411 412 /* 413 * set pllm factor accordingly to the external oscillator 414 * frequency (HSE). For STM32F4 and STM32F7, we want VCO 415 * freq at 1MHz 416 * if input PLL frequency is 25Mhz, divide it by 25 417 */ 418 clk.id = 0; 419 priv->hse_rate = clk_get_rate(&clk); 420 421 if (priv->hse_rate < 1000000) { 422 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__, 423 priv->hse_rate); 424 return -EINVAL; 425 } 426 427 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000; 428 429 if (priv->info.has_overdrive) { 430 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, 431 &args); 432 if (err) { 433 debug("%s: can't find syscon device (%d)\n", __func__, 434 err); 435 return err; 436 } 437 438 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); 439 } 440 441 configure_clocks(dev); 442 443 return 0; 444 } 445 446 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) 447 { 448 debug("%s(clk=%p)\n", __func__, clk); 449 450 if (args->args_count != 2) { 451 debug("Invaild args_count: %d\n", args->args_count); 452 return -EINVAL; 453 } 454 455 if (args->args_count) 456 clk->id = args->args[1]; 457 else 458 clk->id = 0; 459 460 return 0; 461 } 462 463 static struct clk_ops stm32_clk_ops = { 464 .of_xlate = stm32_clk_of_xlate, 465 .enable = stm32_clk_enable, 466 .get_rate = stm32_clk_get_rate, 467 }; 468 469 U_BOOT_DRIVER(stm32fx_clk) = { 470 .name = "stm32fx_rcc_clock", 471 .id = UCLASS_CLK, 472 .ops = &stm32_clk_ops, 473 .probe = stm32_clk_probe, 474 .priv_auto_alloc_size = sizeof(struct stm32_clk), 475 .flags = DM_FLAG_PRE_RELOC, 476 }; 477