xref: /openbmc/u-boot/drivers/clk/aspeed/clk_ast2600.c (revision e9f7e664bae796a7b5b9bb2b1e079ae598a1215b)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * Copyright (C) ASPEED Technology Inc.
4   */
5  
6  #include <common.h>
7  #include <linux/bitfield.h>
8  #include <linux/bitops.h>
9  #include <linux/iopoll.h>
10  #include <clk-uclass.h>
11  #include <dm.h>
12  #include <asm/io.h>
13  #include <dm/lists.h>
14  #include <asm/arch/scu_ast2600.h>
15  #include <dt-bindings/clock/ast2600-clock.h>
16  #include <dt-bindings/reset/ast2600-reset.h>
17  
18  /*
19   * SCU 80 & 90 clock stop control for MAC controllers
20   */
21  #define SCU_CLKSTOP_MAC1			(20)
22  #define SCU_CLKSTOP_MAC2			(21)
23  #define SCU_CLKSTOP_MAC3			(20)
24  #define SCU_CLKSTOP_MAC4			(21)
25  
26  /*
27   * MAC Clock Delay settings
28   */
29  #define MAC_CLK_RGMII_125M_SRC_SEL		BIT(31)
30  #define   MAC_CLK_RGMII_125M_SRC_PAD_RGMIICK	0
31  #define   MAC_CLK_RGMII_125M_SRC_PLL		1
32  #define MAC_CLK_RMII2_50M_RCLK_O_CTRL		BIT(30)
33  #define   MAC_CLK_RMII2_50M_RCLK_O_DIS		0
34  #define   MAC_CLK_RMII2_50M_RCLK_O_EN		1
35  #define MAC_CLK_RMII1_50M_RCLK_O_CTRL		BIT(29)
36  #define   MAC_CLK_RMII1_5M_RCLK_O_DIS		0
37  #define   MAC_CLK_RMII1_5M_RCLK_O_EN		1
38  #define MAC_CLK_RGMIICK_PAD_DIR			BIT(28)
39  #define   MAC_CLK_RGMIICK_PAD_DIR_INPUT		0
40  #define   MAC_CLK_RGMIICK_PAD_DIR_OUTPUT	1
41  #define MAC_CLK_RMII_TXD_FALLING_2		BIT(27)
42  #define MAC_CLK_RMII_TXD_FALLING_1		BIT(26)
43  #define MAC_CLK_RXCLK_INV_2			BIT(25)
44  #define MAC_CLK_RXCLK_INV_1			BIT(24)
45  #define MAC_CLK_1G_INPUT_DELAY_2		GENMASK(23, 18)
46  #define MAC_CLK_1G_INPUT_DELAY_1		GENMASK(17, 12)
47  #define MAC_CLK_1G_OUTPUT_DELAY_2		GENMASK(11, 6)
48  #define MAC_CLK_1G_OUTPUT_DELAY_1		GENMASK(5, 0)
49  
50  #define MAC_CLK_100M_10M_RESERVED		GENMASK(31, 26)
51  #define MAC_CLK_100M_10M_RXCLK_INV_2		BIT(25)
52  #define MAC_CLK_100M_10M_RXCLK_INV_1		BIT(24)
53  #define MAC_CLK_100M_10M_INPUT_DELAY_2		GENMASK(23, 18)
54  #define MAC_CLK_100M_10M_INPUT_DELAY_1		GENMASK(17, 12)
55  #define MAC_CLK_100M_10M_OUTPUT_DELAY_2		GENMASK(11, 6)
56  #define MAC_CLK_100M_10M_OUTPUT_DELAY_1		GENMASK(5, 0)
57  
58  #define RGMII12_CLK_OUTPUT_DELAY_PS		1000
59  #define RGMII34_CLK_OUTPUT_DELAY_PS		1600
60  
61  #define MAC_DEF_DELAY_1G			FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 16) |        \
62  						FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 10) |         \
63  						FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 16) |        \
64  						FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 10)
65  #define MAC_DEF_DELAY_100M			FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) |  \
66  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) |   \
67  						FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) |  \
68  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16)
69  #define MAC_DEF_DELAY_10M			FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) |  \
70  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) |   \
71  						FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) |  \
72  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16)
73  #define MAC34_DEF_DELAY_1G			FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 8) |         \
74  						FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 4) |          \
75  						FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 8) |         \
76  						FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 4)
77  #define MAC34_DEF_DELAY_100M			FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) |   \
78  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) |    \
79  						FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) |   \
80  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4)
81  #define MAC34_DEF_DELAY_10M			FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) |   \
82  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) |    \
83  						FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) |   \
84  						FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4)
85  
86  /*
87   * SCU 320 & 330 Frequency counters
88   */
89  #define FREQC_CTRL_RESERVED			GENMASK(31, 30)
90  #define FREQC_CTRL_RESULT			GENMASK(29, 16)
91  #define FREQC_CTRL_RING_STAGE			GENMASK(15, 9)
92  #define FREQC_CTRL_PIN_O_CTRL			BIT(8)
93  #define   FREQC_CTRL_PIN_O_DIS			0
94  #define   FREQC_CTRL_PIN_O_EN			1
95  #define FREQC_CTRL_CMP_RESULT			BIT(7)
96  #define   FREQC_CTRL_CMP_RESULT_FAIL		0
97  #define   FREQC_CTRL_CMP_RESULT_PASS		1
98  #define FREQC_CTRL_STATUS			BIT(6)
99  #define   FREQC_CTRL_STATUS_NOT_FINISHED	0
100  #define   FREQC_CTRL_STATUS_FINISHED		1
101  #define FREQC_CTRL_SRC_SEL			GENMASK(5, 2)
102  #define   FREQC_CTRL_SRC_SEL_HCLK_DIE0		9
103  #define   FREQC_CTRL_SRC_SEL_DLY32_DIE0		3
104  #define   FREQC_CTRL_SRC_SEL_HCLK_DIE1		1
105  #define   FREQC_CTRL_SRC_SEL_DLY32_DIE1		7
106  #define FREQC_CTRL_OSC_CTRL			BIT(1)
107  #define   FREQC_CTRL_OSC_DIS			0
108  #define   FREQC_CTRL_OSC_EN			1
109  #define FREQC_CTRL_RING_CTRL			BIT(0)
110  #define   FREQC_CTRL_RING_DIS			0
111  #define   FREQC_CTRL_RING_EN			1
112  
113  #define FREQC_RANGE_RESERVED0			GENMASK(31, 30)
114  #define FREQC_RANGE_LOWER			GENMASK(29, 16)
115  #define FREQC_RANGE_RESERVED1			GENMASK(15, 14)
116  #define FREQC_RANGE_UPPER			GENMASK(13, 0)
117  
118  #define DLY32_NUM_OF_TAPS			32
119  #define DLY32_AVERAGE_COUNT_LOG2		4
120  #define DLY32_AVERAGE_COUNT			BIT(DLY32_AVERAGE_COUNT_LOG2)
121  
122  /*
123   * TGMII Clock Duty constants, taken from Aspeed SDK
124   */
125  #define RGMII2_TXCK_DUTY		0x66
126  #define RGMII1_TXCK_DUTY		0x64
127  #define D2PLL_DEFAULT_RATE		(250 * 1000 * 1000)
128  #define CHIP_REVISION_ID		GENMASK(23, 16)
129  
130  DECLARE_GLOBAL_DATA_PTR;
131  
132  /*
133   * Clock divider/multiplier configuration struct.
134   * For H-PLL and M-PLL the formula is
135   * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
136   * M - Numerator
137   * N - Denumerator
138   * P - Post Divider
139   * They have the same layout in their control register.
140   *
141   * D-PLL and D2-PLL have extra divider (OD + 1), which is not
142   * yet needed and ignored by clock configurations.
143   */
144  union ast2600_pll_reg {
145  	u32 w;
146  	struct {
147  		unsigned int m : 13;		/* bit[12:0]	*/
148  		unsigned int n : 6;		/* bit[18:13]	*/
149  		unsigned int p : 4;		/* bit[22:19]	*/
150  		unsigned int off : 1;		/* bit[23]	*/
151  		unsigned int bypass : 1;	/* bit[24]	*/
152  		unsigned int reset : 1;		/* bit[25]	*/
153  		unsigned int reserved : 6;	/* bit[31:26]	*/
154  	} b;
155  };
156  
157  struct ast2600_pll_cfg {
158  	union ast2600_pll_reg reg;
159  	u32 ext_reg;
160  };
161  
162  struct ast2600_pll_desc {
163  	u32 in;
164  	u32 out;
165  	struct ast2600_pll_cfg cfg;
166  };
167  
168  static const struct ast2600_pll_desc ast2600_pll_lookup[] = {
169  	{
170  		.in = AST2600_CLK_IN,
171  		.out = 400000000,
172  		.cfg.reg.b.m = 95,
173  		.cfg.reg.b.n = 2,
174  		.cfg.reg.b.p = 1,
175  		.cfg.ext_reg = 0x31,
176  	}, {
177  		.in = AST2600_CLK_IN,
178  		.out = 200000000,
179  		.cfg.reg.b.m = 127,
180  		.cfg.reg.b.n = 0,
181  		.cfg.reg.b.p = 15,
182  		.cfg.ext_reg = 0x3f,
183  	}, {
184  		.in = AST2600_CLK_IN,
185  		.out = 334000000,
186  		.cfg.reg.b.m = 667,
187  		.cfg.reg.b.n = 4,
188  		.cfg.reg.b.p = 9,
189  		.cfg.ext_reg = 0x14d,
190  	}, {
191  		.in = AST2600_CLK_IN,
192  		.out = 1000000000,
193  		.cfg.reg.b.m = 119,
194  		.cfg.reg.b.n = 2,
195  		.cfg.reg.b.p = 0,
196  		.cfg.ext_reg = 0x3d,
197  	}, {
198  		.in = AST2600_CLK_IN,
199  		.out = 50000000,
200  		.cfg.reg.b.m = 95,
201  		.cfg.reg.b.n = 2,
202  		.cfg.reg.b.p = 15,
203  		.cfg.ext_reg = 0x31,
204  	},
205  };
206  
207  struct mac_delay_config {
208  	u32 tx_delay_1000;
209  	u32 rx_delay_1000;
210  	u32 tx_delay_100;
211  	u32 rx_delay_100;
212  	u32 tx_delay_10;
213  	u32 rx_delay_10;
214  };
215  
ast2600_get_pll_rate(struct ast2600_scu * scu,int pll_idx)216  extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx)
217  {
218  	u32 clkin = AST2600_CLK_IN;
219  	u32 pll_reg = 0;
220  	unsigned int mult, div = 1;
221  
222  	switch (pll_idx) {
223  	case ASPEED_CLK_HPLL:
224  		pll_reg = readl(&scu->h_pll_param);
225  		break;
226  	case ASPEED_CLK_MPLL:
227  		pll_reg = readl(&scu->m_pll_param);
228  		break;
229  	case ASPEED_CLK_DPLL:
230  		pll_reg = readl(&scu->d_pll_param);
231  		break;
232  	case ASPEED_CLK_EPLL:
233  		pll_reg = readl(&scu->e_pll_param);
234  		break;
235  	}
236  	if (pll_reg & BIT(24)) {
237  		/* Pass through mode */
238  		mult = 1;
239  		div = 1;
240  	} else {
241  		union ast2600_pll_reg reg;
242  		/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)
243  		 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1
244  		 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1
245  		 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0
246  		 * HPLL Denumerator (N) =	SCU200[18:13] (default 0x2)
247  		 * HPLL Divider (P)	 =	SCU200[22:19] (default 0x0)
248  		 * HPLL Bandwidth Adj (NB) =  fix 0x2F when SCU500[10]=1
249  		 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1
250  		 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0
251  		 */
252  		reg.w = pll_reg;
253  		if (pll_idx == ASPEED_CLK_HPLL) {
254  			u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap);
255  
256  			if (hwstrap1 & BIT(10)) {
257  				reg.b.m = 0x5F;
258  			} else {
259  				if (hwstrap1 & BIT(8))
260  					reg.b.m = 0xBF;
261  				/* Otherwise keep default 0x8F */
262  			}
263  		}
264  		mult = (reg.b.m + 1) / (reg.b.n + 1);
265  		div = (reg.b.p + 1);
266  	}
267  
268  	return ((clkin * mult) / div);
269  }
270  
ast2600_get_apll_rate(struct ast2600_scu * scu)271  extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu)
272  {
273  	u32 hw_rev = readl(&scu->chip_id1);
274  	u32 clkin = AST2600_CLK_IN;
275  	u32 apll_reg = readl(&scu->a_pll_param);
276  	unsigned int mult, div = 1;
277  
278  	if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) {
279  		//after A2 version
280  		if (apll_reg & BIT(24)) {
281  			/* Pass through mode */
282  			mult = 1;
283  			div = 1;
284  		} else {
285  			/* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
286  			u32 m = apll_reg & 0x1fff;
287  			u32 n = (apll_reg >> 13) & 0x3f;
288  			u32 p = (apll_reg >> 19) & 0xf;
289  
290  			mult = (m + 1);
291  			div = (n + 1) * (p + 1);
292  		}
293  	} else {
294  		if (apll_reg & BIT(20)) {
295  			/* Pass through mode */
296  			mult = 1;
297  			div = 1;
298  		} else {
299  			/* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
300  			u32 m = (apll_reg >> 5) & 0x3f;
301  			u32 od = (apll_reg >> 4) & 0x1;
302  			u32 n = apll_reg & 0xf;
303  
304  			mult = (2 - od) * (m + 2);
305  			div = n + 1;
306  		}
307  	}
308  
309  	return ((clkin * mult) / div);
310  }
311  
312  static u32 ast2600_a0_axi_ahb_div_table[] = {
313  	2,
314  	2,
315  	3,
316  	4,
317  };
318  
319  static u32 ast2600_a1_axi_ahb_div0_table[] = {
320  	3,
321  	2,
322  	3,
323  	4,
324  };
325  
326  static u32 ast2600_a1_axi_ahb_div1_table[] = {
327  	3,
328  	4,
329  	6,
330  	8,
331  };
332  
333  static u32 ast2600_a1_axi_ahb_default_table[] = {
334  	3, 4, 3, 4, 2, 2, 2, 2,
335  };
336  
ast2600_get_hclk(struct ast2600_scu * scu)337  static u32 ast2600_get_hclk(struct ast2600_scu *scu)
338  {
339  	u32 hw_rev = readl(&scu->chip_id1);
340  	u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap);
341  	u32 axi_div = 1;
342  	u32 ahb_div = 0;
343  	u32 rate = 0;
344  
345  	if ((hw_rev & CHIP_REVISION_ID) >> 16) {
346  		//After A0
347  		if (hwstrap1 & BIT(16)) {
348  			ast2600_a1_axi_ahb_div1_table[0] =
349  				ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) &
350  								 0x7] * 2;
351  			axi_div = 1;
352  			ahb_div =
353  				ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) &
354  							      0x3];
355  		} else {
356  			ast2600_a1_axi_ahb_div0_table[0] =
357  				ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) &
358  								 0x7];
359  			axi_div = 2;
360  			ahb_div =
361  				ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) &
362  							      0x3];
363  		}
364  	} else {
365  		//A0 : fix axi = hpll / 2
366  		axi_div = 2;
367  		ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3];
368  	}
369  	rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
370  
371  	return (rate / axi_div / ahb_div);
372  }
373  
ast2600_get_bclk_rate(struct ast2600_scu * scu)374  static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu)
375  {
376  	u32 rate;
377  	u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7;
378  
379  	rate = ast2600_get_pll_rate(scu, ASPEED_CLK_EPLL);
380  
381  	return (rate / ((bclk_sel + 1) * 4));
382  }
383  
384  static u32 ast2600_hpll_pclk1_div_table[] = {
385  	4, 8, 12, 16, 20, 24, 28, 32,
386  };
387  
388  static u32 ast2600_hpll_pclk2_div_table[] = {
389  	2, 4, 6, 8, 10, 12, 14, 16,
390  };
391  
ast2600_get_pclk1(struct ast2600_scu * scu)392  static u32 ast2600_get_pclk1(struct ast2600_scu *scu)
393  {
394  	u32 clk_sel1 = readl(&scu->clk_sel1);
395  	u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)];
396  	u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
397  
398  	return (rate / apb_div);
399  }
400  
ast2600_get_pclk2(struct ast2600_scu * scu)401  static u32 ast2600_get_pclk2(struct ast2600_scu *scu)
402  {
403  	u32 clk_sel4 = readl(&scu->clk_sel4);
404  	u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)];
405  	u32 rate = ast2600_get_hclk(scu);
406  
407  	return (rate / apb_div);
408  }
409  
ast2600_get_uxclk_in_rate(struct ast2600_scu * scu)410  static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu)
411  {
412  	u32 clk_in = 0;
413  	u32 uxclk_sel = readl(&scu->clk_sel5);
414  
415  	uxclk_sel &= 0x3;
416  	switch (uxclk_sel) {
417  	case 0:
418  		clk_in = ast2600_get_apll_rate(scu) / 4;
419  		break;
420  	case 1:
421  		clk_in = ast2600_get_apll_rate(scu) / 2;
422  		break;
423  	case 2:
424  		clk_in = ast2600_get_apll_rate(scu);
425  		break;
426  	case 3:
427  		clk_in = ast2600_get_hclk(scu);
428  		break;
429  	}
430  
431  	return clk_in;
432  }
433  
ast2600_get_huxclk_in_rate(struct ast2600_scu * scu)434  static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu)
435  {
436  	u32 clk_in = 0;
437  	u32 huclk_sel = readl(&scu->clk_sel5);
438  
439  	huclk_sel = ((huclk_sel >> 3) & 0x3);
440  	switch (huclk_sel) {
441  	case 0:
442  		clk_in = ast2600_get_apll_rate(scu) / 4;
443  		break;
444  	case 1:
445  		clk_in = ast2600_get_apll_rate(scu) / 2;
446  		break;
447  	case 2:
448  		clk_in = ast2600_get_apll_rate(scu);
449  		break;
450  	case 3:
451  		clk_in = ast2600_get_hclk(scu);
452  		break;
453  	}
454  
455  	return clk_in;
456  }
457  
ast2600_get_uart_uxclk_rate(struct ast2600_scu * scu)458  static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu)
459  {
460  	u32 clk_in = ast2600_get_uxclk_in_rate(scu);
461  	u32 div_reg = readl(&scu->uart_24m_ref_uxclk);
462  	unsigned int mult, div;
463  
464  	u32 n = (div_reg >> 8) & 0x3ff;
465  	u32 r = div_reg & 0xff;
466  
467  	mult = r;
468  	div = (n * 2);
469  	return (clk_in * mult) / div;
470  }
471  
ast2600_get_uart_huxclk_rate(struct ast2600_scu * scu)472  static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu)
473  {
474  	u32 clk_in = ast2600_get_huxclk_in_rate(scu);
475  	u32 div_reg = readl(&scu->uart_24m_ref_huxclk);
476  
477  	unsigned int mult, div;
478  
479  	u32 n = (div_reg >> 8) & 0x3ff;
480  	u32 r = div_reg & 0xff;
481  
482  	mult = r;
483  	div = (n * 2);
484  	return (clk_in * mult) / div;
485  }
486  
ast2600_get_sdio_clk_rate(struct ast2600_scu * scu)487  static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu)
488  {
489  	u32 clkin = 0;
490  	u32 clk_sel = readl(&scu->clk_sel4);
491  	u32 div = (clk_sel >> 28) & 0x7;
492  	u32 hw_rev = readl(&scu->chip_id1);
493  
494  	if (clk_sel & BIT(8))
495  		clkin = ast2600_get_apll_rate(scu);
496  	else
497  		clkin = ast2600_get_hclk(scu);
498  
499  	div = (1 + div) * 2;
500  	if (((hw_rev & GENMASK(23, 16)) >> 16) >= 2)
501  		div = (div & 0xf) ? div : 1;
502  
503  	return (clkin / div);
504  }
505  
ast2600_get_emmc_clk_rate(struct ast2600_scu * scu)506  static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu)
507  {
508  	u32 mmc_clk_src = readl(&scu->clk_sel1);
509  	u32 clkin;
510  	u32 clk_sel = readl(&scu->clk_sel1);
511  	u32 div = (clk_sel >> 12) & 0x7;
512  
513  	if (mmc_clk_src & BIT(11)) {
514  		/* emmc clock comes from MPLL */
515  		clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
516  		div = (div + 1) * 2;
517  	} else {
518  		clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
519  		div = (div + 1) << 2;
520  	}
521  
522  	return (clkin / div);
523  }
524  
525  #ifdef CONFIG_SPL_BUILD
ast2600_enable_uart_pinmux(struct ast2600_scu * scu,int uart_idx)526  static void ast2600_enable_uart_pinmux(struct ast2600_scu *scu, int uart_idx)
527  {
528  	switch(uart_idx) {
529  	case 1:
530  		scu->pinmux_ctrl7 |= (BIT(7) | BIT(6));
531  		break;
532  	case 2:
533  		scu->pinmux_ctrl7 |= (BIT(14) | BIT(15));
534  		break;
535  	case 3:
536  		scu->pinmux_ctrl6 |= (BIT(28) | BIT(29));
537  		break;
538  	case 4:
539  		scu->pinmux_ctrl4 |= (BIT(14) | BIT(15));
540  		break;
541  	case 5:
542  		/* do nothgin */
543  		break;
544  	case 6:
545  		scu->pinmux_ctrl5 |= (BIT(16) | BIT(17));
546  		break;
547  	case 7:
548  		scu->pinmux_ctrl5 |= (BIT(18) | BIT(19));
549  		break;
550  	case 8:
551  		scu->pinmux_ctrl5 |= (BIT(20) | BIT(21));
552  		break;
553  	case 9:
554  		scu->pinmux_ctrl5 |= (BIT(22) | BIT(23));
555  		break;
556  	case 10:
557  		scu->pinmux_ctrl8 |= (BIT(20) | BIT(21));
558  		break;
559  	case 11:
560  		scu->pinmux_ctrl8 |= (BIT(22) | BIT(23));
561  		break;
562  	case 12:
563  		scu->pinmux_ctrl19 |= (BIT(0) | BIT(1));
564  		scu->pinmux_ctrl6 &= ~(BIT(0) | BIT(1));
565  		break;
566  	case 13:
567  		scu->pinmux_ctrl19 |= (BIT(2) | BIT(3));
568  		scu->pinmux_ctrl6 &= ~(BIT(2) | BIT(3));
569  		break;
570  	default:
571  		break;
572  	}
573  }
574  #endif
575  
ast2600_get_uart_clk_rate(struct ast2600_scu * scu,int uart_idx)576  static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx)
577  {
578  	u32 hicr9 = readl(0x1e789098);
579  	u32 uart_sel = readl(&scu->clk_sel4);
580  	u32 uart_sel5 = readl(&scu->clk_sel5);
581  	ulong uart_clk = 0;
582  
583  #ifdef CONFIG_SPL_BUILD
584  	ast2600_enable_uart_pinmux(scu, uart_idx);
585  #endif
586  
587  	switch (uart_idx) {
588  	case 1:
589  	case 2:
590  	case 3:
591  	case 4:
592  		hicr9 &= ~(BIT(uart_idx + 3));
593  		writel(hicr9, 0x1e789098);
594  	case 6:
595  		if (uart_sel & BIT(uart_idx - 1))
596  			uart_clk = ast2600_get_uart_huxclk_rate(scu);
597  		else
598  			uart_clk = ast2600_get_uart_uxclk_rate(scu);
599  		break;
600  	case 5: //24mhz is come form usb phy 48Mhz
601  	{
602  		u8 uart5_clk_sel = 0;
603  		//high bit
604  		if (readl(&scu->misc_ctrl1) & BIT(12))
605  			uart5_clk_sel = 0x2;
606  		else
607  			uart5_clk_sel = 0x0;
608  
609  		if (readl(&scu->clk_sel2) & BIT(14))
610  			uart5_clk_sel |= 0x1;
611  
612  		switch (uart5_clk_sel) {
613  		case 0:
614  			uart_clk = 24000000;
615  			break;
616  		case 1:
617  			uart_clk = 192000000;
618  			break;
619  		case 2:
620  			uart_clk = 24000000 / 13;
621  			break;
622  		case 3:
623  			uart_clk = 192000000 / 13;
624  			break;
625  		}
626  	} break;
627  	case 7:
628  	case 8:
629  	case 9:
630  	case 10:
631  	case 11:
632  	case 12:
633  	case 13:
634  		if (uart_sel5 & BIT(uart_idx - 1))
635  			uart_clk = ast2600_get_uart_huxclk_rate(scu);
636  		else
637  			uart_clk = ast2600_get_uart_uxclk_rate(scu);
638  		break;
639  	}
640  
641  	return uart_clk;
642  }
643  
ast2600_clk_get_rate(struct clk * clk)644  static ulong ast2600_clk_get_rate(struct clk *clk)
645  {
646  	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
647  	ulong rate = 0;
648  
649  	switch (clk->id) {
650  	case ASPEED_CLK_HPLL:
651  	case ASPEED_CLK_EPLL:
652  	case ASPEED_CLK_DPLL:
653  	case ASPEED_CLK_MPLL:
654  		rate = ast2600_get_pll_rate(priv->scu, clk->id);
655  		break;
656  	case ASPEED_CLK_AHB:
657  		rate = ast2600_get_hclk(priv->scu);
658  		break;
659  	case ASPEED_CLK_APB1:
660  		rate = ast2600_get_pclk1(priv->scu);
661  		break;
662  	case ASPEED_CLK_APB2:
663  		rate = ast2600_get_pclk2(priv->scu);
664  		break;
665  	case ASPEED_CLK_APLL:
666  		rate = ast2600_get_apll_rate(priv->scu);
667  		break;
668  	case ASPEED_CLK_GATE_UART1CLK:
669  		rate = ast2600_get_uart_clk_rate(priv->scu, 1);
670  		break;
671  	case ASPEED_CLK_GATE_UART2CLK:
672  		rate = ast2600_get_uart_clk_rate(priv->scu, 2);
673  		break;
674  	case ASPEED_CLK_GATE_UART3CLK:
675  		rate = ast2600_get_uart_clk_rate(priv->scu, 3);
676  		break;
677  	case ASPEED_CLK_GATE_UART4CLK:
678  		rate = ast2600_get_uart_clk_rate(priv->scu, 4);
679  		break;
680  	case ASPEED_CLK_GATE_UART5CLK:
681  		rate = ast2600_get_uart_clk_rate(priv->scu, 5);
682  		break;
683  	case ASPEED_CLK_BCLK:
684  		rate = ast2600_get_bclk_rate(priv->scu);
685  		break;
686  	case ASPEED_CLK_SDIO:
687  		rate = ast2600_get_sdio_clk_rate(priv->scu);
688  		break;
689  	case ASPEED_CLK_EMMC:
690  		rate = ast2600_get_emmc_clk_rate(priv->scu);
691  		break;
692  	case ASPEED_CLK_UARTX:
693  		rate = ast2600_get_uart_uxclk_rate(priv->scu);
694  		break;
695  	case ASPEED_CLK_HUARTX:
696  		rate = ast2600_get_uart_huxclk_rate(priv->scu);
697  		break;
698  	default:
699  		pr_debug("can't get clk rate\n");
700  		return -ENOENT;
701  	}
702  
703  	return rate;
704  }
705  
706  /**
707   * @brief	lookup PLL divider config by input/output rate
708   * @param[in]	*pll - PLL descriptor
709   * @return	true - if PLL divider config is found, false - else
710   * The function caller shall fill "pll->in" and "pll->out",
711   * then this function will search the lookup table
712   * to find a valid PLL divider configuration.
713   */
ast2600_search_clock_config(struct ast2600_pll_desc * pll)714  static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll)
715  {
716  	u32 i;
717  	bool is_found = false;
718  
719  	for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) {
720  		const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i];
721  
722  		if (def_cfg->in == pll->in && def_cfg->out == pll->out) {
723  			is_found = true;
724  			pll->cfg.reg.w = def_cfg->cfg.reg.w;
725  			pll->cfg.ext_reg = def_cfg->cfg.ext_reg;
726  			break;
727  		}
728  	}
729  	return is_found;
730  }
731  
ast2600_configure_pll(struct ast2600_scu * scu,struct ast2600_pll_cfg * p_cfg,int pll_idx)732  static u32 ast2600_configure_pll(struct ast2600_scu *scu,
733  				 struct ast2600_pll_cfg *p_cfg, int pll_idx)
734  {
735  	u32 addr, addr_ext;
736  	u32 reg;
737  
738  	switch (pll_idx) {
739  	case ASPEED_CLK_HPLL:
740  		addr = (u32)(&scu->h_pll_param);
741  		addr_ext = (u32)(&scu->h_pll_ext_param);
742  		break;
743  	case ASPEED_CLK_MPLL:
744  		addr = (u32)(&scu->m_pll_param);
745  		addr_ext = (u32)(&scu->m_pll_ext_param);
746  		break;
747  	case ASPEED_CLK_DPLL:
748  		addr = (u32)(&scu->d_pll_param);
749  		addr_ext = (u32)(&scu->d_pll_ext_param);
750  		break;
751  	case ASPEED_CLK_EPLL:
752  		addr = (u32)(&scu->e_pll_param);
753  		addr_ext = (u32)(&scu->e_pll_ext_param);
754  		break;
755  	default:
756  		debug("unknown PLL index\n");
757  		return 1;
758  	}
759  
760  	p_cfg->reg.b.bypass = 0;
761  	p_cfg->reg.b.off = 0;
762  	p_cfg->reg.b.reset = 1;
763  
764  	reg = readl(addr);
765  	reg &= ~GENMASK(25, 0);
766  	reg |= p_cfg->reg.w;
767  	writel(reg, addr);
768  
769  	/* write extend parameter */
770  	writel(p_cfg->ext_reg, addr_ext);
771  	udelay(100);
772  	p_cfg->reg.b.off = 0;
773  	p_cfg->reg.b.reset = 0;
774  	reg &= ~GENMASK(25, 0);
775  	reg |= p_cfg->reg.w;
776  	writel(reg, addr);
777  	while (!(readl(addr_ext) & BIT(31)))
778  		;
779  
780  	return 0;
781  }
782  
ast2600_configure_ddr(struct ast2600_scu * scu,ulong rate)783  static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)
784  {
785  	struct ast2600_pll_desc mpll;
786  
787  	mpll.in = AST2600_CLK_IN;
788  	mpll.out = rate;
789  	if (ast2600_search_clock_config(&mpll) == false) {
790  		printf("error!! unable to find valid DDR clock setting\n");
791  		return 0;
792  	}
793  	ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL);
794  
795  	return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
796  }
797  
ast2600_clk_set_rate(struct clk * clk,ulong rate)798  static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)
799  {
800  	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
801  	ulong new_rate;
802  
803  	switch (clk->id) {
804  	case ASPEED_CLK_MPLL:
805  		new_rate = ast2600_configure_ddr(priv->scu, rate);
806  		break;
807  	default:
808  		return -ENOENT;
809  	}
810  
811  	return new_rate;
812  }
813  
ast2600_calc_dly32_time(struct ast2600_scu * scu,int die_id,int stage)814  static int ast2600_calc_dly32_time(struct ast2600_scu *scu, int die_id, int stage)
815  {
816  	int ret, i;
817  	u64 sum = 0;
818  	u32 base, value, reset_sel, dly32_sel;
819  
820  	if (die_id) {
821  		base = (u32)&scu->freq_counter_ctrl2;
822  		reset_sel = FREQC_CTRL_SRC_SEL_HCLK_DIE1;
823  		dly32_sel = FREQC_CTRL_SRC_SEL_DLY32_DIE1;
824  	} else {
825  		base = (u32)&scu->freq_counter_ctrl1;
826  		reset_sel = FREQC_CTRL_SRC_SEL_HCLK_DIE0;
827  		dly32_sel = FREQC_CTRL_SRC_SEL_DLY32_DIE0;
828  	}
829  
830  	for (i = 0; i < DLY32_AVERAGE_COUNT; i++) {
831  		/* reset frequency-counter */
832  		writel(FIELD_PREP(FREQC_CTRL_SRC_SEL, reset_sel), base);
833  		ret = readl_poll_timeout(base, value, !(value & FREQC_CTRL_RESULT), 1000);
834  		if (ret)
835  			return -1;
836  
837  		/* start frequency counter */
838  		value = FIELD_PREP(FREQC_CTRL_RING_STAGE, stage)
839  		      | FIELD_PREP(FREQC_CTRL_SRC_SEL, dly32_sel)
840  		      | FIELD_PREP(FREQC_CTRL_RING_CTRL, FREQC_CTRL_RING_EN);
841  		writel(value, base);
842  
843  		/* delay for a while for settling down */
844  		udelay(100);
845  
846  		/* enable osc for measurement */
847  		value |= FIELD_PREP(FREQC_CTRL_OSC_CTRL, FREQC_CTRL_OSC_EN);
848  		writel(value, base);
849  		ret = readl_poll_timeout(base, value, value & FREQC_CTRL_STATUS, 1000);
850  		if (ret)
851  			return -1;
852  
853  		/* the result is represented in T count, will translate to pico-second later */
854  		sum += FIELD_GET(FREQC_CTRL_RESULT, value);
855  	}
856  
857  	/* return the DLY32 value in pico-second */
858  	return (2560000 / (int)(sum >> DLY32_AVERAGE_COUNT_LOG2));
859  }
860  
ast2600_init_dly32_lookup(struct ast2600_clk_priv * priv)861  static void ast2600_init_dly32_lookup(struct ast2600_clk_priv *priv)
862  {
863  	struct ast2600_scu *scu = priv->scu;
864  	int i;
865  
866  	for (i = 0; i < DLY32_NUM_OF_TAPS; i++) {
867  		priv->dly32_lookup[0][i] = ast2600_calc_dly32_time(scu, 0, i);
868  		priv->dly32_lookup[1][i] = ast2600_calc_dly32_time(scu, 1, i);
869  	}
870  
871  #ifdef DEBUG
872  	for (i = 0; i < DLY32_NUM_OF_TAPS; i++)
873  		printf("28nm DLY32[%d] = %d ps\n", i, priv->dly32_lookup[0][i]);
874  
875  	for (i = 0; i < DLY32_NUM_OF_TAPS; i++)
876  		printf("55nm DLY32[%d] = %d ps\n", i, priv->dly32_lookup[1][i]);
877  #endif
878  }
879  
880  /**
881   * @brief find the DLY32 tap number fitting the target delay time
882   *
883   * @param target_pico_sec target delay time in pico-second
884   * @param lookup DLY32 lookup table
885   * @return int DLY32 tap number
886   */
ast2600_find_dly32_tap(int target_pico_sec,int * lookup)887  static int ast2600_find_dly32_tap(int target_pico_sec, int *lookup)
888  {
889  	int i;
890  	bool found = false;
891  
892  	for (i = 0; i < DLY32_NUM_OF_TAPS; i++) {
893  		if (lookup[i] >= target_pico_sec) {
894  			found = true;
895  			break;
896  		}
897  	}
898  
899  	if (!found)
900  		return -1;
901  
902  	return i;
903  }
904  
ast2600_configure_mac12_clk(struct ast2600_clk_priv * priv,struct udevice * dev)905  static u32 ast2600_configure_mac12_clk(struct ast2600_clk_priv *priv, struct udevice *dev)
906  {
907  	struct ast2600_scu *scu = priv->scu;
908  	struct mac_delay_config mac1_cfg, mac2_cfg;
909  	u32 reg[3];
910  	int ret;
911  
912  	reg[0] = MAC_DEF_DELAY_1G;
913  	reg[1] = MAC_DEF_DELAY_100M;
914  	reg[2] = MAC_DEF_DELAY_10M;
915  
916  	ret = ast2600_find_dly32_tap(RGMII12_CLK_OUTPUT_DELAY_PS, priv->dly32_lookup[0]);
917  	if (ret > 0) {
918  		debug("suggested tx delay for mac1/2: %d\n", priv->dly32_lookup[0][ret]);
919  
920  		reg[0] &= ~(MAC_CLK_1G_OUTPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_2);
921  		reg[0] |= FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, ret) |
922  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, ret);
923  		reg[1] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
924  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) |
925  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret);
926  		reg[2] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
927  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) |
928  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret);
929  	}
930  	ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg,
931  				 sizeof(mac1_cfg) / sizeof(u32));
932  	if (!ret) {
933  		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_1);
934  		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, mac1_cfg.rx_delay_1000) |
935  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, mac1_cfg.tx_delay_1000);
936  
937  		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
938  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac1_cfg.rx_delay_100) |
939  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac1_cfg.tx_delay_100);
940  
941  		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
942  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac1_cfg.rx_delay_10) |
943  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac1_cfg.tx_delay_10);
944  	}
945  
946  	ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg,
947  				 sizeof(mac2_cfg) / sizeof(u32));
948  	if (!ret) {
949  		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_2 | MAC_CLK_1G_OUTPUT_DELAY_2);
950  		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, mac2_cfg.rx_delay_1000) |
951  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, mac2_cfg.tx_delay_1000);
952  
953  		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
954  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac2_cfg.rx_delay_100) |
955  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac2_cfg.tx_delay_100);
956  
957  		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
958  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac2_cfg.rx_delay_10) |
959  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac2_cfg.tx_delay_10);
960  	}
961  
962  	reg[0] |= (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0));
963  	writel(reg[0], &scu->mac12_clk_delay);
964  	writel(reg[1], &scu->mac12_clk_delay_100M);
965  	writel(reg[2], &scu->mac12_clk_delay_10M);
966  
967  	/* MAC AHB = HPLL / 6 */
968  	clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16));
969  
970  	return 0;
971  }
972  
ast2600_configure_mac34_clk(struct ast2600_clk_priv * priv,struct udevice * dev)973  static u32 ast2600_configure_mac34_clk(struct ast2600_clk_priv *priv, struct udevice *dev)
974  {
975  	struct ast2600_scu *scu = priv->scu;
976  	struct mac_delay_config mac3_cfg, mac4_cfg;
977  	u32 reg[3];
978  	int ret;
979  
980  	reg[0] = MAC34_DEF_DELAY_1G;
981  	reg[1] = MAC34_DEF_DELAY_100M;
982  	reg[2] = MAC34_DEF_DELAY_10M;
983  
984  	ret = ast2600_find_dly32_tap(RGMII34_CLK_OUTPUT_DELAY_PS, priv->dly32_lookup[1]);
985  	if (ret > 0) {
986  		debug("suggested tx delay for mac3/4: %d\n", priv->dly32_lookup[1][ret]);
987  
988  		reg[0] &= ~(MAC_CLK_1G_OUTPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_2);
989  		reg[0] |= FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, ret) |
990  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, ret);
991  		reg[1] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
992  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) |
993  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret);
994  		reg[2] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
995  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) |
996  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret);
997  	}
998  
999  	ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32));
1000  	if (!ret) {
1001  		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_1);
1002  		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, mac3_cfg.rx_delay_1000) |
1003  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, mac3_cfg.tx_delay_1000);
1004  
1005  		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
1006  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac3_cfg.rx_delay_100) |
1007  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac3_cfg.tx_delay_100);
1008  
1009  		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1);
1010  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac3_cfg.rx_delay_10) |
1011  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac3_cfg.tx_delay_10);
1012  	}
1013  
1014  	ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32));
1015  	if (!ret) {
1016  		reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_2 | MAC_CLK_1G_OUTPUT_DELAY_2);
1017  		reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, mac4_cfg.rx_delay_1000) |
1018  			  FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, mac4_cfg.tx_delay_1000);
1019  
1020  		reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
1021  		reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac4_cfg.rx_delay_100) |
1022  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac4_cfg.tx_delay_100);
1023  
1024  		reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2);
1025  		reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac4_cfg.rx_delay_10) |
1026  			  FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac4_cfg.tx_delay_10);
1027  	}
1028  
1029  	reg[0] |= (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0));
1030  	reg[0] &= ~MAC_CLK_RGMII_125M_SRC_SEL;
1031  	reg[0] |= FIELD_PREP(MAC_CLK_RGMII_125M_SRC_SEL, MAC_CLK_RGMII_125M_SRC_PAD_RGMIICK);
1032  	writel(reg[0], &scu->mac34_clk_delay);
1033  	writel(reg[1], &scu->mac34_clk_delay_100M);
1034  	writel(reg[2], &scu->mac34_clk_delay_10M);
1035  
1036  	/*
1037  	 * clock source seletion and divider
1038  	 * scu310[26:24] : MAC AHB bus clock = HCLK / 2
1039  	 * scu310[18:16] : RMII 50M = HCLK_200M / 4
1040  	 */
1041  	clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)),
1042  			((0x0 << 24) | (0x3 << 16)));
1043  
1044  	/*
1045  	 * set driving strength
1046  	 * scu458[3:2] : MAC4 driving strength
1047  	 * scu458[1:0] : MAC3 driving strength
1048  	 */
1049  	clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0),
1050  			(0x3 << 2) | (0x3 << 0));
1051  
1052  	return 0;
1053  }
1054  
1055  /**
1056   * ast2600 RGMII clock source tree
1057   * 125M from external PAD -------->|\
1058   * HPLL -->|\                      | |---->RGMII 125M for MAC#1 & MAC#2
1059   *         | |---->| divider |---->|/                             +
1060   * EPLL -->|/                                                     |
1061   *                                                                |
1062   * +---------<-----------|RGMIICK PAD output enable|<-------------+
1063   * |
1064   * +--------------------------->|\
1065   *                              | |----> RGMII 125M for MAC#3 & MAC#4
1066   * HCLK 200M ---->|divider|---->|/
1067   * To simplify the control flow:
1068   * 1. RGMII 1/2 always use EPLL as the internal clock source
1069   * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source
1070   * 125M from external PAD -------->|\
1071   *                                 | |---->RGMII 125M for MAC#1 & MAC#2
1072   *         EPLL---->| divider |--->|/                             +
1073   *                                                                |
1074   * +<--------------------|RGMIICK PAD output enable|<-------------+
1075   * |
1076   * +--------------------------->RGMII 125M for MAC#3 & MAC#4
1077   */
1078  #define RGMIICK_SRC_PAD		0
1079  #define RGMIICK_SRC_EPLL	1 /* recommended */
1080  #define RGMIICK_SRC_HPLL	2
1081  
1082  #define RGMIICK_DIV2	1
1083  #define RGMIICK_DIV3	2
1084  #define RGMIICK_DIV4	3
1085  #define RGMIICK_DIV5	4
1086  #define RGMIICK_DIV6	5
1087  #define RGMIICK_DIV7	6
1088  #define RGMIICK_DIV8	7 /* recommended */
1089  
1090  #define RMIICK_DIV4		0
1091  #define RMIICK_DIV8		1
1092  #define RMIICK_DIV12	2
1093  #define RMIICK_DIV16	3
1094  #define RMIICK_DIV20	4 /* recommended */
1095  #define RMIICK_DIV24	5
1096  #define RMIICK_DIV28	6
1097  #define RMIICK_DIV32	7
1098  
1099  struct ast2600_mac_clk_div {
1100  	u32 src; /* 0=external PAD, 1=internal PLL */
1101  	u32 fin; /* divider input speed */
1102  	u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */
1103  	u32 fout; /* fout = fin / n */
1104  };
1105  
1106  struct ast2600_mac_clk_div rgmii_clk_defconfig = {
1107  	.src = ASPEED_CLK_EPLL,
1108  	.fin = 1000000000,
1109  	.n = RGMIICK_DIV8,
1110  	.fout = 125000000,
1111  };
1112  
1113  struct ast2600_mac_clk_div rmii_clk_defconfig = {
1114  	.src = ASPEED_CLK_EPLL,
1115  	.fin = 1000000000,
1116  	.n = RMIICK_DIV20,
1117  	.fout = 50000000,
1118  };
1119  
ast2600_init_mac_pll(struct ast2600_scu * p_scu,struct ast2600_mac_clk_div * p_cfg)1120  static void ast2600_init_mac_pll(struct ast2600_scu *p_scu,
1121  				 struct ast2600_mac_clk_div *p_cfg)
1122  {
1123  	struct ast2600_pll_desc pll;
1124  
1125  	pll.in = AST2600_CLK_IN;
1126  	pll.out = p_cfg->fin;
1127  	if (ast2600_search_clock_config(&pll) == false) {
1128  		pr_err("unable to find valid ETHNET MAC clock setting\n");
1129  		debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w,
1130  		      pll.cfg.ext_reg);
1131  		debug("%s: pll cfg = %02x %02x %02x\n", __func__,
1132  		      pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p);
1133  		return;
1134  	}
1135  	ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src);
1136  }
1137  
ast2600_init_rgmii_clk(struct ast2600_scu * p_scu,struct ast2600_mac_clk_div * p_cfg)1138  static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu,
1139  				   struct ast2600_mac_clk_div *p_cfg)
1140  {
1141  	u32 reg_304 = readl(&p_scu->clk_sel2);
1142  	u32 reg_340 = readl(&p_scu->mac12_clk_delay);
1143  	u32 reg_350 = readl(&p_scu->mac34_clk_delay);
1144  
1145  	reg_340 &= ~(MAC_CLK_RGMII_125M_SRC_SEL | MAC_CLK_RMII2_50M_RCLK_O_CTRL |
1146  		     MAC_CLK_RMII1_50M_RCLK_O_CTRL | MAC_CLK_RGMIICK_PAD_DIR);
1147  	/* RGMIICK PAD output enable (to MAC 3/4) */
1148  	reg_340 |= FIELD_PREP(MAC_CLK_RGMIICK_PAD_DIR, MAC_CLK_RGMIICK_PAD_DIR_OUTPUT);
1149  	if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
1150  		/*
1151  		 * re-init PLL if the current PLL output frequency doesn't match
1152  		 * the divider setting
1153  		 */
1154  		if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
1155  			ast2600_init_mac_pll(p_scu, p_cfg);
1156  		/* select RGMII 125M from internal source */
1157  		reg_340 |= FIELD_PREP(MAC_CLK_RGMII_125M_SRC_SEL, MAC_CLK_RGMII_125M_SRC_PLL);
1158  	}
1159  
1160  	reg_304 &= ~GENMASK(23, 20);
1161  
1162  	/* set clock divider */
1163  	reg_304 |= (p_cfg->n & 0x7) << 20;
1164  
1165  	/* select internal clock source */
1166  	if (p_cfg->src == ASPEED_CLK_HPLL)
1167  		reg_304 |= BIT(23);
1168  
1169  	/* RGMII 3/4 clock source select */
1170  	reg_350 &= ~BIT(31);
1171  
1172  	writel(reg_304, &p_scu->clk_sel2);
1173  	writel(reg_340, &p_scu->mac12_clk_delay);
1174  	writel(reg_350, &p_scu->mac34_clk_delay);
1175  }
1176  
1177  /**
1178   * ast2600 RMII/NCSI clock source tree
1179   * HPLL -->|\
1180   *         | |---->| divider |----> RMII 50M for MAC#1 & MAC#2
1181   * EPLL -->|/
1182   * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4
1183   */
ast2600_init_rmii_clk(struct ast2600_scu * p_scu,struct ast2600_mac_clk_div * p_cfg)1184  static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu,
1185  				  struct ast2600_mac_clk_div *p_cfg)
1186  {
1187  	u32 reg_304;
1188  	u32 reg_310;
1189  
1190  	if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) {
1191  		/*
1192  		 * re-init PLL if the current PLL output frequency doesn't match
1193  		 * the divider setting
1194  		 */
1195  		if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src))
1196  			ast2600_init_mac_pll(p_scu, p_cfg);
1197  	}
1198  
1199  	reg_304 = readl(&p_scu->clk_sel2);
1200  	reg_310 = readl(&p_scu->clk_sel4);
1201  
1202  	reg_304 &= ~GENMASK(19, 16);
1203  
1204  	/* set RMII 1/2 clock divider */
1205  	reg_304 |= (p_cfg->n & 0x7) << 16;
1206  
1207  	/* RMII clock source selection */
1208  	if (p_cfg->src == ASPEED_CLK_HPLL)
1209  		reg_304 |= BIT(19);
1210  
1211  	/* set RMII 3/4 clock divider */
1212  	reg_310 &= ~GENMASK(18, 16);
1213  	reg_310 |= (0x3 << 16);
1214  
1215  	writel(reg_304, &p_scu->clk_sel2);
1216  	writel(reg_310, &p_scu->clk_sel4);
1217  }
1218  
ast2600_configure_mac(struct ast2600_scu * scu,int index)1219  static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index)
1220  {
1221  	u32 reset_bit;
1222  	u32 clkstop_bit;
1223  
1224  	switch (index) {
1225  	case 1:
1226  		reset_bit = BIT(ASPEED_RESET_MAC1);
1227  		clkstop_bit = BIT(SCU_CLKSTOP_MAC1);
1228  		writel(reset_bit, &scu->sysreset_ctrl1);
1229  		udelay(100);
1230  		writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1231  		mdelay(10);
1232  		writel(reset_bit, &scu->sysreset_clr_ctrl1);
1233  		break;
1234  	case 2:
1235  		reset_bit = BIT(ASPEED_RESET_MAC2);
1236  		clkstop_bit = BIT(SCU_CLKSTOP_MAC2);
1237  		writel(reset_bit, &scu->sysreset_ctrl1);
1238  		udelay(100);
1239  		writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1240  		mdelay(10);
1241  		writel(reset_bit, &scu->sysreset_clr_ctrl1);
1242  		break;
1243  	case 3:
1244  		reset_bit = BIT(ASPEED_RESET_MAC3 - 32);
1245  		clkstop_bit = BIT(SCU_CLKSTOP_MAC3);
1246  		writel(reset_bit, &scu->sysreset_ctrl2);
1247  		udelay(100);
1248  		writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
1249  		mdelay(10);
1250  		writel(reset_bit, &scu->sysreset_clr_ctrl2);
1251  		break;
1252  	case 4:
1253  		reset_bit = BIT(ASPEED_RESET_MAC4 - 32);
1254  		clkstop_bit = BIT(SCU_CLKSTOP_MAC4);
1255  		writel(reset_bit, &scu->sysreset_ctrl2);
1256  		udelay(100);
1257  		writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
1258  		mdelay(10);
1259  		writel(reset_bit, &scu->sysreset_clr_ctrl2);
1260  		break;
1261  	default:
1262  		return -EINVAL;
1263  	}
1264  
1265  	return 0;
1266  }
1267  
1268  #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK	BIT(19)
1269  #define SCU_CLK_ECC_RSA_CLK_MASK		GENMASK(27, 26)
1270  #define SCU_CLK_ECC_RSA_CLK_DIV(x)		((x) << 26)
ast2600_configure_rsa_ecc_clk(struct ast2600_scu * scu)1271  static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu)
1272  {
1273  	u32 clk_sel = readl(&scu->clk_sel1);
1274  
1275  	/* Configure RSA clock = HPLL/4 */
1276  	clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK;
1277  	clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK;
1278  	clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3);
1279  
1280  	writel(clk_sel, &scu->clk_sel1);
1281  }
1282  
1283  #define SCU_CLKSTOP_SDIO 4
ast2600_enable_sdclk(struct ast2600_scu * scu)1284  static ulong ast2600_enable_sdclk(struct ast2600_scu *scu)
1285  {
1286  	u32 reset_bit;
1287  	u32 clkstop_bit;
1288  
1289  	reset_bit = BIT(ASPEED_RESET_SD - 32);
1290  	clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
1291  
1292  	writel(reset_bit, &scu->sysreset_ctrl2);
1293  
1294  	udelay(100);
1295  	//enable clk
1296  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
1297  	mdelay(10);
1298  	writel(reset_bit, &scu->sysreset_clr_ctrl2);
1299  
1300  	return 0;
1301  }
1302  
1303  #define SCU_CLKSTOP_EXTSD			31
1304  #define SCU_CLK_SD_MASK				(0x7 << 28)
1305  #define SCU_CLK_SD_DIV(x)			((x) << 28)
1306  #define SCU_CLK_SD_FROM_APLL_CLK	BIT(8)
1307  
ast2600_enable_extsdclk(struct ast2600_scu * scu)1308  static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu)
1309  {
1310  	u32 clk_sel = readl(&scu->clk_sel4);
1311  	u32 enableclk_bit;
1312  	u32 rate = 0;
1313  	u32 div = 0;
1314  	int i = 0;
1315  
1316  	enableclk_bit = BIT(SCU_CLKSTOP_EXTSD);
1317  
1318  	/* ast2600 sd controller max clk is 200Mhz :
1319  	 * use apll for clock source 800/4 = 200 : controller max is 200mhz
1320  	 */
1321  	rate = ast2600_get_apll_rate(scu);
1322  	for (i = 0; i < 8; i++) {
1323  		div = (i + 1) * 2;
1324  		if ((rate / div) <= 200000000)
1325  			break;
1326  	}
1327  	clk_sel &= ~SCU_CLK_SD_MASK;
1328  	clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK;
1329  	writel(clk_sel, &scu->clk_sel4);
1330  
1331  	//enable clk
1332  	setbits_le32(&scu->clk_sel4, enableclk_bit);
1333  
1334  	return 0;
1335  }
1336  
1337  #define SCU_CLKSTOP_EMMC 27
ast2600_enable_emmcclk(struct ast2600_scu * scu)1338  static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu)
1339  {
1340  	u32 reset_bit;
1341  	u32 clkstop_bit;
1342  
1343  	reset_bit = BIT(ASPEED_RESET_EMMC);
1344  	clkstop_bit = BIT(SCU_CLKSTOP_EMMC);
1345  
1346  	writel(reset_bit, &scu->sysreset_ctrl1);
1347  	udelay(100);
1348  	//enable clk
1349  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1350  	mdelay(10);
1351  	writel(reset_bit, &scu->sysreset_clr_ctrl1);
1352  
1353  	return 0;
1354  }
1355  
1356  #define SCU_CLKSTOP_EXTEMMC			15
1357  #define SCU_CLK_EMMC_MASK			(0x7 << 12)
1358  #define SCU_CLK_EMMC_DIV(x)			((x) << 12)
1359  #define SCU_CLK_EMMC_FROM_MPLL_CLK	BIT(11)
1360  
ast2600_enable_extemmcclk(struct ast2600_scu * scu)1361  static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu)
1362  {
1363  	u32 revision_id = readl(&scu->chip_id1);
1364  	u32 clk_sel = readl(&scu->clk_sel1);
1365  	u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC);
1366  	u32 rate = 0;
1367  	u32 div = 0;
1368  	int i = 0;
1369  
1370  	/*
1371  	 * ast2600 eMMC controller max clk is 200Mhz
1372  	 * HPll->1/2->|\
1373  	 *				|->SCU300[11]->SCU300[14:12][1/N] +
1374  	 * MPLL------>|/								  |
1375  	 * +----------------------------------------------+
1376  	 * |
1377  	 * +---------> EMMC12C[15:8][1/N]-> eMMC clk
1378  	 */
1379  	if (((revision_id & CHIP_REVISION_ID) >> 16)) {
1380  		//AST2600A1 : use mpll to be clk source
1381  		rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
1382  		for (i = 0; i < 8; i++) {
1383  			div = (i + 1) * 2;
1384  			if ((rate / div) <= 200000000)
1385  				break;
1386  		}
1387  
1388  		clk_sel &= ~SCU_CLK_EMMC_MASK;
1389  		clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK;
1390  		writel(clk_sel, &scu->clk_sel1);
1391  
1392  	} else {
1393  		//AST2600A0 : use hpll to be clk source
1394  		rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
1395  
1396  		for (i = 0; i < 8; i++) {
1397  			div = (i + 1) * 4;
1398  			if ((rate / div) <= 200000000)
1399  				break;
1400  		}
1401  
1402  		clk_sel &= ~SCU_CLK_EMMC_MASK;
1403  		clk_sel |= SCU_CLK_EMMC_DIV(i);
1404  		writel(clk_sel, &scu->clk_sel1);
1405  	}
1406  	setbits_le32(&scu->clk_sel1, enableclk_bit);
1407  
1408  	return 0;
1409  }
1410  
1411  #define SCU_CLKSTOP_FSICLK 30
1412  
ast2600_enable_fsiclk(struct ast2600_scu * scu)1413  static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu)
1414  {
1415  	u32 reset_bit;
1416  	u32 clkstop_bit;
1417  
1418  	reset_bit = BIT(ASPEED_RESET_FSI % 32);
1419  	clkstop_bit = BIT(SCU_CLKSTOP_FSICLK);
1420  
1421  	/* The FSI clock is shared between masters. If it's already on
1422  	 * don't touch it, as that will reset the existing master.
1423  	 */
1424  	if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) {
1425  		debug("%s: already running, not touching it\n", __func__);
1426  		return 0;
1427  	}
1428  
1429  	writel(reset_bit, &scu->sysreset_ctrl2);
1430  	udelay(100);
1431  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
1432  	mdelay(10);
1433  	writel(reset_bit, &scu->sysreset_clr_ctrl2);
1434  
1435  	return 0;
1436  }
1437  
ast2600_enable_usbahclk(struct ast2600_scu * scu)1438  static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu)
1439  {
1440  	u32 reset_bit;
1441  	u32 clkstop_bit;
1442  
1443  	reset_bit = BIT(ASPEED_RESET_EHCI_P1);
1444  	clkstop_bit = BIT(14);
1445  
1446  	writel(reset_bit, &scu->sysreset_ctrl1);
1447  	udelay(100);
1448  	writel(clkstop_bit, &scu->clk_stop_ctrl1);
1449  	mdelay(20);
1450  	writel(reset_bit, &scu->sysreset_clr_ctrl1);
1451  
1452  	return 0;
1453  }
1454  
ast2600_enable_usbbhclk(struct ast2600_scu * scu)1455  static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
1456  {
1457  	u32 reset_bit;
1458  	u32 clkstop_bit;
1459  
1460  	reset_bit = BIT(ASPEED_RESET_EHCI_P2);
1461  	clkstop_bit = BIT(7);
1462  
1463  	writel(reset_bit, &scu->sysreset_ctrl1);
1464  	udelay(100);
1465  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1466  	mdelay(20);
1467  
1468  	writel(reset_bit, &scu->sysreset_clr_ctrl1);
1469  
1470  	return 0;
1471  }
1472  
1473  /* also known as yclk */
ast2600_enable_haceclk(struct ast2600_scu * scu)1474  static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
1475  {
1476  	u32 reset_bit;
1477  	u32 clkstop_bit;
1478  
1479  	reset_bit = BIT(ASPEED_RESET_HACE);
1480  	clkstop_bit = BIT(13);
1481  
1482  	writel(reset_bit, &scu->sysreset_ctrl1);
1483  	udelay(100);
1484  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1485  	mdelay(20);
1486  
1487  	writel(reset_bit, &scu->sysreset_clr_ctrl1);
1488  
1489  	return 0;
1490  }
1491  
ast2600_enable_rsaeccclk(struct ast2600_scu * scu)1492  static ulong ast2600_enable_rsaeccclk(struct ast2600_scu *scu)
1493  {
1494  	u32 clkstop_bit;
1495  
1496  	clkstop_bit = BIT(24);
1497  
1498  	writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
1499  	mdelay(20);
1500  
1501  	return 0;
1502  }
1503  
ast2600_clk_enable(struct clk * clk)1504  static int ast2600_clk_enable(struct clk *clk)
1505  {
1506  	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
1507  
1508  	switch (clk->id) {
1509  	case ASPEED_CLK_GATE_MAC1CLK:
1510  		ast2600_configure_mac(priv->scu, 1);
1511  		break;
1512  	case ASPEED_CLK_GATE_MAC2CLK:
1513  		ast2600_configure_mac(priv->scu, 2);
1514  		break;
1515  	case ASPEED_CLK_GATE_MAC3CLK:
1516  		ast2600_configure_mac(priv->scu, 3);
1517  		break;
1518  	case ASPEED_CLK_GATE_MAC4CLK:
1519  		ast2600_configure_mac(priv->scu, 4);
1520  		break;
1521  	case ASPEED_CLK_GATE_SDCLK:
1522  		ast2600_enable_sdclk(priv->scu);
1523  		break;
1524  	case ASPEED_CLK_GATE_SDEXTCLK:
1525  		ast2600_enable_extsdclk(priv->scu);
1526  		break;
1527  	case ASPEED_CLK_GATE_EMMCCLK:
1528  		ast2600_enable_emmcclk(priv->scu);
1529  		break;
1530  	case ASPEED_CLK_GATE_EMMCEXTCLK:
1531  		ast2600_enable_extemmcclk(priv->scu);
1532  		break;
1533  	case ASPEED_CLK_GATE_FSICLK:
1534  		ast2600_enable_fsiclk(priv->scu);
1535  		break;
1536  	case ASPEED_CLK_GATE_USBPORT1CLK:
1537  		ast2600_enable_usbahclk(priv->scu);
1538  		break;
1539  	case ASPEED_CLK_GATE_USBPORT2CLK:
1540  		ast2600_enable_usbbhclk(priv->scu);
1541  		break;
1542  	case ASPEED_CLK_GATE_YCLK:
1543  		ast2600_enable_haceclk(priv->scu);
1544  		break;
1545  	case ASPEED_CLK_GATE_RSAECCCLK:
1546  		ast2600_enable_rsaeccclk(priv->scu);
1547  		break;
1548  	default:
1549  		pr_err("can't enable clk\n");
1550  		return -ENOENT;
1551  	}
1552  
1553  	return 0;
1554  }
1555  
1556  struct clk_ops ast2600_clk_ops = {
1557  	.get_rate = ast2600_clk_get_rate,
1558  	.set_rate = ast2600_clk_set_rate,
1559  	.enable = ast2600_clk_enable,
1560  };
1561  
ast2600_clk_probe(struct udevice * dev)1562  static int ast2600_clk_probe(struct udevice *dev)
1563  {
1564  	struct ast2600_clk_priv *priv = dev_get_priv(dev);
1565  	u32 uart_clk_source;
1566  
1567  	priv->scu = devfdt_get_addr_ptr(dev);
1568  	if (IS_ERR(priv->scu))
1569  		return PTR_ERR(priv->scu);
1570  
1571  	uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0);
1572  
1573  	if (uart_clk_source) {
1574  		if (uart_clk_source & GENMASK(5, 0))
1575  			setbits_le32(&priv->scu->clk_sel4,
1576  				     uart_clk_source & GENMASK(5, 0));
1577  		if (uart_clk_source & GENMASK(12, 6))
1578  			setbits_le32(&priv->scu->clk_sel5,
1579  				     uart_clk_source & GENMASK(12, 6));
1580  	}
1581  
1582  	ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig);
1583  	ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig);
1584  	ast2600_init_dly32_lookup(priv);
1585  	ast2600_configure_mac12_clk(priv, dev);
1586  	ast2600_configure_mac34_clk(priv, dev);
1587  	ast2600_configure_rsa_ecc_clk(priv->scu);
1588  
1589  	return 0;
1590  }
1591  
ast2600_clk_bind(struct udevice * dev)1592  static int ast2600_clk_bind(struct udevice *dev)
1593  {
1594  	int ret;
1595  
1596  	/* The reset driver does not have a device node, so bind it here */
1597  	ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
1598  	if (ret)
1599  		debug("Warning: No reset driver: ret=%d\n", ret);
1600  
1601  	return 0;
1602  }
1603  
1604  struct aspeed_clks {
1605  	ulong id;
1606  	const char *name;
1607  };
1608  
1609  static struct aspeed_clks aspeed_clk_names[] = {
1610  	{ ASPEED_CLK_HPLL, "hpll" },     { ASPEED_CLK_MPLL, "mpll" },
1611  	{ ASPEED_CLK_APLL, "apll" },     { ASPEED_CLK_EPLL, "epll" },
1612  	{ ASPEED_CLK_DPLL, "dpll" },     { ASPEED_CLK_AHB, "hclk" },
1613  	{ ASPEED_CLK_APB1, "pclk1" },    { ASPEED_CLK_APB2, "pclk2" },
1614  	{ ASPEED_CLK_BCLK, "bclk" },     { ASPEED_CLK_UARTX, "uxclk" },
1615  	{ ASPEED_CLK_HUARTX, "huxclk" },
1616  };
1617  
soc_clk_dump(void)1618  int soc_clk_dump(void)
1619  {
1620  	struct udevice *dev;
1621  	struct clk clk;
1622  	unsigned long rate;
1623  	int i, ret;
1624  
1625  	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
1626  					  &dev);
1627  	if (ret)
1628  		return ret;
1629  
1630  	printf("Clk\t\tHz\n");
1631  
1632  	for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
1633  		clk.id = aspeed_clk_names[i].id;
1634  		ret = clk_request(dev, &clk);
1635  		if (ret < 0) {
1636  			debug("%s clk_request() failed: %d\n", __func__, ret);
1637  			continue;
1638  		}
1639  
1640  		ret = clk_get_rate(&clk);
1641  		rate = ret;
1642  
1643  		clk_free(&clk);
1644  
1645  		if (ret == -ENOTSUPP) {
1646  			printf("clk ID %lu not supported yet\n",
1647  			       aspeed_clk_names[i].id);
1648  			continue;
1649  		}
1650  		if (ret < 0) {
1651  			printf("%s %lu: get_rate err: %d\n", __func__,
1652  			       aspeed_clk_names[i].id, ret);
1653  			continue;
1654  		}
1655  
1656  		printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name,
1657  		       aspeed_clk_names[i].id, rate);
1658  	}
1659  
1660  	return 0;
1661  }
1662  
1663  static const struct udevice_id ast2600_clk_ids[] = {
1664  	{
1665  		.compatible = "aspeed,ast2600-scu",
1666  	},
1667  	{}
1668  };
1669  
1670  U_BOOT_DRIVER(aspeed_scu) = {
1671  	.name = "aspeed_scu",
1672  	.id = UCLASS_CLK,
1673  	.of_match = ast2600_clk_ids,
1674  	.priv_auto_alloc_size = sizeof(struct ast2600_clk_priv),
1675  	.ops = &ast2600_clk_ops,
1676  	.bind = ast2600_clk_bind,
1677  	.probe = ast2600_clk_probe,
1678  };
1679