1ae3ed042SDavid Wu /* 2ae3ed042SDavid Wu * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd 3ae3ed042SDavid Wu * 4ae3ed042SDavid Wu * SPDX-License-Identifier: GPL-2.0+ 5ae3ed042SDavid Wu * 6ae3ed042SDavid Wu * Rockchip SARADC driver for U-Boot 7ae3ed042SDavid Wu */ 8ae3ed042SDavid Wu 9ae3ed042SDavid Wu #include <common.h> 10ae3ed042SDavid Wu #include <adc.h> 11ae3ed042SDavid Wu #include <clk.h> 12ae3ed042SDavid Wu #include <dm.h> 13ae3ed042SDavid Wu #include <errno.h> 14ae3ed042SDavid Wu #include <asm/io.h> 15ae3ed042SDavid Wu 16ae3ed042SDavid Wu #define SARADC_CTRL_CHN_MASK GENMASK(2, 0) 17ae3ed042SDavid Wu #define SARADC_CTRL_POWER_CTRL BIT(3) 18ae3ed042SDavid Wu #define SARADC_CTRL_IRQ_ENABLE BIT(5) 19ae3ed042SDavid Wu #define SARADC_CTRL_IRQ_STATUS BIT(6) 20ae3ed042SDavid Wu 21ae3ed042SDavid Wu #define SARADC_TIMEOUT (100 * 1000) 22ae3ed042SDavid Wu 23ae3ed042SDavid Wu struct rockchip_saradc_regs { 24ae3ed042SDavid Wu unsigned int data; 25ae3ed042SDavid Wu unsigned int stas; 26ae3ed042SDavid Wu unsigned int ctrl; 27ae3ed042SDavid Wu unsigned int dly_pu_soc; 28ae3ed042SDavid Wu }; 29ae3ed042SDavid Wu 30ae3ed042SDavid Wu struct rockchip_saradc_data { 31ae3ed042SDavid Wu int num_bits; 32ae3ed042SDavid Wu int num_channels; 33ae3ed042SDavid Wu unsigned long clk_rate; 34ae3ed042SDavid Wu }; 35ae3ed042SDavid Wu 36ae3ed042SDavid Wu struct rockchip_saradc_priv { 37ae3ed042SDavid Wu struct rockchip_saradc_regs *regs; 38ae3ed042SDavid Wu int active_channel; 39ae3ed042SDavid Wu const struct rockchip_saradc_data *data; 40ae3ed042SDavid Wu }; 41ae3ed042SDavid Wu 42ae3ed042SDavid Wu int rockchip_saradc_channel_data(struct udevice *dev, int channel, 43ae3ed042SDavid Wu unsigned int *data) 44ae3ed042SDavid Wu { 45ae3ed042SDavid Wu struct rockchip_saradc_priv *priv = dev_get_priv(dev); 46ae3ed042SDavid Wu struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 47ae3ed042SDavid Wu 48ae3ed042SDavid Wu if (channel != priv->active_channel) { 49*9b643e31SMasahiro Yamada pr_err("Requested channel is not active!"); 50ae3ed042SDavid Wu return -EINVAL; 51ae3ed042SDavid Wu } 52ae3ed042SDavid Wu 53ae3ed042SDavid Wu if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != 54ae3ed042SDavid Wu SARADC_CTRL_IRQ_STATUS) 55ae3ed042SDavid Wu return -EBUSY; 56ae3ed042SDavid Wu 57ae3ed042SDavid Wu /* Read value */ 58ae3ed042SDavid Wu *data = readl(&priv->regs->data); 59ae3ed042SDavid Wu *data &= uc_pdata->data_mask; 60ae3ed042SDavid Wu 61ae3ed042SDavid Wu /* Power down adc */ 62ae3ed042SDavid Wu writel(0, &priv->regs->ctrl); 63ae3ed042SDavid Wu 64ae3ed042SDavid Wu return 0; 65ae3ed042SDavid Wu } 66ae3ed042SDavid Wu 67ae3ed042SDavid Wu int rockchip_saradc_start_channel(struct udevice *dev, int channel) 68ae3ed042SDavid Wu { 69ae3ed042SDavid Wu struct rockchip_saradc_priv *priv = dev_get_priv(dev); 70ae3ed042SDavid Wu 71ae3ed042SDavid Wu if (channel < 0 || channel >= priv->data->num_channels) { 72*9b643e31SMasahiro Yamada pr_err("Requested channel is invalid!"); 73ae3ed042SDavid Wu return -EINVAL; 74ae3ed042SDavid Wu } 75ae3ed042SDavid Wu 76ae3ed042SDavid Wu /* 8 clock periods as delay between power up and start cmd */ 77ae3ed042SDavid Wu writel(8, &priv->regs->dly_pu_soc); 78ae3ed042SDavid Wu 79ae3ed042SDavid Wu /* Select the channel to be used and trigger conversion */ 80ae3ed042SDavid Wu writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | 81ae3ed042SDavid Wu SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl); 82ae3ed042SDavid Wu 83ae3ed042SDavid Wu priv->active_channel = channel; 84ae3ed042SDavid Wu 85ae3ed042SDavid Wu return 0; 86ae3ed042SDavid Wu } 87ae3ed042SDavid Wu 88ae3ed042SDavid Wu int rockchip_saradc_stop(struct udevice *dev) 89ae3ed042SDavid Wu { 90ae3ed042SDavid Wu struct rockchip_saradc_priv *priv = dev_get_priv(dev); 91ae3ed042SDavid Wu 92ae3ed042SDavid Wu /* Power down adc */ 93ae3ed042SDavid Wu writel(0, &priv->regs->ctrl); 94ae3ed042SDavid Wu 95ae3ed042SDavid Wu priv->active_channel = -1; 96ae3ed042SDavid Wu 97ae3ed042SDavid Wu return 0; 98ae3ed042SDavid Wu } 99ae3ed042SDavid Wu 100ae3ed042SDavid Wu int rockchip_saradc_probe(struct udevice *dev) 101ae3ed042SDavid Wu { 102ae3ed042SDavid Wu struct rockchip_saradc_priv *priv = dev_get_priv(dev); 103ae3ed042SDavid Wu struct clk clk; 104ae3ed042SDavid Wu int ret; 105ae3ed042SDavid Wu 106ae3ed042SDavid Wu ret = clk_get_by_index(dev, 0, &clk); 107ae3ed042SDavid Wu if (ret) 108ae3ed042SDavid Wu return ret; 109ae3ed042SDavid Wu 110ae3ed042SDavid Wu ret = clk_set_rate(&clk, priv->data->clk_rate); 111ae3ed042SDavid Wu if (IS_ERR_VALUE(ret)) 112ae3ed042SDavid Wu return ret; 113ae3ed042SDavid Wu 114ae3ed042SDavid Wu priv->active_channel = -1; 115ae3ed042SDavid Wu 116ae3ed042SDavid Wu return 0; 117ae3ed042SDavid Wu } 118ae3ed042SDavid Wu 119ae3ed042SDavid Wu int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) 120ae3ed042SDavid Wu { 121ae3ed042SDavid Wu struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 122ae3ed042SDavid Wu struct rockchip_saradc_priv *priv = dev_get_priv(dev); 123ae3ed042SDavid Wu struct rockchip_saradc_data *data; 124ae3ed042SDavid Wu 125ae3ed042SDavid Wu data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); 126ae3ed042SDavid Wu priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev); 127ae3ed042SDavid Wu if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) { 128*9b643e31SMasahiro Yamada pr_err("Dev: %s - can't get address!", dev->name); 129ae3ed042SDavid Wu return -ENODATA; 130ae3ed042SDavid Wu } 131ae3ed042SDavid Wu 132ae3ed042SDavid Wu priv->data = data; 133ae3ed042SDavid Wu uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; 134ae3ed042SDavid Wu uc_pdata->data_format = ADC_DATA_FORMAT_BIN; 135ae3ed042SDavid Wu uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; 136ae3ed042SDavid Wu uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; 137ae3ed042SDavid Wu 138ae3ed042SDavid Wu return 0; 139ae3ed042SDavid Wu } 140ae3ed042SDavid Wu 141ae3ed042SDavid Wu static const struct adc_ops rockchip_saradc_ops = { 142ae3ed042SDavid Wu .start_channel = rockchip_saradc_start_channel, 143ae3ed042SDavid Wu .channel_data = rockchip_saradc_channel_data, 144ae3ed042SDavid Wu .stop = rockchip_saradc_stop, 145ae3ed042SDavid Wu }; 146ae3ed042SDavid Wu 147ae3ed042SDavid Wu static const struct rockchip_saradc_data saradc_data = { 148ae3ed042SDavid Wu .num_bits = 10, 149ae3ed042SDavid Wu .num_channels = 3, 150ae3ed042SDavid Wu .clk_rate = 1000000, 151ae3ed042SDavid Wu }; 152ae3ed042SDavid Wu 153ae3ed042SDavid Wu static const struct rockchip_saradc_data rk3066_tsadc_data = { 154ae3ed042SDavid Wu .num_bits = 12, 155ae3ed042SDavid Wu .num_channels = 2, 156ae3ed042SDavid Wu .clk_rate = 50000, 157ae3ed042SDavid Wu }; 158ae3ed042SDavid Wu 159ae3ed042SDavid Wu static const struct rockchip_saradc_data rk3399_saradc_data = { 160ae3ed042SDavid Wu .num_bits = 10, 161ae3ed042SDavid Wu .num_channels = 6, 162ae3ed042SDavid Wu .clk_rate = 1000000, 163ae3ed042SDavid Wu }; 164ae3ed042SDavid Wu 165ae3ed042SDavid Wu static const struct udevice_id rockchip_saradc_ids[] = { 166ae3ed042SDavid Wu { .compatible = "rockchip,saradc", 167ae3ed042SDavid Wu .data = (ulong)&saradc_data }, 168ae3ed042SDavid Wu { .compatible = "rockchip,rk3066-tsadc", 169ae3ed042SDavid Wu .data = (ulong)&rk3066_tsadc_data }, 170ae3ed042SDavid Wu { .compatible = "rockchip,rk3399-saradc", 171ae3ed042SDavid Wu .data = (ulong)&rk3399_saradc_data }, 172ae3ed042SDavid Wu { } 173ae3ed042SDavid Wu }; 174ae3ed042SDavid Wu 175ae3ed042SDavid Wu U_BOOT_DRIVER(rockchip_saradc) = { 176ae3ed042SDavid Wu .name = "rockchip_saradc", 177ae3ed042SDavid Wu .id = UCLASS_ADC, 178ae3ed042SDavid Wu .of_match = rockchip_saradc_ids, 179ae3ed042SDavid Wu .ops = &rockchip_saradc_ops, 180ae3ed042SDavid Wu .probe = rockchip_saradc_probe, 181ae3ed042SDavid Wu .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, 182ae3ed042SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), 183ae3ed042SDavid Wu }; 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