1*40d1a31eSPatrice ChotardST DWC3 glue logic 2*40d1a31eSPatrice Chotard 3*40d1a31eSPatrice ChotardThis file documents the parameters for the dwc3-st driver. 4*40d1a31eSPatrice ChotardThis driver controls the glue logic used to configure the dwc3 core on 5*40d1a31eSPatrice ChotardSTiH407 based platforms. 6*40d1a31eSPatrice Chotard 7*40d1a31eSPatrice ChotardRequired properties: 8*40d1a31eSPatrice Chotard - compatible : must be "st,stih407-dwc3" 9*40d1a31eSPatrice Chotard - reg : glue logic base address and USB syscfg ctrl register offset 10*40d1a31eSPatrice Chotard - reg-names : should be "reg-glue" and "syscfg-reg" 11*40d1a31eSPatrice Chotard - st,syscon : should be phandle to system configuration node which 12*40d1a31eSPatrice Chotard encompasses the glue registers 13*40d1a31eSPatrice Chotard - resets : list of phandle and reset specifier pairs. There should be two entries, one 14*40d1a31eSPatrice Chotard for the powerdown and softreset lines of the usb3 IP 15*40d1a31eSPatrice Chotard - reset-names : list of reset signal names. Names should be "powerdown" and "softreset" 16*40d1a31eSPatrice Chotard 17*40d1a31eSPatrice Chotard - #address-cells, #size-cells : should be '1' if the device has sub-nodes 18*40d1a31eSPatrice Chotard with 'reg' property 19*40d1a31eSPatrice Chotard 20*40d1a31eSPatrice Chotard - pinctl-names : A pinctrl state named "default" must be defined 21*40d1a31eSPatrice Chotard 22*40d1a31eSPatrice Chotard - pinctrl-0 : Pin control group 23*40d1a31eSPatrice Chotard 24*40d1a31eSPatrice Chotard - ranges : allows valid 1:1 translation between child's address space and 25*40d1a31eSPatrice Chotard parent's address space 26*40d1a31eSPatrice Chotard 27*40d1a31eSPatrice ChotardSub-nodes: 28*40d1a31eSPatrice ChotardThe dwc3 core should be added as subnode to ST DWC3 glue as shown in the 29*40d1a31eSPatrice Chotardexample below. 30*40d1a31eSPatrice Chotard 31*40d1a31eSPatrice ChotardNB: The dr_mode property is NOT optional for this driver, as the default value 32*40d1a31eSPatrice Chotardis "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are 33*40d1a31eSPatrice Chotardeither "host" or "device". 34*40d1a31eSPatrice Chotard 35*40d1a31eSPatrice ChotardExample: 36*40d1a31eSPatrice Chotard 37*40d1a31eSPatrice Chotardst_dwc3: dwc3@8f94000 { 38*40d1a31eSPatrice Chotard status = "disabled"; 39*40d1a31eSPatrice Chotard compatible = "st,stih407-dwc3"; 40*40d1a31eSPatrice Chotard reg = <0x08f94000 0x1000>, <0x110 0x4>; 41*40d1a31eSPatrice Chotard reg-names = "reg-glue", "syscfg-reg"; 42*40d1a31eSPatrice Chotard st,syscfg = <&syscfg_core>; 43*40d1a31eSPatrice Chotard resets = <&powerdown STIH407_USB3_POWERDOWN>, 44*40d1a31eSPatrice Chotard <&softreset STIH407_MIPHY2_SOFTRESET>; 45*40d1a31eSPatrice Chotard reset-names = "powerdown", "softreset"; 46*40d1a31eSPatrice Chotard #address-cells = <1>; 47*40d1a31eSPatrice Chotard #size-cells = <1>; 48*40d1a31eSPatrice Chotard pinctrl-names = "default"; 49*40d1a31eSPatrice Chotard pinctrl-0 = <&pinctrl_usb3>; 50*40d1a31eSPatrice Chotard ranges; 51*40d1a31eSPatrice Chotard 52*40d1a31eSPatrice Chotard dwc3: dwc3@9900000 { 53*40d1a31eSPatrice Chotard compatible = "snps,dwc3"; 54*40d1a31eSPatrice Chotard reg = <0x09900000 0x100000>; 55*40d1a31eSPatrice Chotard interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; 56*40d1a31eSPatrice Chotard dr_mode = "host"; 57*40d1a31eSPatrice Chotard phy-names = "usb2-phy", "usb3-phy"; 58*40d1a31eSPatrice Chotard phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>; 59*40d1a31eSPatrice Chotard }; 60*40d1a31eSPatrice Chotard}; 61