1c7ba7bdcSDan Murphy* Texas Instruments - dp83867 Giga bit ethernet phy 2c7ba7bdcSDan Murphy 3c7ba7bdcSDan MurphyRequired properties: 4c7ba7bdcSDan Murphy - reg - The ID number for the phy, usually a small integer 5c7ba7bdcSDan Murphy - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h 6c7ba7bdcSDan Murphy for applicable values 7c7ba7bdcSDan Murphy - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 8c7ba7bdcSDan Murphy for applicable values 9c7ba7bdcSDan Murphy - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h 10c7ba7bdcSDan Murphy for applicable values 11fba725f4SJanine Hagemann - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to 12fba725f4SJanine Hagemann compensate for the board being designed with the lanes swapped. 13fba725f4SJanine Hagemann - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the 14fba725f4SJanine Hagemann TX/RX lanes. 15*0f347a00SJanine Hagemann - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h 16*0f347a00SJanine Hagemann for applicable values 17c7ba7bdcSDan Murphy 18c7ba7bdcSDan MurphyDefault child nodes are standard Ethernet PHY device 19c7ba7bdcSDan Murphynodes as described in doc/devicetree/bindings/net/ethernet.txt 20c7ba7bdcSDan Murphy 21c7ba7bdcSDan MurphyExample: 22c7ba7bdcSDan Murphy 23c7ba7bdcSDan Murphy ethernet-phy@0 { 24c7ba7bdcSDan Murphy reg = <0>; 25c7ba7bdcSDan Murphy ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 26c7ba7bdcSDan Murphy ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 27c7ba7bdcSDan Murphy ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 28fba725f4SJanine Hagemann enet-phy-lane-no-swap; 29*0f347a00SJanine Hagemann ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; 30c7ba7bdcSDan Murphy }; 31c7ba7bdcSDan Murphy 32c7ba7bdcSDan MurphyDatasheet can be found: 33c7ba7bdcSDan Murphyhttp://www.ti.com/product/DP83867IR/datasheet 34